Home
last modified time | relevance | path

Searched refs:mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_9_3_0_offset.h1335 #define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX … macro
H A Dmmhub_1_0_offset.h1319 #define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX … macro
H A Dmmhub_9_1_offset.h1351 #define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX … macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h1215 #define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX … macro
H A Dgc_9_2_1_offset.h1179 #define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX … macro
H A Dgc_9_1_offset.h1241 #define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX … macro