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Searched refs:mmio_base (Results 1 – 25 of 26) sorted by relevance

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/netbsd/sys/external/bsd/drm2/dist/drm/i915/gt/
H A Dintel_engine.h58 __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base))
68 lower_reg__((engine__)->mmio_base), \
69 upper_reg__((engine__)->mmio_base))
72 __ENGINE_REG_OP(read, (engine__), reg__((engine__)->mmio_base, (idx__)))
75 __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base), (val__))
H A Dintel_rc6.c74 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); in gen11_rc6_enable()
139 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); in gen9_rc6_enable()
203 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); in gen8_rc6_enable()
230 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); in gen6_rc6_enable()
355 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); in chv_rc6_enable()
382 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); in vlv_rc6_enable()
H A Dintel_ring_submission.c573 hwsp = RING_HWS_PGA_GEN6(engine->mmio_base); in set_hwsp()
575 hwsp = RING_HWS_PGA(engine->mmio_base); in set_hwsp()
596 RING_INSTPM(engine->mmio_base), in flush_cs_tlb()
619 RING_MI_MODE(engine->mmio_base), in stop_ring()
715 RING_CTL(engine->mmio_base), in xcs_resume()
752 const u32 base = engine->mmio_base; in reset_prepare()
1384 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); in load_pd_dir()
1388 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
1398 *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base)); in load_pd_dir()
1445 RING_PSMI_CTL(signaller->mmio_base)); in mi_set_context()
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H A Dintel_engine_cs.c312 engine->mmio_base = __engine_mmio_base(gt->i915, info->mmio_bases); in intel_engine_setup()
882 const u32 base = engine->mmio_base; in intel_engine_stop_cs()
978 u32 mmio_base = engine->mmio_base; in intel_engine_get_instdone() local
987 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); in intel_engine_get_instdone()
1005 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); in intel_engine_get_instdone()
1022 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); in intel_engine_get_instdone()
1039 if (I915_SELFTEST_ONLY(!engine->mmio_base)) in ring_is_idle()
1553 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base); in intel_engine_dump()
H A Dintel_workarounds.c1231 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), in icl_whitelist_build()
1234 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), in icl_whitelist_build()
1237 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), in icl_whitelist_build()
1305 const u32 base = engine->mmio_base; in intel_engine_apply_whitelist()
1477 RING_SEMA_WAIT_POLL(engine->mmio_base), in xcs_engine_wa_init()
H A Dselftest_lrc.c28 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
3776 i915_mmio_reg_offset(RING_START(engine->mmio_base)), in live_lrc_fixed()
3781 i915_mmio_reg_offset(RING_CTL(engine->mmio_base)), in live_lrc_fixed()
3786 i915_mmio_reg_offset(RING_HEAD(engine->mmio_base)), in live_lrc_fixed()
3791 i915_mmio_reg_offset(RING_TAIL(engine->mmio_base)), in live_lrc_fixed()
3796 i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)), in live_lrc_fixed()
3801 i915_mmio_reg_offset(RING_BBSTATE(engine->mmio_base)), in live_lrc_fixed()
3877 *cs++ = i915_mmio_reg_offset(RING_START(engine->mmio_base)); in __live_lrc_state()
3884 *cs++ = i915_mmio_reg_offset(RING_TAIL(engine->mmio_base)); in __live_lrc_state()
H A Dintel_engine_types.h297 u32 mmio_base; member
H A Dintel_reset.c498 const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base); in gen8_engine_reset_prepare()
535 RING_RESET_CTL(engine->mmio_base), in gen8_engine_reset_cancel()
H A Dselftest_workarounds.c105 const u32 base = engine->mmio_base; in read_nonprivs()
189 RING_NOPID(engine->mmio_base); in get_whitelist_reg()
H A Dintel_lrc.c558 const u32 base = engine->mmio_base; in set_offsets()
4393 u32 base = engine->mmio_base; in intel_execlists_submission_setup()
/netbsd/sys/external/bsd/drm2/dist/drm/i915/selftests/
H A Dintel_uncore.c197 i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset); in live_forcewake_ops()
198 u32 __iomem *reg = uncore->regs + engine->mmio_base + r->offset; in live_forcewake_ops()
/netbsd/sys/external/bsd/drm2/dist/drm/savage/
H A Dsavage_bci.c580 unsigned long mmio_base, fb_base, fb_size, aperture_base; in savage_driver_firstopen() local
592 mmio_base = fb_base + SAVAGE_FB_SIZE_S3; in savage_driver_firstopen()
614 mmio_base = pci_resource_start(dev->pdev, 0); in savage_driver_firstopen()
633 mmio_base = pci_resource_start(dev->pdev, 0); in savage_driver_firstopen()
642 ret = drm_legacy_addmap(dev, mmio_base, SAVAGE_MMIO_SIZE, in savage_driver_firstopen()
/netbsd/sys/external/bsd/drm/dist/shared-core/
H A Dsavage_bci.c563 unsigned long mmio_base, fb_base, fb_size, aperture_base; in savage_driver_firstopen() local
578 mmio_base = fb_base + SAVAGE_FB_SIZE_S3; in savage_driver_firstopen()
606 mmio_base = drm_get_resource_start(dev, 0); in savage_driver_firstopen()
626 mmio_base = drm_get_resource_start(dev, 0); in savage_driver_firstopen()
637 ret = drm_addmap(dev, mmio_base, SAVAGE_MMIO_SIZE, _DRM_REGISTERS, in savage_driver_firstopen()
H A Dmga_dma.c411 dev_priv->mmio_base = drm_get_resource_start(dev, 1); in mga_driver_load()
720 err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size, in mga_do_dma_bootstrap()
H A Dmga_drv.h116 u32 mmio_base; /**< Bus address of base of MMIO. */ member
/netbsd/sys/external/bsd/drm2/dist/drm/i915/gvt/
H A Dscheduler.c221 u32 ring_base = dev_priv->engine[ring_id]->mmio_base; in save_ring_hw_state()
579 ring_base = dev_priv->engine[workload->ring_id]->mmio_base; in update_vreg_in_ctx()
819 ring_base = dev_priv->engine[workload->ring_id]->mmio_base; in update_guest_context()
H A Dexeclist.c48 (gvt->dev_priv->engine[ring_id]->mmio_base + (offset))
H A Dhandlers.c165 if (engine->mmio_base == offset) in intel_gvt_render_mmio_to_ring_id()
533 ring_base = dev_priv->engine[ring_id]->mmio_base; in force_nonpriv_write()
1674 ring_base = dev_priv->engine[ring_id]->mmio_base; in mmio_read_from_hw()
/netbsd/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/device/
H A Dnouveau_nvkm_engine_device_base.c2969 u64 mmio_base, mmio_size; local
3002 mmio_base = device->func->resource_addr(device, 0);
3013 ret = -bus_space_map(mmiot, mmio_base, 0x102000, 0, &mmioh);
3031 map = ioremap(mmio_base, 0x102000);
3230 ret = -bus_space_map(mmiot, mmio_base, mmio_size,
3238 device->mmioaddr = mmio_base;
3241 device->pri = ioremap(mmio_base, mmio_size);
/netbsd/sys/external/bsd/drm2/dist/drm/mga/
H A Dmga_dma.c429 dev_priv->mmio_base = pci_resource_start(dev->pdev, 1); in mga_driver_load()
734 err = drm_legacy_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size, in mga_do_dma_bootstrap()
H A Dmga_drv.h133 resource_size_t mmio_base; /**< Bus address of base of MMIO. */ member
/netbsd/sys/external/bsd/drm2/dist/drm/i915/
H A Di915_gpu_error.c1182 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); in engine_record_registers()
1185 mmio = RING_HWS_PGA(engine->mmio_base); in engine_record_registers()
1205 u32 base = engine->mmio_base; in engine_record_registers()
H A Di915_perf.c1766 const u32 base = stream->engine->mmio_base; in alloc_noa_wait()
2353 RING_CONTEXT_CONTROL(ce->engine->mmio_base), in gen12_configure_oar_context()
H A Di915_reg.h409 #define GEN11_VCS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x88C)
411 #define GEN11_VCS_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x890)
415 #define GEN11_VECS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x201C)
417 #define GEN11_VECS_SFC_LOCK_ACK(engine) _MMIO((engine)->mmio_base + 0x2018)
419 #define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014)
/netbsd/sys/external/bsd/drm2/dist/drm/i915/gem/
H A Di915_gem_context.c1113 u32 base = engine->mmio_base; in emit_ppgtt_update()

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