/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64SVEInstrInfo.td | 512 defm : fma<nxv4f16, nxv4i1, "H">; 514 defm : fma<nxv4f32, nxv4i1, "S">; 1171 def : Pat<(nxv2i1 (extract_subvector (nxv4i1 PPR:$Ps), (i64 0))), 1208 def : Pat<(nxv4i1 (concat_vectors nxv2i1:$p1, nxv2i1:$p2)), 1210 def : Pat<(nxv8i1 (concat_vectors nxv4i1:$p1, nxv4i1:$p2)), 1472 def : Pat<(nxv4f16 (AArch64scvtf_mt (nxv4i1 PPR:$Pg), 1499 def : Pat<(nxv4f16 (AArch64ucvtf_mt (nxv4i1 PPR:$Pg), 1639 def : Pat<(AArch64ptest (nxv4i1 PPR:$pg), (nxv4i1 PPR:$src)), 1791 def : Pat<(nxv4i1 (and PPR:$Ps1, PPR:$Ps2)), 2012 defm Pat_Store_P4 : unpred_store_predicate<nxv4i1, STR_PXI>; [all …]
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H A D | SVEInstrFormats.td | 594 def : SVE_2_Op_Pat<nxv4i1, op, nxv4i1, nxv4i1, !cast<Instruction>(NAME # _S)>; 643 def : Pat<(i32 (op GPR32:$Rn, (nxv4i1 PPRAny:$Pg))), 693 …at<(i64 (combine_op GPR64:$Rn, (int_aarch64_sve_cntp_oneuse (nxv4i1 (SVEAllActive)), (nxv4i1 PPRAn… 768 def : SVE_2_Op_Pat<i64, int_op, nxv4i1, nxv4i1, !cast<Instruction>(NAME # _S)>; 1257 def : SVE_1_Op_Pat<nxv4i1, op, nxv4i1, !cast<Instruction>(NAME # _S)>; 1501 def : SVE_3_Op_Pat<nxv4i1, op, nxv4i1, nxv4i1, nxv4i1, !cast<Instruction>(NAME)>; 1507 def : SVE_2_Op_AllActive_Pat<nxv4i1, op_nopred, nxv4i1, nxv4i1, 4401 def : SVE_3_Op_Pat<nxv4i1, op, nxv4i1, nxv4i32, nxv2i64, !cast<Instruction>(NAME # _S)>; 4411 def : SVE_3_Op_Pat<nxv4i1, op, nxv4i1, nxv4i32, nxv2i64, !cast<Instruction>(NAME # _S)>; 4738 def : SVE_3_Op_Pat<nxv4i1, op, nxv4i1, nxv4f32, nxv4f32, !cast<Instruction>(NAME # _S)>; [all …]
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H A D | AArch64TargetTransformInfo.cpp | 630 { ISD::TRUNCATE, MVT::nxv4i1, MVT::nxv4i16, 1 }, in getCastInstrCost() 631 { ISD::TRUNCATE, MVT::nxv4i1, MVT::nxv4i32, 1 }, in getCastInstrCost() 632 { ISD::TRUNCATE, MVT::nxv4i1, MVT::nxv4i64, 2 }, in getCastInstrCost() 1712 { TTI::SK_Broadcast, MVT::nxv4i1, 1 }, in getShuffleCost() 1730 { TTI::SK_Reverse, MVT::nxv4i1, 1 }, in getShuffleCost()
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H A D | AArch64CallingConvention.td | 85 CCIfType<[nxv2i1, nxv4i1, nxv8i1, nxv16i1], 87 CCIfType<[nxv2i1, nxv4i1, nxv8i1, nxv16i1], 166 CCIfType<[nxv2i1, nxv4i1, nxv8i1, nxv16i1],
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H A D | AArch64RegisterInfo.td | 864 [ nxv16i1, nxv8i1, nxv4i1, nxv2i1 ], 16,
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H A D | AArch64ISelLowering.cpp | 284 addRegisterClass(MVT::nxv4i1, &AArch64::PPRRegClass); in AArch64TargetLowering() 1174 for (auto VT : {MVT::nxv16i1, MVT::nxv8i1, MVT::nxv4i1, MVT::nxv2i1}) { in AArch64TargetLowering() 1345 setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv4i1, MVT::nxv4i32); in AArch64TargetLowering() 17314 MaskVT = MVT::nxv4i1; in getPredicateForFixedLengthVector()
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H A D | AArch64ISelDAGToDAG.cpp | 4889 PredVT != MVT::nxv4i1 && PredVT != MVT::nxv2i1) in getPackedVectorTypeFromPredicateType()
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/netbsd/external/apache2/llvm/dist/llvm/include/llvm/Support/ |
H A D | MachineValueType.h | 177 nxv4i1 = 112, // n x 4 x i1 enumerator 519 case nxv4i1: in getVectorElementType() 756 case nxv4i1: in getVectorMinNumElements() 848 case nxv4i1: return TypeSize::Scalable(4); in getSizeInBits() 1259 if (NumElements == 4) return MVT::nxv4i1; in getScalableVectorVT()
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/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | ValueTypes.td | 144 def nxv4i1 : ValueType<4, 112>; // n x 4 x i1 vector value
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | ValueTypes.cpp | 396 case MVT::nxv4i1: in getTypeForEVT()
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/netbsd/external/apache2/llvm/dist/llvm/utils/TableGen/ |
H A D | CodeGenTarget.cpp | 176 case MVT::nxv4i1: return "MVT::nxv4i1"; in getEnumName()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
H A D | RISCVRegisterInfo.td | 337 defvar vbool16_t = nxv4i1;
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H A D | RISCVISelLowering.cpp | 94 MVT::nxv1i1, MVT::nxv2i1, MVT::nxv4i1, MVT::nxv8i1, in RISCVTargetLowering()
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/netbsd/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
H A D | IntrinsicsAArch64.td | 917 def llvm_nxv4i1_ty : LLVMType<nxv4i1>;
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