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Searched refs:range_bpg_offset (Results 1 – 6 of 6) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A Damdgpu_dcn20_dsc.c667 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset); in dsc_write_to_registers()
672 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset, in dsc_write_to_registers()
675 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset); in dsc_write_to_registers()
680 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset, in dsc_write_to_registers()
683 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset); in dsc_write_to_registers()
688 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset, in dsc_write_to_registers()
691 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset); in dsc_write_to_registers()
696 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset, in dsc_write_to_registers()
699 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset); in dsc_write_to_registers()
704 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset, in dsc_write_to_registers()
[all …]
/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dsc/
H A Ddscc_types.h40 int range_bpg_offset; member
H A Damdgpu_rc_calc_dpi.c95 dsc_cfg->rc_range_params[i].range_bpg_offset = 0x3f & rc->ofs[i]; in copy_rc_to_cfg()
/netbsd/sys/external/bsd/drm2/dist/include/drm/
H A Ddrm_dsc.h68 u8 range_bpg_offset; member
/netbsd/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_vdsc.c448 vdsc_cfg->rc_range_params[i].range_bpg_offset = in intel_dsc_compute_params()
449 rc_params->rc_range_params[i].range_bpg_offset & in intel_dsc_compute_params()
817 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << in intel_dsc_pps_configure()
/netbsd/sys/external/bsd/drm2/dist/drm/
H A Ddrm_dsc.c229 (dsc_cfg->rc_range_params[i].range_bpg_offset)); in drm_dsc_pps_payload_pack()