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Searched refs:stnt1h (Results 1 – 22 of 22) sorted by relevance

/netbsd/external/gpl3/gdb/dist/gas/testsuite/gas/aarch64/
H A Dsve1-extended-sve2.s101 stnt1h { z17.s }, p5, [z21.s, x27] label
102 stnt1h { z0.s }, p0, [z0.s, x0] label
103 stnt1h { z0.s }, p0, [z0.s] label
104 stnt1h { z0.s }, p0, [z0.s, xzr] label
105 stnt1h { z17.d }, p5, [z21.d, x27] label
106 stnt1h { z0.d }, p0, [z0.d, x0] label
107 stnt1h { z0.d }, p0, [z0.d] label
108 stnt1h { z0.d }, p0, [z0.d, xzr] label
H A Dillegal-sve2-sve1ext.l92 [^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z17\.s},p5,\[z21\.s,x27\]'
94 [^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.s},p0,\[z0\.s\]'
96 [^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z17\.d},p5,\[z21\.d,x27\]'
98 [^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.d},p0,\[z0\.d\]'
H A Dillegal-sve2.s1467 stnt1h { z0.d }, p0/m, [z0.d] label
1468 stnt1h { z32.d }, p0, [z0.d] label
1469 stnt1h { z0.d }, p8, [z0.d] label
1470 stnt1h { z0.d }, p0, [z32.d] label
1471 stnt1h { z0.d }, p0, [z0.d, sp] label
1472 stnt1h { z0.d }, p0, [z0.d, x32] label
1475 stnt1h { z0.s }, p0, [z0.d] label
1477 stnt1h { z32.s }, p0, [z0.s] label
1478 stnt1h { z0.s }, p8, [z0.s] label
1479 stnt1h { z0.s }, p0, [z32.s] label
[all …]
H A Dsve2.s1105 stnt1h { z17.s }, p5, [z21.s, x27] label
1106 stnt1h { z0.s }, p0, [z0.s, x0] label
1107 stnt1h { z0.s }, p0, [z0.s] label
1108 stnt1h { z0.s }, p0, [z0.s, xzr] label
1109 stnt1h { z17.d }, p5, [z21.d, x27] label
1110 stnt1h { z0.d }, p0, [z0.d, x0] label
1111 stnt1h { z0.d }, p0, [z0.d] label
1112 stnt1h { z0.d }, p0, [z0.d, xzr] label
H A Dsve2.d889 *[0-9a-f]+: e4db36b1 stnt1h {z17\.s}, p5, \[z21\.s, x27\]
890 *[0-9a-f]+: e4c02000 stnt1h {z0\.s}, p0, \[z0\.s, x0\]
891 *[0-9a-f]+: e4df2000 stnt1h {z0\.s}, p0, \[z0\.s, xzr\]
892 *[0-9a-f]+: e4df2000 stnt1h {z0\.s}, p0, \[z0\.s, xzr\]
893 *[0-9a-f]+: e49b36b1 stnt1h {z17\.d}, p5, \[z21\.d, x27\]
894 *[0-9a-f]+: e4802000 stnt1h {z0\.d}, p0, \[z0\.d, x0\]
895 *[0-9a-f]+: e49f2000 stnt1h {z0\.d}, p0, \[z0\.d, xzr\]
896 *[0-9a-f]+: e49f2000 stnt1h {z0\.d}, p0, \[z0\.d, xzr\]
H A Dillegal-sve2.l2250 [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1h {z0\.d},p0/m,\[z0\.d\]'
2254 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1h {z0\.d},p8,\[z0\.d\]'
2256 [^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,sp\]'
2258 [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `stnt1h {z0\.d},p0,\[z0…
2260 [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1h {z0\.s},p0,\[z0\.d\]'
2264 [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1h {z32\.s},p0,\[z0\…
2266 [^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1h {z0\.s},p0,\[z32\.s\]'
2268 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,x32\]'
H A Dsve-invalid.s90 stnt1h z0, p1/z, [x1]
120 stnt1h {z0}, p1/z, [x1]
562 stnt1h z0.h, p0, [x1,xzr,lsl #1]
H A Dsve.d33696 [^:]+: e490e000 stnt1h {z0.h}, p0, \[x0\]
33697 [^:]+: e490e000 stnt1h {z0.h}, p0, \[x0\]
33698 [^:]+: e490e000 stnt1h {z0.h}, p0, \[x0\]
33699 [^:]+: e490e000 stnt1h {z0.h}, p0, \[x0\]
33700 [^:]+: e490e000 stnt1h {z0.h}, p0, \[x0\]
33701 [^:]+: e490e001 stnt1h {z1.h}, p0, \[x0\]
33702 [^:]+: e490e001 stnt1h {z1.h}, p0, \[x0\]
33703 [^:]+: e490e001 stnt1h {z1.h}, p0, \[x0\]
33704 [^:]+: e490e001 stnt1h {z1.h}, p0, \[x0\]
33705 [^:]+: e490e001 stnt1h {z1.h}, p0, \[x0\]
[all …]
H A Dsve.s33705 stnt1h z0.h, p0, [x0,#0]
33706 stnt1h {z0.h}, p0, [x0,#0]
33709 stnt1h {z0.h}, p0, [x0]
33710 stnt1h z1.h, p0, [x0,#0]
33714 stnt1h {z1.h}, p0, [x0]
33715 stnt1h z31.h, p0, [x0,#0]
33719 stnt1h {z31.h}, p0, [x0]
33723 stnt1h {z0.h}, p2, [x0]
33727 stnt1h {z0.h}, p7, [x0]
33731 stnt1h {z0.h}, p0, [x3]
[all …]
H A Dsve-invalid.l558 .*: Error: index register xzr is not allowed at operand 3 -- `stnt1h z0\.h,p0,\[x1,xzr,lsl#1\]'
/netbsd/external/gpl3/gdb.old/dist/gas/testsuite/gas/aarch64/
H A Dsve1-extended-sve2.s101 stnt1h { z17.s }, p5, [z21.s, x27] label
102 stnt1h { z0.s }, p0, [z0.s, x0] label
103 stnt1h { z0.s }, p0, [z0.s] label
104 stnt1h { z0.s }, p0, [z0.s, xzr] label
105 stnt1h { z17.d }, p5, [z21.d, x27] label
106 stnt1h { z0.d }, p0, [z0.d, x0] label
107 stnt1h { z0.d }, p0, [z0.d] label
108 stnt1h { z0.d }, p0, [z0.d, xzr] label
H A Dillegal-sve2-sve1ext.l92 [^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z17\.s},p5,\[z21\.s,x27\]'
94 [^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.s},p0,\[z0\.s\]'
96 [^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z17\.d},p5,\[z21\.d,x27\]'
98 [^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.d},p0,\[z0\.d\]'
H A Dillegal-sve2.s1467 stnt1h { z0.d }, p0/m, [z0.d] label
1468 stnt1h { z32.d }, p0, [z0.d] label
1469 stnt1h { z0.d }, p8, [z0.d] label
1470 stnt1h { z0.d }, p0, [z32.d] label
1471 stnt1h { z0.d }, p0, [z0.d, sp] label
1472 stnt1h { z0.d }, p0, [z0.d, x32] label
1475 stnt1h { z0.s }, p0, [z0.d] label
1477 stnt1h { z32.s }, p0, [z0.s] label
1478 stnt1h { z0.s }, p8, [z0.s] label
1479 stnt1h { z0.s }, p0, [z32.s] label
[all …]
H A Dsve2.s1105 stnt1h { z17.s }, p5, [z21.s, x27] label
1106 stnt1h { z0.s }, p0, [z0.s, x0] label
1107 stnt1h { z0.s }, p0, [z0.s] label
1108 stnt1h { z0.s }, p0, [z0.s, xzr] label
1109 stnt1h { z17.d }, p5, [z21.d, x27] label
1110 stnt1h { z0.d }, p0, [z0.d, x0] label
1111 stnt1h { z0.d }, p0, [z0.d] label
1112 stnt1h { z0.d }, p0, [z0.d, xzr] label
H A Dsve2.d889 *[0-9a-f]+: e4db36b1 stnt1h {z17\.s}, p5, \[z21\.s, x27\]
890 *[0-9a-f]+: e4c02000 stnt1h {z0\.s}, p0, \[z0\.s, x0\]
891 *[0-9a-f]+: e4df2000 stnt1h {z0\.s}, p0, \[z0\.s, xzr\]
892 *[0-9a-f]+: e4df2000 stnt1h {z0\.s}, p0, \[z0\.s, xzr\]
893 *[0-9a-f]+: e49b36b1 stnt1h {z17\.d}, p5, \[z21\.d, x27\]
894 *[0-9a-f]+: e4802000 stnt1h {z0\.d}, p0, \[z0\.d, x0\]
895 *[0-9a-f]+: e49f2000 stnt1h {z0\.d}, p0, \[z0\.d, xzr\]
896 *[0-9a-f]+: e49f2000 stnt1h {z0\.d}, p0, \[z0\.d, xzr\]
H A Dillegal-sve2.l2250 [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1h {z0\.d},p0/m,\[z0\.d\]'
2254 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1h {z0\.d},p8,\[z0\.d\]'
2256 [^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,sp\]'
2258 [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `stnt1h {z0\.d},p0,\[z0…
2260 [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1h {z0\.s},p0,\[z0\.d\]'
2264 [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1h {z32\.s},p0,\[z0\…
2266 [^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1h {z0\.s},p0,\[z32\.s\]'
2268 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,x32\]'
H A Dsve-invalid.s90 stnt1h z0, p1/z, [x1]
120 stnt1h {z0}, p1/z, [x1]
562 stnt1h z0.h, p0, [x1,xzr,lsl #1]
H A Dsve.d33696 [^:]+: e490e000 stnt1h {z0.h}, p0, \[x0\]
33697 [^:]+: e490e000 stnt1h {z0.h}, p0, \[x0\]
33698 [^:]+: e490e000 stnt1h {z0.h}, p0, \[x0\]
33699 [^:]+: e490e000 stnt1h {z0.h}, p0, \[x0\]
33700 [^:]+: e490e000 stnt1h {z0.h}, p0, \[x0\]
33701 [^:]+: e490e001 stnt1h {z1.h}, p0, \[x0\]
33702 [^:]+: e490e001 stnt1h {z1.h}, p0, \[x0\]
33703 [^:]+: e490e001 stnt1h {z1.h}, p0, \[x0\]
33704 [^:]+: e490e001 stnt1h {z1.h}, p0, \[x0\]
33705 [^:]+: e490e001 stnt1h {z1.h}, p0, \[x0\]
[all …]
H A Dsve.s33705 stnt1h z0.h, p0, [x0,#0]
33706 stnt1h {z0.h}, p0, [x0,#0]
33709 stnt1h {z0.h}, p0, [x0]
33710 stnt1h z1.h, p0, [x0,#0]
33714 stnt1h {z1.h}, p0, [x0]
33715 stnt1h z31.h, p0, [x0,#0]
33719 stnt1h {z31.h}, p0, [x0]
33723 stnt1h {z0.h}, p2, [x0]
33727 stnt1h {z0.h}, p7, [x0]
33731 stnt1h {z0.h}, p0, [x3]
[all …]
H A Dsve-invalid.l558 .*: Error: index register xzr is not allowed at operand 3 -- `stnt1h z0\.h,p0,\[x1,xzr,lsl#1\]'
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SVEInstrInfo.td1046 defm STNT1H_ZRI : sve_mem_cstnt_si<0b01, "stnt1h", Z_h, ZPR16>;
1052 defm STNT1H_ZRR : sve_mem_cstnt_ss<0b01, "stnt1h", Z_h, ZPR16, GPR64NoXZRshifted16>;
2740 defm STNT1H_ZZR_S : sve2_mem_sstnt_vs_32_ptrs<0b011, "stnt1h", AArch64stnt1_scatter, nxv4i16>;
2744 defm STNT1H_ZZR_D : sve2_mem_sstnt_vs_64_ptrs<0b010, "stnt1h", AArch64stnt1_scatter, nxv2i16>;
H A DAArch64SchedA64FX.td3679 // [464] "stnt1h $Zt, $Pg, [$Rn, $Rm]";
3682 // [465] "stnt1h $Zt, $Pg, [$Rn, $imm4, mul vl]";