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Searched refs:tx_conf_write (Results 1 – 18 of 18) sorted by relevance

/netbsd/sys/arch/hpcmips/tx/
H A Dtx39power.c113 tx_conf_write(tc, TX39_POWERCTRL_REG, reg); in tx39power_attach()
122 tx_conf_write(tc, TX39_POWERCTRL_REG, reg); in tx39power_attach()
172 tx_conf_write(tc, TX39_INTRENABLE1_REG, 0); in tx39power_suspend_cpu()
173 tx_conf_write(tc, TX39_INTRENABLE2_REG, 0); in tx39power_suspend_cpu()
174 tx_conf_write(tc, TX39_INTRENABLE3_REG, 0); in tx39power_suspend_cpu()
175 tx_conf_write(tc, TX39_INTRENABLE4_REG, 0); in tx39power_suspend_cpu()
176 tx_conf_write(tc, TX39_INTRENABLE5_REG, 0); in tx39power_suspend_cpu()
178 tx_conf_write(tc, TX39_INTRENABLE7_REG, 0); in tx39power_suspend_cpu()
179 tx_conf_write(tc, TX39_INTRENABLE8_REG, 0); in tx39power_suspend_cpu()
187 tx_conf_write(tc, TX39_POWERCTRL_REG, reg); in tx39power_suspend_cpu()
[all …]
H A Dtx39spi.c78 tx_conf_write(tc, TX39_SPICTRL_REG, reg); in tx39spi_attach()
80 tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_SPIERRINT); in tx39spi_attach()
81 tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_SPIRCVINT); in tx39spi_attach()
82 tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_SPIEMPTYINT); in tx39spi_attach()
150 tx_conf_write(tc, TX39_SPITXHOLD_REG , w & 0xffff); in tx39spi_put_word()
160 tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_SPIRCVINT); in tx39spi_get_word()
174 tx_conf_write(tc, TX39_SPICTRL_REG, reg); in tx39spi_enable()
202 tx_conf_write(tc, TX39_SPICTRL_REG, reg); in tx39spi_word()
214 tx_conf_write(tc, TX39_SPICTRL_REG, reg); in tx39spi_phapol()
226 tx_conf_write(tc, TX39_SPICTRL_REG, reg); in tx39spi_clkpol()
[all …]
H A Dtx39icu.c270 tx_conf_write(tc, TX39_INTRCLEAR1_REG, in tx39icu_attach()
272 tx_conf_write(tc, TX39_INTRCLEAR2_REG, in tx39icu_attach()
274 tx_conf_write(tc, TX39_INTRCLEAR3_REG, in tx39icu_attach()
276 tx_conf_write(tc, TX39_INTRCLEAR4_REG, in tx39icu_attach()
278 tx_conf_write(tc, TX39_INTRCLEAR5_REG, in tx39icu_attach()
281 tx_conf_write(tc, TX39_INTRCLEAR7_REG, in tx39icu_attach()
283 tx_conf_write(tc, TX39_INTRCLEAR8_REG, in tx39icu_attach()
361 tx_conf_write(tc, ofs, reg); in TX_INTR()
468 tx_conf_write(tc, ofs, he_mask); in tx39_irqhigh_intr()
575 tx_conf_write(tc, ofs, reg); in tx_intr_establish()
[all …]
H A Dtx3912video.c159 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); in tx3912video_attach()
735 tx_conf_write(tc, TX3912_VIDEOCTRL8_REG, in tx3912video_clut_init()
738 tx_conf_write(tc, TX3912_VIDEOCTRL9_REG, in tx3912video_clut_init()
742 tx_conf_write(tc, TX3912_VIDEOCTRL10_REG, in tx3912video_clut_init()
745 tx_conf_write(tc, TX3912_VIDEOCTRL11_REG, in tx3912video_clut_init()
748 tx_conf_write(tc, TX3912_VIDEOCTRL12_REG, in tx3912video_clut_init()
751 tx_conf_write(tc, TX3912_VIDEOCTRL13_REG, in tx3912video_clut_init()
754 tx_conf_write(tc, TX3912_VIDEOCTRL14_REG, in tx3912video_clut_init()
761 tx_conf_write(tc, TX3912_VIDEOCTRL5_REG, in tx3912video_clut_init()
771 tx_conf_write(tc, TX3912_VIDEOCTRL6_REG, in tx3912video_clut_init()
[all …]
H A Dtx39clock.c120 tx_conf_write(tc, TX39_TIMERCONTROL_REG, 0); in tx39clock_attach()
125 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); in tx39clock_attach()
189 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); in __tx39timer_rtcfreeze()
228 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); in __tx39timer_rtcreset()
232 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); in __tx39timer_rtcreset()
264 tx_conf_write(tc, TX39_TIMERPERIODIC_REG, reg); in tx39clock_init()
271 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); in tx39clock_init()
308 tx_conf_write(tc, TX39_TIMERALARMHI_REG, t.t_hi); in tx39clock_alarm_refill()
309 tx_conf_write(tc, TX39_TIMERALARMLO_REG, t.t_lo); in tx39clock_alarm_refill()
H A Dtx39sib.c207 tx_conf_write(tc, TX39_SIBCTRL_REG, reg); in tx39sib_enable1()
215 tx_conf_write(tc, TX39_SIBDMACTRL_REG, reg); in tx39sib_enable1()
222 tx_conf_write(tc, TX39_SIBCTRL_REG, reg); in tx39sib_enable1()
234 tx_conf_write(tc, TX39_SIBCTRL_REG, reg); in tx39sib_enable2()
249 tx_conf_write(tc, TX39_SIBCTRL_REG, reg); in tx39sib_disable()
258 tx_conf_write(tc, TX39_SIBCTRL_REG, reg); in tx39sib_disable()
262 tx_conf_write(tc, TX39_SIBCTRL_REG, reg); in tx39sib_disable()
317 tx_conf_write(tc, TX39_INTRSTATUS1_REG, TX39_INTRSTATUS1_SIBSF0INT); in __txsibsf0_ready()
344 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg); in txsibsf0_reg_write()
362 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg); in txsibsf0_read()
H A Dtxcom.c320 tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg); in txcom_reset()
323 tx_conf_write(tc, ofs, 0); in txcom_reset()
350 tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg); in txcom_enable()
357 tx_conf_write(tc, ofs, reg); in txcom_enable()
363 tx_conf_write(tc, ofs, reg); in txcom_enable()
400 tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg); in txcom_disable()
435 tx_conf_write(tc, ofs, reg); in txcom_pulse_mode()
500 tx_conf_write(chip->sc_tc, ofs, reg); in txcom_setmode()
531 tx_conf_write(chip->sc_tc, ofs, reg); in txcom_setmode()
549 tx_conf_write(chip->sc_tc, ofs, reg1); in txcom_setbaudrate()
[all …]
H A Dtxcsbus.c280 tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg); in __txcsbus_alloc_cstag()
290 tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg); in __txcsbus_alloc_cstag()
299 tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg); in __txcsbus_alloc_cstag()
307 tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg); in __txcsbus_alloc_cstag()
326 tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg); in __txcsbus_alloc_cstag()
347 tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg); in __txcsbus_alloc_cstag()
H A Dtx39biu.c104 tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg); in tx39biu_attach()
156 tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg); in tx39biu_intr()
159 tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg); in tx39biu_intr()
H A Dtx39ir.c102 tx_conf_write(tc, TX39_IRCTRL1_REG, reg); in tx39ir_attach()
107 tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg); in tx39ir_attach()
H A Dtx39io.c235 tx_conf_write(tc, TX39_IOMFIODATAOUT_REG, reg); in mfio_out()
320 tx_conf_write(tc, TX39_IOCTRL_REG, reg); in tx391x_io_out()
400 tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg); in tx392x_io_out()
H A Dtx39var.h97 #define tx_conf_write(t, reg, val) ( \ macro
/netbsd/sys/arch/hpcmips/dev/
H A Ducbsnd.c274 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg); in ucbsnd_exec_output()
285 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg); in ucbsnd_exec_output()
289 tx_conf_write(tc, TX39_SIBCTRL_REG, in ucbsnd_exec_output()
299 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg); in ucbsnd_exec_output()
322 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg); in ucbsnd_exec_output()
362 tx_conf_write(tc, TX39_SIBSNDTXSTART_REG, in ucbsnd_exec_output()
366 tx_conf_write(tc, TX39_SIBSIZE_REG, in ucbsnd_exec_output()
374 tx_conf_write(tc, TX39_SIBDMACTRL_REG, reg); in ucbsnd_exec_output()
402 tx_conf_write(tc, TX39_SIBSNDHOLD_REG, in ucbsnd_exec_output()
428 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg); in ucbsnd_exec_output()
[all …]
H A Dteliosio.c265 tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg); in teliosio_mbu_write()
272 tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg); in teliosio_mbu_write()
290 tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg); in teliosio_mbu_read()
299 tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg); in teliosio_mbu_read()
H A Doptpoint.c165 tx_conf_write(tc, TX39_INTRCLEAR4_REG, in optpoint_intr()
190 tx_conf_write(tc, TX39_INTRCLEAR4_REG, TX39_INTRSTATUS4_OPTPOINTINT); in optpoint_intr()
284 tx_conf_write(tc, TX39_INTRCLEAR4_REG, TX39_INTRSTATUS4_OPTPOINTINT); in optpoint_initialize()
H A Ducbtp.c576 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg); in ucbtp_adc_async()
626 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg); in ucbtp_adc_async()
H A Dit8368.c568 tx_conf_write(sc->sc_tc, TX39_MEMCONFIG3_REG, reg32); in it8368_mode()
/netbsd/sys/arch/hpcmips/stand/pbsdboot/
H A Dtx39xx.c57 tx_conf_write(tx_chipset_tag_t t, int reg, u_int32_t val) in tx_conf_write() function