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Searched refs:v16i8 (Results 1 – 25 of 90) sorted by relevance

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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrAltivec.td876 def : Pat<(v16i8 (rotl v16i8:$vA, v16i8:$vB)),
877 (v16i8 (VRLB v16i8:$vA, v16i8:$vB))>;
960 def : Pat<(v16i8 (umax v16i8:$src1, v16i8:$src2)),
962 def : Pat<(v16i8 (smax v16i8:$src1, v16i8:$src2)),
1065 def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)),
1073 def : Pat<(v16i8 (PPCshl v16i8:$vA, v16i8:$vB)),
1082 def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)),
1090 def : Pat<(v16i8 (PPCsrl v16i8:$vA, v16i8:$vB)),
1099 def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)),
1105 def : Pat<(v16i8 (PPCsra v16i8:$vA, v16i8:$vB)),
[all …]
H A DPPCInstrPrefix.td1370 def : Pat<(v512i1 (int_ppc_mma_xvi4ger8 v16i8:$XA, v16i8:$XB)),
1375 def : Pat<(v512i1 (int_ppc_mma_xvi8ger4 v16i8:$XA, v16i8:$XB)),
1380 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2s v16i8:$XA, v16i8:$XB)),
1385 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2 v16i8:$XA, v16i8:$XB)),
1396 def : Pat<(v512i1 (int_ppc_mma_xvf32ger v16i8:$XA, v16i8:$XB)),
1417 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2 v16i8:$XA, v16i8:$XB)),
1427 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2 v16i8:$XA, v16i8:$XB)),
2562 def : Pat<(v16i8 (int_ppc_vsx_xvcvspbf16 v16i8:$XA)),
2564 def : Pat<(v16i8 (int_ppc_vsx_xvcvbf16spn v16i8:$XA)),
2686 def : Pat<(v16i8 (int_ppc_vsx_xxpermx v16i8:$A, v16i8:$B, v16i8:$C, timm:$D)),
[all …]
H A DPPCInstrVSX.td2112 dag LE_VDOUBLE_PERMUTE = (v16i8 (VPERM (v16i8 (COPY_TO_REGCLASS $S, VRRC)),
2200 dag BE_VDOUBLE_PERMUTE = (v16i8 (VPERM (v16i8 (COPY_TO_REGCLASS $S, VRRC)),
2486 def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor v16i8:$a,
2487 v16i8:$b, v16i8:$c)),
2491 def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor v16i8:$a,
2492 v16i8:$b, v16i8:$c)),
2682 def : Pat<(v16i8 (vselect v16i8:$vA, v16i8:$vB, v16i8:$vC)),
2973 (PPCvperm v16i8:$A, v16i8:$B, v16i8:$C)))), 0)),
3238 def : Pat<(v16i8 (bitconvert (v16i8 immAllOnesV))),
3513 v16i8, (i32 i32:$A),
[all …]
H A DREADME_P9.txt33 (set v16i8:$vD, (int_ppc_altivec_vinsertb v16i8:$vA, imm:$UIMM))
41 (set i64:$rD, (int_ppc_altivec_vclzlsbb v16i8:$vB))
42 (set i64:$rD, (int_ppc_altivec_vctzlsbb v16i8:$vB))
46 (set v16i8:$vD, (cttz v16i8:$vB)) // vctzb
108 VA1a_Int_Ty3<59, "vpermr", int_ppc_altivec_vpermr, v16i8, v16i8, v16i8>;
128 . VX1_Int_Ty<1860, "vslv", int_ppc_altivec_vslv, v16i8>;
129 VX1_Int_Ty<1796, "vsrv", int_ppc_altivec_vsrv, v16i8>;
484 (set v16i8:$XT, (int_ppc_vsx_xxperm v16i8:$XA, v16i8:$XB))
485 (set v16i8:$XT, (int_ppc_vsx_xxpermr v16i8:$XA, v16i8:$XB))
551 (set v16i8:$XT, (int_ppc_vsx_lxvb16x xoaddr:$src))
[all …]
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMInstrCDE.td588 def : Pat<(v16i8 (int_arm_cde_vcx1qa timm:$coproc, (v16i8 MQPR:$acc),
592 def : Pat<(v16i8 (int_arm_cde_vcx2q timm:$coproc, (v16i8 MQPR:$n), timm:$imm)),
594 def : Pat<(v16i8 (int_arm_cde_vcx2qa timm:$coproc, (v16i8 MQPR:$acc),
599 def : Pat<(v16i8 (int_arm_cde_vcx3q timm:$coproc, (v16i8 MQPR:$n),
603 def : Pat<(v16i8 (int_arm_cde_vcx3qa timm:$coproc, (v16i8 MQPR:$acc),
604 (v16i8 MQPR:$n), (v16i8 MQPR:$m),
626 (v16i8 MQPR:$n), timm:$imm,
642 (v16i8 MQPR:$n), (v16i8 MQPR:$m),
646 (v16i8 MQPR:$m),
652 (v16i8 MQPR:$n), (v16i8 MQPR:$m), timm:$imm,
[all …]
H A DARMInstrMVE.td2234 def : Pat<(v16i8 (ARMvshrsImm (addnsw (addnsw (v16i8 MQPR:$Qm), (v16i8 MQPR:$Qn)),
2246 def : Pat<(v16i8 (ARMvshruImm (addnuw (addnuw (v16i8 MQPR:$Qm), (v16i8 MQPR:$Qn)),
3183 def : Pat<(v16i8 (ARMvshlu (v16i8 MQPR:$Qm), (v16i8 MQPR:$Qn))),
3184 (v16i8 (MVE_VSHL_by_vecu8 (v16i8 MQPR:$Qm), (v16i8 MQPR:$Qn)))>;
3190 def : Pat<(v16i8 (ARMvshls (v16i8 MQPR:$Qm), (v16i8 MQPR:$Qn))),
3191 (v16i8 (MVE_VSHL_by_vecs8 (v16i8 MQPR:$Qm), (v16i8 MQPR:$Qn)))>;
5421 def : Pat<(v16i8 (ARMvshlu (v16i8 MQPR:$Qm), (v16i8 (ARMvdup rGPR:$Rm)))),
5428 def : Pat<(v16i8 (ARMvshls (v16i8 MQPR:$Qm), (v16i8 (ARMvdup rGPR:$Rm)))),
5463 def : Pat<(v16i8 ( bitreverse (v16i8 MQPR:$val1))),
6741 def : Pat<(v16i8 (vselect (v16i1 VCCR:$pred), (v16i8 MQPR:$v1), (v16i8 MQPR:$v2))),
[all …]
H A DARMCallingConv.td34 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
60 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
75 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
95 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
112 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
169 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
187 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
214 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
237 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
H A DARMTargetTransformInfo.cpp501 {ISD::TRUNCATE, MVT::v16i32, MVT::v16i8, 3}, in getCastInstrCost()
502 {ISD::TRUNCATE, MVT::v16i16, MVT::v16i8, 1}, in getCastInstrCost()
595 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
596 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
1159 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 1}}; in getShuffleCost()
1180 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 2}}; in getShuffleCost()
1204 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 32}}; in getShuffleCost()
1218 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 1}, in getShuffleCost()
1603 {ISD::ADD, MVT::v16i8, 1}, in getArithmeticReductionCost()
1659 LT.second == MVT::v16i8) { in getIntrinsicInstrCost()
[all …]
H A DARMInstrNEON.td3372 v16i8, v16i8, fc, Commutable>;
3476 v16i8, v16i8, OpNode, Commutable>;
3582 v16i8, v16i8, IntOp, Commutable>;
3596 v16i8, v16i8, IntOp>;
5496 def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 QPR:$src1),
5873 def : Pat<(v16i8 (ARMvshls (v16i8 QPR:$Dn), (v16i8 QPR:$Dm))),
5890 def : Pat<(v16i8 (ARMvshlu (v16i8 QPR:$Dn), (v16i8 QPR:$Dm))),
6138 v16i8, v16i8, ctpop>;
6631 def : Pat<(v16i8 (ARMvduplane (v16i8 QPR:$src), imm:$lane)),
7237 !strconcat("aes", op), "8", v16i8, v16i8, Int>;
[all …]
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp677 { ISD::SHL, MVT::v16i8, 1 }, in getArithmeticInstrCost()
678 { ISD::SRL, MVT::v16i8, 2 }, in getArithmeticInstrCost()
679 { ISD::SRA, MVT::v16i8, 2 }, in getArithmeticInstrCost()
2299 { ISD::SETCC, MVT::v16i8, 1 }, in getCmpSelInstrCost()
2381 { ISD::CTLZ, MVT::v16i8, 4 }, in getTypeBasedIntrinsicInstrCost()
2670 { ISD::CTTZ, MVT::v16i8, 9 } in getTypeBasedIntrinsicInstrCost()
3036 { ISD::ROTR, MVT::v16i8, 2 } in getIntrinsicInstrCost()
3551 { ISD::ADD, MVT::v16i8, 3 }, in getArithmeticReductionCost()
3797 {ISD::UMIN, MVT::v16i8, 1}, in getMinMaxCost()
3804 {ISD::SMIN, MVT::v16i8, 1}, in getMinMaxCost()
[all …]
H A DX86InstrXOP.td126 defm VPROTB : xop3op<0x90, "vprotb", rotl, v16i8, SchedWriteVarVecShift.XMM>;
130 defm VPSHAB : xop3op<0x98, "vpshab", X86vpsha, v16i8, SchedWriteVarVecShift.XMM>;
134 defm VPSHLB : xop3op<0x94, "vpshlb", X86vpshl, v16i8, SchedWriteVarVecShift.XMM>;
157 defm VPROTB : xop3opimm<0xC0, "vprotb", X86vrotli, v16i8,
273 defm VPCOMB : xopvpcom<0xCC, "b", X86vpcom, v16i8, SchedWriteVecALU.XMM>;
277 defm VPCOMUB : xopvpcom<0xEC, "ub", X86vpcomu, v16i8, SchedWriteVecALU.XMM>;
305 (v16i8 (OpNode (vt128 VR128:$src1), (vt128 (load addr:$src2)),
323 defm VPPERM : xop4op<0xA3, "vpperm", X86vpperm, v16i8,
375 def : Pat<(v16i8 (or (and VR128:$src3, VR128:$src1),
H A DX86CallingConv.td110 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
142 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
187 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
229 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
236 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
550 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
555 CCIfType<[f32, f64, f128, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
697 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
771 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
790 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
[all …]
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td722 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^ADD(v16i8|v8i16|v4i32|v2i64)$")>;
724 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(AND|ORR|ORN|BIC|EOR)v16i8$")>;
726 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(NEG|SUB)(v16i8|v8i16|v4i32|v2i64)$")>;
734 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^ADDP(v4i32|v8i16|v16i8)$")>; // sz!=11
738 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^PMULL(v8i8|v16i8)$")>;
739 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^SHL(v16i8|v8i16|v4i32|v2i64)_shift$")>;
743 def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(S|U)ABD(v16i8|v8i16|v4i32|v2i64)$")>;
750 def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(SU|US)QADD(v16i8|v8i16|v4i32|v2i64)$")>;
772 def : InstRW<[FalkorWr_4VXVY_4cyc], (instregex "^(S|U)ABA(v16i8|v8i16|v4i32)$")>;
910 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^DUP(v16i8|v8i16)(gpr|lane)$")>;
[all …]
H A DAArch64InstrInfo.td5163 def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
5169 def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd),
5170 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
5529 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
6880 (v16i8 (int_aarch64_crypto_aese (v16i8 V128:$src1),
6882 (v16i8 (AESMCrrTied (v16i8 (AESErr (v16i8 V128:$src1),
6887 (v16i8 (int_aarch64_crypto_aesd (v16i8 V128:$src1),
6889 (v16i8 (AESIMCrrTied (v16i8 (AESDrr (v16i8 V128:$src1),
7141 def : Pat<(v16i8 (AArch64NvCast (v16i8 FPR128:$src))), (v16i8 FPR128:$src)>;
7701 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
[all …]
H A DAArch64SchedKryoDetails.td39 (instregex "(S|U)ABA(v16i8|v8i16|v4i32)")>;
75 (instregex "(S|U)ADALP(v16i8|v8i16|v4i32)_v.*")>;
165 (instregex "(S|U)H(ADD|SUB)(v16i8|v8i16|v4i32)")>;
291 (instregex "(S|U)SHL(v16i8|v8i16|v4i32|v2i64)$")>;
399 (instregex "ADDP(v16i8|v8i16|v4i32|v2i64)")>;
441 …(instregex "((AND|ORN|EOR|EON)S?(Xr[rsi]|v16i8|v8i16|v4i32)|(ORR|BIC)S?(Xr[rs]|v16i8|v8i16|v4i32))…
501 (instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>;
1674 (instregex "NEG(v16i8|v8i16|v4i32|v2i64)")>;
2335 (instregex "(TRN1|TRN2)(v4i32|v8i16|v16i8)")>;
2359 (instregex "(UZP1|UZP2)(v4i32|v8i16|v16i8)")>;
[all …]
H A DAArch64ISelDAGToDAG.cpp4225 } else if (VT == MVT::v16i8) { in Select()
4253 } else if (VT == MVT::v16i8) { in Select()
4281 } else if (VT == MVT::v16i8) { in Select()
4309 } else if (VT == MVT::v16i8) { in Select()
4337 } else if (VT == MVT::v16i8) { in Select()
4365 } else if (VT == MVT::v16i8) { in Select()
4393 } else if (VT == MVT::v16i8) { in Select()
4421 } else if (VT == MVT::v16i8) { in Select()
4449 } else if (VT == MVT::v16i8) { in Select()
4477 } else if (VT == MVT::v16i8) { in Select()
[all …]
H A DAArch64TargetTransformInfo.cpp244 static const auto ValidSatTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16, in getIntrinsicInstrCost()
624 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
656 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, in getCastInstrCost()
657 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, in getCastInstrCost()
658 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
659 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
690 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 21 }, in getCastInstrCost()
691 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 21 }, in getCastInstrCost()
1628 {ISD::ADD, MVT::v16i8, 1}, in getArithmeticReductionCost()
1652 { TTI::SK_Broadcast, MVT::v16i8, 1 }, in getShuffleCost()
[all …]
H A DAArch64SchedA57.td347 // Q form - v16i8, v8i16, v4i32
349 // Q form - v16i8, v8i16, v4i32, v2i64
386 def : InstRW<[A57Write_6cyc_2W_Mul_Forward], (instregex "^MUL(v16i8|v8i16|v4i32)(_indexed)?$")>;
388 def : InstRW<[A57Write_6cyc_2W], (instregex "^(PMUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>;
407 def : InstRW<[A57Write_5cyc_1W], (instregex "^PMULL(v8i8|v16i8)")>;
421 def : InstRW<[A57Write_4cyc_2X], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>;
427 def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>;
518 // Q form - v16i8, v8i16, v4i32
520 // Q form - v16i8, v8i16, v4i32, v2i64
523 def : InstRW<[A57Write_3cyc_2V], (instregex "^(BIF|BIT|BSL|BSP)v16i8")>;
[all …]
H A DAArch64CallingConvention.td35 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8],
115 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
123 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
140 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8],
159 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
241 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
257 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
278 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
300 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
361 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, f128], CCBitConvertToType<v2f64>>,
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.td60 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
80 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
124 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
131 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
136 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
199 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
246 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
249 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
275 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
284 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
H A DSystemZInstrVector.td49 def : VectorExtractSubreg<v16i8, VLGVB>;
280 def : Pat<(v16i8 (z_loadeswap bdxaddr12only:$addr)),
462 defm : GenericVectorOps<v16i8, v16i8>;
897 defm : BitwiseVectorOps<v16i8>;
1527 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
1528 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
1529 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
1530 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
1531 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
1532 def : Pat<(v16i8 (bitconvert (f128 VR128:$src))), (v16i8 VR128:$src)>;
[all …]
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td92 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>;
162 def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>;
166 def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>;
170 def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>;
174 def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>;
178 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
3885 (v16i8 (BCLR_B v16i8:$ws, v16i8:$wt))>;
3972 (i32 (vextract_sext_i8 v16i8:$ws, i64:$idx)),
3975 (SPLAT_B v16i8:$ws,
4010 (i32 (vextract_zext_i8 v16i8:$ws, i64:$idx)),
[all …]
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp68 .Case("v16i8", MVT::v16i8) in parseMVT()
137 case MVT::v16i8: in toValType()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp62 addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
134 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
162 for (auto T : {MVT::v16i8, MVT::v8i16}) in WebAssemblyTargetLowering()
166 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
181 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
191 setOperationAction(ISD::MUL, MVT::v16i8, Expand); in WebAssemblyTargetLowering()
201 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
206 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32}) in WebAssemblyTargetLowering()
1680 bool CanSwizzle = VecT == MVT::v16i8; in LowerBUILD_VECTOR()
1713 if (SwizzleSrc.getValueType() != MVT::v16i8 || in LowerBUILD_VECTOR()
[all …]
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/Support/
H A DMachineValueType.h77 v16i8 = 30, // 16 x i8 enumerator
391 return (SimpleTy == MVT::v128i1 || SimpleTy == MVT::v16i8 || in is128BitVector()
528 case v16i8: in getVectorElementType()
712 case v16i8: in getVectorMinNumElements()
913 case v16i8: in getSizeInBits()
1151 if (NumElements == 16) return MVT::v16i8; in getVectorVT()

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