/netbsd/external/apache2/llvm/dist/llvm/include/llvm/Support/ |
H A D | MachineValueType.h | 83 v1i16 = 35, // 1 x i16 enumerator 368 return (SimpleTy == MVT::v2i8 || SimpleTy == MVT::v1i16 || in is16BitVector() 540 case v1i16: in getVectorElementType() 790 case v1i16: in getVectorMinNumElements() 859 case v1i16: in getSizeInBits() 1158 if (NumElements == 1) return MVT::v1i16; in getVectorVT()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64SchedFalkorDetails.td | 681 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i… 683 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v2… 685 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QSUB(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i… 690 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v… 694 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQABS(v1i8|v1i16|v1i32|v1i64|v2i32|v4i16|v8i8)$"… 695 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQNEG(v1i8|v1i16|v1i32|v1i64)$")>; 703 … (instregex "^SQR?DMULH(v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?$")>; 707 … (instregex "^SQRDML(A|S)H(i16|i32|v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?$")>;
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H A D | AArch64SchedA57.td | 348 // D form - v1i8, v1i16, v1i32, v1i64 380 def : InstRW<[A57Write_5cyc_1W_Mul_Forward], (instregex "^MUL(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i… 382 def : InstRW<[A57Write_5cyc_1W], (instregex "^(PMUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1… 424 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2… 519 // D form - v1i8, v1i16, v1i32, v1i64
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H A D | AArch64SchedTSV110.td | 523 // D form - v1i8, v1i16, v1i32, v1i64 553 …0Wr_4cyc_1FSU1], (instregex "^(MUL|ML[AS]|SQR?D(MULH))(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)")>; 574 def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16…
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H A D | AArch64SchedKryoDetails.td | 213 (instregex "(S|U|SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64)")>; 231 (instregex "(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32)$")>; 261 (instregex "(S|U)QSUB(v8i8|v4i16|v2i32|v1i64|v1i32|v1i16|v1i8)")>; 273 (instregex "(S|U)QXTU?N(v1i8|v1i16|v1i32)")>; 1818 (instregex "SQR?DMULH(v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?")>; 1824 (instregex "SQ(ABS|NEG)(v1i8|v1i16|v1i32|v1i64)")>;
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H A D | AArch64SchedThunderX2T99.td | 1306 "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" # 1335 "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
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H A D | AArch64SchedThunderX3T110.td | 1414 "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" # 1443 "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
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H A D | AArch64InstrFormats.td | 6786 def v1i16 : BaseSIMDThreeScalar<U, 0b011, opc, FPR16, asm, []>; 6799 def v1i16 : BaseSIMDThreeScalar<U, 0b011, opc, FPR16, asm, []>; 6807 def v1i16: BaseSIMDThreeScalarTied<U, 0b01, R, opc, (outs FPR16:$dst), 7027 def v1i16 : BaseSIMDTwoScalar<U, {S,1}, 0b11, opc, FPR16, FPR16, asm, 7039 def v1i16 : BaseSIMDTwoScalar<U, 0b01, 0b00, opc, FPR16, FPR16, asm, []>; 7054 def v1i16 : BaseSIMDTwoScalarTied<U, 0b01, opc, FPR16, FPR16, asm, []>; 7069 def v1i16 : BaseSIMDTwoScalar<U, 0b01, 0b00, opc, FPR16, FPR32, asm, []>;
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H A D | AArch64SchedA64FX.td | 1682 "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" # 1723 "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
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H A D | AArch64ISelLowering.cpp | 16820 if (VT == MVT::v1i8 || VT == MVT::v1i16 || VT == MVT::v1i32 || in getPreferredVectorAction()
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/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | ValueTypes.td | 59 def v1i16 : ValueType<16, 35>; // 1 x i16 vector value
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | ValueTypes.cpp | 242 case MVT::v1i16: in getTypeForEVT()
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/netbsd/external/apache2/llvm/dist/llvm/utils/TableGen/ |
H A D | CodeGenTarget.cpp | 102 case MVT::v1i16: return "MVT::v1i16"; in getEnumName()
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/netbsd/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
H A D | Intrinsics.td | 285 def llvm_v1i16_ty : LLVMType<v1i16>; // 1 x i16
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