Searched refs:v2_1 (Results 1 – 8 of 8) sorted by relevance
182 const struct rlc_firmware_header_v2_1 *v2_1 = in amdgpu_ucode_print_rlc_hdr() local187 le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver)); in amdgpu_ucode_print_rlc_hdr()189 le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver)); in amdgpu_ucode_print_rlc_hdr()191 le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes)); in amdgpu_ucode_print_rlc_hdr()195 le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver)); in amdgpu_ucode_print_rlc_hdr()197 le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver)); in amdgpu_ucode_print_rlc_hdr()199 le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes)); in amdgpu_ucode_print_rlc_hdr()201 le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes)); in amdgpu_ucode_print_rlc_hdr()203 le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver)); in amdgpu_ucode_print_rlc_hdr()205 le32_to_cpu(v2_1->save_restore_list_srm_feature_ver)); in amdgpu_ucode_print_rlc_hdr()[all …]
529 SET_DCE_CLOCK_PS_ALLOCATION_V2_1 v2_1; member551 args.v2_1.asParam.ulDCEClkFreq = cpu_to_le32(freq); /* 10kHz units */ in amdgpu_atombios_crtc_set_dce_clock()552 args.v2_1.asParam.ucDCEClkType = clk_type; in amdgpu_atombios_crtc_set_dce_clock()553 args.v2_1.asParam.ucDCEClkSrc = clk_src; in amdgpu_atombios_crtc_set_dce_clock()555 ret_freq = le32_to_cpu(args.v2_1.asParam.ulDCEClkFreq) * 10; in amdgpu_atombios_crtc_set_dce_clock()
1563 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; member1597 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { in amdgpu_atombios_init_mc_reg_table()1600 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); in amdgpu_atombios_init_mc_reg_table()
6 #define v2_1 crypto_scalarmult_curve25519_sandy2x_v2_1 macro
12 v2_1: .quad 2, 1 label
74 vpmuludq v2_1(%rip),%xmm10,%xmm1079 vpmuludq v2_1(%rip),%xmm10,%xmm1084 vpmuludq v2_1(%rip),%xmm10,%xmm1089 vpmuludq v2_1(%rip),%xmm10,%xmm10
319 const struct smc_firmware_header_v2_1 *v2_1; in smu_v11_0_set_pptable_v2_1() local324 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; in smu_v11_0_set_pptable_v2_1()326 ((const uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); in smu_v11_0_set_pptable_v2_1()327 pptable_count = le32_to_cpu(v2_1->pptable_count); in smu_v11_0_set_pptable_v2_1()330 *table = ((const uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); in smu_v11_0_set_pptable_v2_1()
3815 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; member3878 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { in radeon_atom_get_memory_info()3880 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo; in radeon_atom_get_memory_info()4003 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { in radeon_atom_init_mc_reg_table()4006 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); in radeon_atom_init_mc_reg_table()