| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/Support/ |
| H A D | MachineValueType.h | 151 v32f32 = 94, // 32 x f32 enumerator
421 SimpleTy == MVT::v32f32 || SimpleTy == MVT::v16f64 || in is1024BitVector()
627 case v32f32: in getVectorElementType()
703 case v32f32: in getVectorMinNumElements()
971 case v32f32: in getSizeInBits()
1229 if (NumElements == 32) return MVT::v32f32; in getVectorVT()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstructions.td | 1118 f32, v32f32, Index, !cast<SubRegIndex>(sub#Index)
1122 f32, v32f32, Index, !cast<SubRegIndex>(sub#Index)
1240 def : BitConvert <v32i32, v32f32, VReg_1024>;
1241 def : BitConvert <v32f32, v32i32, VReg_1024>;
1246 def : BitConvert <v16f64, v32f32, VReg_1024>;
1247 def : BitConvert <v32f32, v16f64, VReg_1024>;
1248 def : BitConvert <v16i64, v32f32, VReg_1024>;
1251 def : BitConvert <v32f32, v16i64, VReg_1024>;
1747 defm : SI_INDIRECT_Pattern <v32f32, f32, "V32">;
|
| H A D | SIRegisterInfo.td | 777 def SGPR_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32, v16i64, v16f64], 32,
782 def SReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32, v16i64, v16f64], 32,
818 defm VReg_1024 : VRegClass<32, [v32i32, v32f32, v16i64, v16f64], (add VGPR_1024)>;
838 defm AReg_1024 : ARegClass<32, [v32i32, v32f32, v16i64, v16f64], (add AGPR_1024)>;
|
| H A D | SIInstrInfo.td | 2294 def VOP_V32F32_F32_F32_V32F32 : VOPProfile <[v32f32, f32, f32, v32f32]>;
2297 def VOP_V32F32_V4F16_V4F16_V32F32 : VOPProfile <[v32f32, v4f16, v4f16, v32f32]>;
2300 def VOP_V32F32_V2I16_V2I16_V32F32 : VOPProfile <[v32f32, v2i16, v2i16, v32f32]>;
2313 def VOP_V32F32_V4I16_V4I16_V32F32 : VOPProfile <[v32f32, v4i16, v4i16, v32f32]>;
|
| H A D | AMDGPUISelLowering.cpp | 87 setOperationAction(ISD::LOAD, MVT::v32f32, Promote); in AMDGPUTargetLowering()
88 AddPromotedToType(ISD::LOAD, MVT::v32f32, MVT::v32i32); in AMDGPUTargetLowering()
172 setLoadExtAction(ISD::EXTLOAD, MVT::v32f32, MVT::v32f16, Expand); in AMDGPUTargetLowering()
207 setOperationAction(ISD::STORE, MVT::v32f32, Promote); in AMDGPUTargetLowering()
208 AddPromotedToType(ISD::STORE, MVT::v32f32, MVT::v32i32); in AMDGPUTargetLowering()
256 setTruncStoreAction(MVT::v32f32, MVT::v32f16, Expand); in AMDGPUTargetLowering()
342 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32f32, Custom); in AMDGPUTargetLowering()
|
| H A D | SIISelLowering.cpp | 131 addRegisterClass(MVT::v32f32, TRI->getVGPRClassForBitWidth(1024)); in SITargetLowering()
248 MVT::v16i64, MVT::v16f64, MVT::v32i32, MVT::v32f32 }) { in SITargetLowering()
734 for (MVT VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32, MVT::v32f32 }) { in SITargetLowering()
4433 VT == MVT::v8f32 || VT == MVT::v16f32 || VT == MVT::v32f32); in splitBinaryVectorOp()
4455 VT == MVT::v8f32 || VT == MVT::v16f32 || VT == MVT::v32f32); in splitTernaryVectorOp()
|
| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ValueTypes.td | 124 def v32f32 : ValueType<1024, 94>; // 32 x f32 vector value
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | ValueTypes.cpp | 360 case MVT::v32f32: in getTypeForEVT()
|
| /netbsd/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | CodeGenTarget.cpp | 158 case MVT::v32f32: return "MVT::v32f32"; in getEnumName()
|
| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| H A D | Intrinsics.td | 323 def llvm_v32f32_ty : LLVMType<v32f32>; // 32 x float
|