| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/Support/ |
| H A D | MachineValueType.h | 96 v3i32 = 47, // 3 x i32 enumerator
558 case v3i32: in getVectorElementType()
766 case v3i32: in getVectorMinNumElements()
907 case v3i32: in getSizeInBits()
1172 if (NumElements == 3) return MVT::v3i32; in getVectorVT()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | BUFInstructions.td | 827 "buffer_load_format_d16_xyz", v3i32
839 "buffer_store_format_d16_xyz", v3i32
892 "buffer_load_dwordx3", v3i32
906 defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_DWORDX3", v3i32, load_global>;
917 "buffer_load_dwordx3", v3i32, null_frag, 0, 1
937 "buffer_store_dwordx3", v3i32, store_global
1237 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v3i32, "BUFFER_LOAD_FORMAT_XYZ">;
1271 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v3i32, "BUFFER_LOAD_DWORDX3">;
1354 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store, v3i32, "BUFFER_STORE_DWORDX3">;
1783 defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v3i32, "TBUFFER_LOAD_FORMAT_XYZ">;
[all …]
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| H A D | SIRegisterInfo.td | 690 def SGPR_96 : RegisterClass<"AMDGPU", [v3i32, v3f32], 32,
695 def SReg_96 : RegisterClass<"AMDGPU", [v3i32, v3f32], 32,
811 defm VReg_96 : VRegClass<3, [v3i32, v3f32], (add VGPR_96)>;
832 defm AReg_96 : ARegClass<3, [v3i32, v3f32], (add AGPR_96)>;
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| H A D | FLATInstructions.td | 963 def : FlatLoadPat <FLAT_LOAD_DWORDX3, load_flat, v3i32>;
981 def : FlatStorePat <FLAT_STORE_DWORDX3, store_flat, v3i32>;
1162 defm : GlobalFLATLoadPats <GLOBAL_LOAD_DWORDX3, load_global, v3i32>;
1179 defm : GlobalFLATStorePats <GLOBAL_STORE_DWORDX3, store_global, v3i32>;
1273 defm : ScratchFLATLoadPats <SCRATCH_LOAD_DWORDX3, load_private, v3i32>;
1284 defm : ScratchFLATStorePats <SCRATCH_STORE_DWORDX3, store_private, v3i32>;
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| H A D | SIInstructions.td | 1009 i32, v3i32, Index, !cast<SubRegIndex>(sub#Index)
1012 i32, v3i32, Index, !cast<SubRegIndex>(sub#Index)
1189 def : BitConvert <v3i32, v3f32, SGPR_96>;
1190 def : BitConvert <v3f32, v3i32, SGPR_96>;
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| H A D | AMDGPUISelLowering.cpp | 73 AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32); in AMDGPUTargetLowering()
193 AddPromotedToType(ISD::STORE, MVT::v3f32, MVT::v3i32); in AMDGPUTargetLowering()
322 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3i32, Custom); in AMDGPUTargetLowering()
333 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3i32, Custom); in AMDGPUTargetLowering()
415 MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32 in AMDGPUTargetLowering()
500 AddPromotedToType(ISD::SELECT, MVT::v3f32, MVT::v3i32); in AMDGPUTargetLowering()
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| H A D | SIISelLowering.cpp | 92 addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass); in SITargetLowering()
144 setOperationAction(ISD::LOAD, MVT::v3i32, Custom); in SITargetLowering()
153 setOperationAction(ISD::STORE, MVT::v3i32, Custom); in SITargetLowering()
162 setTruncStoreAction(MVT::v3i32, MVT::v3i16, Expand); in SITargetLowering()
365 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3i32, Custom); in SITargetLowering()
7436 (WidenedVT == MVT::v3i32 || WidenedVT == MVT::v3f32)) { in getMemIntrinsicNode()
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| /netbsd/external/apache2/llvm/dist/llvm/docs/GlobalISel/ |
| H A D | GMIR.rst | 186 ``<3 x s32>`` ``v3i32`` ``<3 x i32>``
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ValueTypes.td | 72 def v3i32 : ValueType<96, 47>; // 3 x i32 vector value
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | ValueTypes.cpp | 266 case MVT::v3i32: in getTypeForEVT()
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| /netbsd/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | CodeGenTarget.cpp | 113 case MVT::v3i32: return "MVT::v3i32"; in getEnumName()
|