/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 1490 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, in getCastInstrCost() 1491 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, in getCastInstrCost() 1503 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, in getCastInstrCost() 1504 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, in getCastInstrCost() 1665 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, in getCastInstrCost() 1870 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost() 1871 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, in getCastInstrCost() 1883 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, in getCastInstrCost() 1884 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, in getCastInstrCost() 3629 { ISD::AND, MVT::v4i1, 5 }, in getArithmeticReductionCost() [all …]
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H A D | X86InstrVecCompiler.td | 169 def maskzeroupperv4i1 : maskzeroupper<v4i1, VK4>; 264 (v4i1 VK4:$mask), (iPTR 0))), 290 (v4i1 VK4:$mask), (iPTR 0))), 340 (v4i1 VK4:$mask), (iPTR 0))), 353 (v4i1 VK4:$mask), (iPTR 0))),
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H A D | X86RegisterInfo.td | 611 def VK4 : RegisterClass<"X86", [v4i1], 16, (add VK2)> {let Size = 16;} 629 def VK4WM : RegisterClass<"X86", [v4i1], 16, (sub VK4, K0)> {let Size = 16;}
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H A D | X86CallingConv.td | 227 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 548 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 837 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
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H A D | X86InstrAVX512.td | 166 def v4i1_info : X86KVectorVTInfo<VK4, VK4WM, v4i1>; 2861 def : Pat<(v4i1 (load addr:$src)), 2894 defm : operation_gpr_mask_copy_lowering<VK4, v4i1>; 3281 def : Pat<(v4i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK4)>; 3300 defm : operation_subvector_mask_lowering<VK1, v1i1, VK4, v4i1>; 3306 defm : operation_subvector_mask_lowering<VK2, v2i1, VK4, v4i1>; 3312 defm : operation_subvector_mask_lowering<VK4, v4i1, VK8, v8i1>; 4160 (v4i1 (extract_subvector 4164 (v4i1 (extract_subvector 4192 (v4i1 (extract_subvector [all …]
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H A D | X86ISelLowering.cpp | 1446 addRegisterClass(MVT::v4i1, &X86::VK4RegClass); in X86TargetLowering() 1471 setOperationAction(ISD::LOAD, MVT::v4i1, Custom); in X86TargetLowering() 1476 setOperationAction(ISD::STORE, MVT::v4i1, Custom); in X86TargetLowering() 1490 for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) { in X86TargetLowering() 1505 for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1 }) in X86TargetLowering() 18272 case MVT::v4i1: in lower1BitShuffle() 21235 MVT TruncVT = MVT::v4i1; in LowerFP_TO_INT() 31225 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i1, Mask, in ReplaceNodeResults() 39509 if (SrcVT != MVT::v4i1) in adjustBitcastSrcVectorSSE1() 39624 case MVT::v4i1: in combineBitcastvxi1() [all …]
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H A D | X86InstrCompiler.td | 577 defm _VK4 : CMOVrr_PSEUDO<VK4, v4i1>;
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMInstrMVE.td | 297 def MVE_v4i32 : MVEVectorVTInfo<v4i32, v2i64, v4i1, v4i1, 0b10, "i", ?>; 314 def MVE_v4f32 : MVEVectorVTInfo<v4f32, v2f64, v4i1, v4i1, 0b10, "f", ?>; 4308 def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmpz (v4i32 MQPR:$v1), fc)))), 4331 def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmp (v4i32 MQPR:$v1), (v4i32 MQPR:$v2), fc)))), 4338 …def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmp (v4i32 MQPR:$v1), (v4i32 (ARMvdup rGPR:$v2)),… 4350 def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmpz (v4f32 MQPR:$v1), fc)))), 4367 def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmp (v4f32 MQPR:$v1), (v4f32 MQPR:$v2), fc)))), 4372 …def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmp (v4f32 MQPR:$v1), (v4f32 (ARMvdup rGPR:$v2)),… 4425 def v4i1 : Pat<(v4i1 (opnode (v4i1 VCCR:$p1), (v4i1 VCCR:$p2))), 6831 def : Pat<(v4i1 (xor (v4i1 VCCR:$pred), (v4i1 (predicate_cast (i32 65535))))), [all …]
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H A D | ARMTargetTransformInfo.cpp | 612 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost() 613 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost() 917 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 }, in getCmpSelInstrCost()
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H A D | ARMRegisterInfo.td | 386 def VCCR : RegisterClass<"ARM", [i32, v16i1, v8i1, v4i1], 32, (add VPR)> {
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H A D | ARMISelLowering.cpp | 436 const MVT pTypes[] = {MVT::v16i1, MVT::v8i1, MVT::v4i1}; in addMVEVectorTypes() 8106 case MVT::v4i1: in getVectorTyFromPredicateVector() 8758 assert((VT == MVT::v16i1 || VT == MVT::v8i1 || VT == MVT::v4i1) && in LowerTruncatei1() 9491 assert((MemVT == MVT::v4i1 || MemVT == MVT::v8i1 || MemVT == MVT::v16i1) && in LowerPredicateLoad() 9547 assert((MemVT == MVT::v4i1 || MemVT == MVT::v8i1 || MemVT == MVT::v16i1) && in LowerPredicateStore() 9605 ((MemVT == MVT::v4i1 || MemVT == MVT::v8i1 || in LowerSTORE() 13373 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT) || VT == MVT::v4i1 || in PerformANDCombine() 13671 (VT == MVT::v4i1 || VT == MVT::v8i1 || VT == MVT::v16i1)) in PerformORCombine() 17174 if ((Ty == MVT::v16i1 || Ty == MVT::v8i1 || Ty == MVT::v4i1)) { in allowsMisalignedMemoryAccesses()
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/netbsd/external/apache2/llvm/dist/llvm/include/llvm/Support/ |
H A D | MachineValueType.h | 63 v4i1 = 17, // 4 x i1 enumerator 508 case v4i1: in getVectorElementType() 747 case v4i1: in getVectorMinNumElements() 847 case v4i1: return TypeSize::Fixed(4); in getSizeInBits() 1136 if (NumElements == 4) return MVT::v4i1; in getVectorVT()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonPatterns.td | 81 def V4I1: PatLeaf<(v4i1 PredRegs:$R)>; 586 def: OpR_RR_pat<MI, VOp, v4i1, V4I1>; 662 def: OpR_RR_pat<A2_vcmpheq, seteq, v4i1, V4I16>; 664 def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, v4i1, V4I16>; 666 def: OpR_RR_pat<A2_vcmphgt, setgt, v4i1, V4I16>; 668 def: OpR_RR_pat<A2_vcmphgtu, RevCmp<setult>, v4i1, V4I16>; 670 def: OpR_RR_pat<A2_vcmphgtu, setugt, v4i1, V4I16>; 739 def: OpmR_RR_pat<Outn<A2_vcmpheq>, setne, v4i1, V4I16>; 1437 def: OpR_RR_pat<C2_xor, Add, v4i1, V4I1>; 1441 def: OpR_RR_pat<C2_xor, Sub, v4i1, V4I1>; [all …]
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H A D | HexagonISelLowering.cpp | 1471 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa in HexagonTargetLowering() 1692 for (MVT NativeVT : {MVT::v8i1, MVT::v4i1, MVT::v2i1, MVT::v4i8, in HexagonTargetLowering() 1730 for (MVT VT : {MVT::v2i1, MVT::v4i1, MVT::v8i1}) { in HexagonTargetLowering() 2737 if (VecTy == MVT::v8i1 || VecTy == MVT::v4i1 || VecTy == MVT::v2i1) { in LowerBUILD_VECTOR() 2790 assert(VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1); in LowerCONCAT_VECTORS() 2892 bool DoCast = (Ty == MVT::v2i1 || Ty == MVT::v4i1 || Ty == MVT::v8i1); in LowerLoad() 2922 bool DoCast = (Ty == MVT::v2i1 || Ty == MVT::v4i1 || Ty == MVT::v8i1); in LowerStore()
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H A D | HexagonRegisterInfo.td | 392 [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32, (add P0, P1, P2, P3)>;
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H A D | HexagonISelLoweringHVX.cpp | 682 assert(PredTy == MVT::v2i1 || PredTy == MVT::v4i1 || PredTy == MVT::v8i1); in createHvxPrefixPred()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.cpp | 69 setLoadExtAction(ISD::EXTLOAD, MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering() 70 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering() 71 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering() 95 setTruncStoreAction(MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering() 161 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand); in R600TargetLowering()
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H A D | SIISelLowering.cpp | 200 setOperationAction(ISD::SETCC, MVT::v4i1, Expand); in SITargetLowering() 213 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom); in SITargetLowering()
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/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | ValueTypes.td | 39 def v4i1 : ValueType<4, 17>; // 4 x i1 vector value
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | ValueTypes.cpp | 206 case MVT::v4i1: in getTypeForEVT()
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/netbsd/external/apache2/llvm/dist/llvm/utils/TableGen/ |
H A D | CodeGenTarget.cpp | 84 case MVT::v4i1: return "MVT::v4i1"; in getEnumName()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64TargetTransformInfo.cpp | 1138 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4 * AmortizationCost }, in getCmpSelInstrCost()
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/netbsd/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
H A D | IntrinsicsARM.td | 812 // vctp64 takes v4i1, to work around v2i1 not being a legal MVE type
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H A D | Intrinsics.td | 265 def llvm_v4i1_ty : LLVMType<v4i1>; // 4 x i1
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 124 case MVT::v4i1: in IsPTXVectorType()
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