/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
H A D | amdgpu_smu8_hwmgr.c | 111 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_sclk_level() 267 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_construct_max_power_limits_table() 449 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_upload_pptable_to_smu() 563 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_init_sclk_limit() 692 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_update_sclk_limit() 1152 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_phm_unforce_dpm_levels() 1351 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_dpm_get_pp_table_entry_callback() 1524 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_print_clock_levels() 1622 table = hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_clock_by_type() 1641 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_max_high_clocks() [all …]
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H A D | amdgpu_processpptables.c | 1218 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; in init_clock_voltage_dependency() 1314 &hwmgr->dyn_state.vddc_dependency_on_sclk, table); in init_clock_voltage_dependency() 1346 if(result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) && in init_clock_voltage_dependency() 1347 (0 != hwmgr->dyn_state.vddc_dependency_on_sclk->count)) in init_clock_voltage_dependency() 1350 hwmgr->dyn_state.vddc_dependency_on_sclk); in init_clock_voltage_dependency() 1655 kfree(hwmgr->dyn_state.vddc_dependency_on_sclk); in pp_tables_uninitialize() 1656 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; in pp_tables_uninitialize()
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H A D | amdgpu_ppatomctrl.c | 1135 for (entry_id = 0; entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count; entry_id++) { in atomctrl_get_voltage_evv() 1136 if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].v == virtual_voltage_id) { in atomctrl_get_voltage_evv() 1142 if (entry_id >= hwmgr->dyn_state.vddc_dependency_on_sclk->count) { in atomctrl_get_voltage_evv() 1151 cpu_to_le32(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].clk); in atomctrl_get_voltage_evv()
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H A D | amdgpu_smu7_hwmgr.c | 680 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu7_setup_dpm_tables_v0() 2408 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk); in smu7_patch_dependency_tables_with_leakage() 2464 …clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk; in smu7_set_private_data_based_on_pptable_v0() 2761 for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; in smu7_get_profiling_clk() 2763 if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) { in smu7_get_profiling_clk() 2764 tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk; in smu7_get_profiling_clk() 2771 tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk; in smu7_get_profiling_clk() 2775 *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; in smu7_get_profiling_clk() 4675 sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk; in smu7_get_sclks()
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
H A D | amdgpu_iceland_smumgr.c | 545 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk, in iceland_get_std_voltage_value_sidd() 559 for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in iceland_get_std_voltage_value_sidd() 560 if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { in iceland_get_std_voltage_value_sidd() 579 …for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in iceland_get_std_voltage_value_sidd() 580 if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { in iceland_get_std_voltage_value_sidd() 739 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in iceland_populate_ulv_level() 746 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in iceland_populate_ulv_level() 750 (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage) in iceland_populate_ulv_level() 907 hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock, in iceland_populate_single_graphic_level() 1831 count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count); in iceland_populate_smc_initial_state() [all …]
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H A D | amdgpu_ci_smumgr.c | 422 hwmgr->dyn_state.vddc_dependency_on_sclk, clock, in ci_populate_single_graphic_level() 776 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk, in ci_get_std_voltage_value_sidd() 785 for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in ci_get_std_voltage_value_sidd() 786 if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { in ci_get_std_voltage_value_sidd() 801 …for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in ci_get_std_voltage_value_sidd() 802 if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { in ci_get_std_voltage_value_sidd() 970 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in ci_populate_ulv_level() 977 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in ci_populate_ulv_level() 981 (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage) in ci_populate_ulv_level() 1863 count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count); in ci_populate_smc_initial_state() [all …]
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/netbsd/sys/external/bsd/drm2/dist/drm/radeon/ |
H A D | radeon_r600_dpm.c | 931 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in r600_parse_extended_power_table() 943 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table() 954 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table() 966 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table() 1307 kfree(dyn_state->vddc_dependency_on_sclk.entries); in r600_free_extended_power_table()
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H A D | radeon_kv_dpm.c | 562 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7() 584 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2() 725 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state() 1086 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings() 1720 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_set_valid_clock_range() 2115 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_get_high_voltage_limit() 2156 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_apply_state_adjust_rules() 2360 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_init_graphics_levels()
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H A D | radeon_ci_dpm.c | 292 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) in ci_populate_bapm_vddc_vid_sidd() 2343 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in ci_get_std_voltage_value_sidd() 2349 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd() 2366 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd() 2600 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >= in ci_populate_smc_initial_state() 3147 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; in ci_populate_ulv_level() 3234 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in ci_populate_single_graphic_level() 3451 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_setup_default_dpm_tables() 3794 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_apply_disp_minimum_voltage_request() 4927 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_set_private_data_variables_based_on_pptable() [all …]
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H A D | radeon_btc_dpm.c | 2214 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in btc_apply_state_adjust_rules() 2223 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in btc_apply_state_adjust_rules() 2232 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in btc_apply_state_adjust_rules()
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H A D | radeon_si_dpm.c | 3053 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules() 3159 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules() 4161 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in si_get_std_voltage_value() 4164 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value() 4166 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value() 4179 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value() 4181 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value() 5909 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in si_patch_dependency_tables_based_on_leakage()
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H A D | radeon_atombios.c | 3311 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; in radeon_atom_get_voltage_evv() 3315 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == in radeon_atom_get_voltage_evv() 3327 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); in radeon_atom_get_voltage_evv()
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H A D | radeon_ni_dpm.c | 879 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in ni_apply_state_adjust_rules() 1018 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in ni_patch_dependency_tables_based_on_leakage()
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H A D | radeon.h | 1516 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; member
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
H A D | amdgpu_kv_dpm.c | 81 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7() 103 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2() 808 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state() 1169 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings() 1784 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_set_valid_clock_range() 2180 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_get_high_voltage_limit() 2221 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_apply_state_adjust_rules() 2425 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_init_graphics_levels()
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H A D | amdgpu_dpm.h | 210 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; member
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H A D | amdgpu_atombios.c | 1368 u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; in amdgpu_atombios_get_voltage_evv() 1372 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == in amdgpu_atombios_get_voltage_evv() 1384 cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); in amdgpu_atombios_get_voltage_evv()
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H A D | amdgpu_dpm.c | 339 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in amdgpu_parse_extended_power_table() 728 kfree(dyn_state->vddc_dependency_on_sclk.entries); in amdgpu_free_extended_power_table()
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H A D | amdgpu_si_dpm.c | 3513 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules() 3619 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules() 4625 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in si_get_std_voltage_value() 4628 …for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value() 4630 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value() 4643 …for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value() 4645 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value() 6363 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in si_patch_dependency_tables_based_on_leakage()
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
H A D | hwmgr.h | 627 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk; member
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