Searched refs:vdsc_cfg (Results 1 – 6 of 6) sorted by relevance
272 if (vdsc_cfg->native_420 || vdsc_cfg->native_422) { in drm_dsc_compute_rc_parameters()278 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 * in drm_dsc_compute_rc_parameters()287 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * in drm_dsc_compute_rc_parameters()305 slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; in drm_dsc_compute_rc_parameters()321 vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - in drm_dsc_compute_rc_parameters()325 if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { in drm_dsc_compute_rc_parameters()331 (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); in drm_dsc_compute_rc_parameters()347 vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - in drm_dsc_compute_rc_parameters()377 rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + in drm_dsc_compute_rc_parameters()383 vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; in drm_dsc_compute_rc_parameters()[all …]
397 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, in intel_dsc_compute_params()401 vdsc_cfg->simple_422 = false; in intel_dsc_compute_params()403 vdsc_cfg->vbr_enable = false; in intel_dsc_compute_params()468 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / in intel_dsc_compute_params()469 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); in intel_dsc_compute_params()520 if (vdsc_cfg->convert_rgb) in intel_dsc_pps_configure()522 if (vdsc_cfg->simple_422) in intel_dsc_pps_configure()524 if (vdsc_cfg->vbr_enable) in intel_dsc_pps_configure()749 vdsc_cfg->slice_width) | in intel_dsc_pps_configure()751 vdsc_cfg->slice_height); in intel_dsc_pps_configure()[all …]
1342 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in gen11_dsi_dsc_compute_config() local1358 vdsc_cfg->convert_rgb = true; in gen11_dsi_dsc_compute_config()1365 WARN_ON(vdsc_cfg->vbr_enable); in gen11_dsi_dsc_compute_config()1366 WARN_ON(vdsc_cfg->simple_422); in gen11_dsi_dsc_compute_config()1367 WARN_ON(vdsc_cfg->pic_width % vdsc_cfg->slice_width); in gen11_dsi_dsc_compute_config()1368 WARN_ON(vdsc_cfg->slice_height < 8); in gen11_dsi_dsc_compute_config()1369 WARN_ON(vdsc_cfg->pic_height % vdsc_cfg->slice_height); in gen11_dsi_dsc_compute_config()1371 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); in gen11_dsi_dsc_compute_config()
2425 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in fill_dsc() local2428 vdsc_cfg->dsc_version_major = dsc->version_major; in fill_dsc()2429 vdsc_cfg->dsc_version_minor = dsc->version_minor; in fill_dsc()2483 vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth); in fill_dsc()2485 vdsc_cfg->block_pred_enable = dsc->block_prediction_enable; in fill_dsc()2487 vdsc_cfg->slice_height = dsc->slice_height; in fill_dsc()
2065 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dp_dsc_compute_params() local2078 if (vdsc_cfg->pic_height % 8 == 0) in intel_dp_dsc_compute_params()2079 vdsc_cfg->slice_height = 8; in intel_dp_dsc_compute_params()2080 else if (vdsc_cfg->pic_height % 4 == 0) in intel_dp_dsc_compute_params()2081 vdsc_cfg->slice_height = 4; in intel_dp_dsc_compute_params()2083 vdsc_cfg->slice_height = 2; in intel_dp_dsc_compute_params()2085 vdsc_cfg->dsc_version_major = in intel_dp_dsc_compute_params()2088 vdsc_cfg->dsc_version_minor = in intel_dp_dsc_compute_params()2102 if (vdsc_cfg->dsc_version_minor == 2) in intel_dp_dsc_compute_params()2109 vdsc_cfg->block_pred_enable = in intel_dp_dsc_compute_params()[all …]
609 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);