1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the Software), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef _LS10_H_ 25 #define _LS10_H_ 26 27 28 29 #include "export_nvswitch.h" 30 #include "common_nvswitch.h" 31 32 #include "ctrl_dev_nvswitch.h" 33 34 #include "nvswitch/ls10/dev_master.h" 35 36 #define NVSWITCH_NUM_LINKS_LS10 64 37 #define NVSWITCH_NUM_LANES_LS10 2 38 39 #define NVSWITCH_LINKS_PER_MINION_LS10 4 40 #define NVSWITCH_LINKS_PER_NVLIPT_LS10 4 41 #define NVSWITCH_LINKS_PER_NVLW_LS10 4 42 #define NVSWITCH_LINKS_PER_NPG_LS10 4 43 44 #define NVSWITCH_NPORT_PER_NPG_LS10 NVSWITCH_LINKS_PER_NPG_LS10 45 46 #define NUM_PTOP_ENGINE_LS10 1 47 #define NUM_FUSE_ENGINE_LS10 1 48 #define NUM_GIN_ENGINE_LS10 1 49 #define NUM_JTAG_ENGINE_LS10 1 50 51 #define NUM_PMGR_ENGINE_LS10 1 52 #define NUM_SAW_ENGINE_LS10 1 53 #define NUM_ROM_ENGINE_LS10 1 54 #define NUM_EXTDEV_ENGINE_LS10 1 55 #define NUM_PTIMER_ENGINE_LS10 1 56 #define NUM_SOE_ENGINE_LS10 1 57 #define NUM_SMR_ENGINE_LS10 2 58 #define NUM_SE_ENGINE_LS10 1 59 #define NUM_THERM_ENGINE_LS10 1 60 #define NUM_XAL_ENGINE_LS10 1 61 #define NUM_XAL_FUNC_ENGINE_LS10 1 62 #define NUM_XTL_CONFIG_ENGINE_LS10 1 63 #define NUM_XPL_ENGINE_LS10 1 64 #define NUM_XTL_ENGINE_LS10 1 65 #define NUM_SYSCTRL_ENGINE_LS10 1 66 #define NUM_UXL_ENGINE_LS10 1 67 #define NUM_GPU_PTOP_ENGINE_LS10 1 68 #define NUM_PMC_ENGINE_LS10 1 69 #define NUM_PBUS_ENGINE_LS10 1 70 #define NUM_ROM2_ENGINE_LS10 1 71 #define NUM_GPIO_ENGINE_LS10 1 72 #define NUM_FSP_ENGINE_LS10 1 73 74 #define NUM_CLKS_SYS_ENGINE_LS10 1 75 #define NUM_CLKS_SYSB_ENGINE_LS10 1 76 #define NUM_CLKS_P0_ENGINE_LS10 4 77 #define NUM_CLKS_P0_BCAST_ENGINE_LS10 1 78 #define NUM_SAW_PM_ENGINE_LS10 1 79 #define NUM_PCIE_PM_ENGINE_LS10 1 80 #define NUM_PRT_PRI_HUB_ENGINE_LS10 16 81 #define NUM_PRT_PRI_RS_CTRL_ENGINE_LS10 16 82 #define NUM_PRT_PRI_HUB_BCAST_ENGINE_LS10 1 83 #define NUM_PRT_PRI_RS_CTRL_BCAST_ENGINE_LS10 1 84 #define NUM_SYS_PRI_HUB_ENGINE_LS10 1 85 #define NUM_SYS_PRI_RS_CTRL_ENGINE_LS10 1 86 #define NUM_SYSB_PRI_HUB_ENGINE_LS10 1 87 #define NUM_SYSB_PRI_RS_CTRL_ENGINE_LS10 1 88 #define NUM_PRI_MASTER_RS_ENGINE_LS10 1 89 90 #define NUM_NPG_ENGINE_LS10 16 91 #define NUM_NPG_PERFMON_ENGINE_LS10 NUM_NPG_ENGINE_LS10 92 #define NUM_NPORT_ENGINE_LS10 (NUM_NPG_ENGINE_LS10 * NVSWITCH_NPORT_PER_NPG_LS10) 93 #define NUM_NPORT_MULTICAST_ENGINE_LS10 NUM_NPG_ENGINE_LS10 94 #define NUM_NPORT_PERFMON_ENGINE_LS10 NUM_NPORT_ENGINE_LS10 95 #define NUM_NPORT_PERFMON_MULTICAST_ENGINE_LS10 NUM_NPG_ENGINE_LS10 96 97 #define NUM_NPG_BCAST_ENGINE_LS10 1 98 #define NUM_NPG_PERFMON_BCAST_ENGINE_LS10 NUM_NPG_BCAST_ENGINE_LS10 99 #define NUM_NPORT_BCAST_ENGINE_LS10 NVSWITCH_NPORT_PER_NPG_LS10 100 #define NUM_NPORT_MULTICAST_BCAST_ENGINE_LS10 NUM_NPG_BCAST_ENGINE_LS10 101 #define NUM_NPORT_PERFMON_BCAST_ENGINE_LS10 NUM_NPORT_BCAST_ENGINE_LS10 102 #define NUM_NPORT_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NPG_BCAST_ENGINE_LS10 103 104 #define NUM_NVLW_ENGINE_LS10 16 105 #define NUM_NVLIPT_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 106 #define NUM_MINION_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 107 #define NUM_PLL_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 108 #define NUM_CPR_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 109 #define NUM_NVLW_PERFMON_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 110 #define NUM_NVLIPT_SYS_PERFMON_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 111 #define NUM_NVLDL_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 112 #define NUM_NVLTLC_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 113 #define NUM_NVLIPT_LNK_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 114 #define NUM_SYS_PERFMON_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 115 #define NUM_TX_PERFMON_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 116 #define NUM_RX_PERFMON_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 117 #define NUM_NVLDL_ENGINE_LS10 (NUM_NVLW_ENGINE_LS10 * NVSWITCH_LINKS_PER_NVLIPT_LS10) 118 #define NUM_NVLTLC_ENGINE_LS10 NUM_NVLDL_ENGINE_LS10 119 #define NUM_NVLIPT_LNK_ENGINE_LS10 NUM_NVLDL_ENGINE_LS10 120 #define NUM_SYS_PERFMON_ENGINE_LS10 NUM_NVLDL_ENGINE_LS10 121 #define NUM_TX_PERFMON_ENGINE_LS10 NUM_NVLDL_ENGINE_LS10 122 #define NUM_RX_PERFMON_ENGINE_LS10 NUM_NVLDL_ENGINE_LS10 123 124 #define NUM_NVLW_BCAST_ENGINE_LS10 1 125 #define NUM_NVLIPT_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 126 #define NUM_MINION_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 127 #define NUM_PLL_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 128 #define NUM_CPR_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 129 #define NUM_NVLW_PERFMON_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 130 #define NUM_NVLIPT_SYS_PERFMON_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 131 #define NUM_NVLDL_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 132 #define NUM_NVLTLC_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 133 #define NUM_NVLIPT_LNK_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 134 #define NUM_SYS_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 135 #define NUM_TX_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 136 #define NUM_RX_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 137 #define NUM_NVLDL_BCAST_ENGINE_LS10 NVSWITCH_LINKS_PER_NVLIPT_LS10 138 #define NUM_NVLTLC_BCAST_ENGINE_LS10 NUM_NVLDL_BCAST_ENGINE_LS10 139 #define NUM_NVLIPT_LNK_BCAST_ENGINE_LS10 NUM_NVLDL_BCAST_ENGINE_LS10 140 #define NUM_SYS_PERFMON_BCAST_ENGINE_LS10 NUM_NVLDL_BCAST_ENGINE_LS10 141 #define NUM_TX_PERFMON_BCAST_ENGINE_LS10 NUM_NVLDL_BCAST_ENGINE_LS10 142 #define NUM_RX_PERFMON_BCAST_ENGINE_LS10 NUM_NVLDL_BCAST_ENGINE_LS10 143 144 #define NUM_NXBAR_ENGINE_LS10 3 145 #define NUM_NXBAR_PERFMON_ENGINE_LS10 NUM_NXBAR_ENGINE_LS10 146 #define NUM_TILE_MULTICAST_ENGINE_LS10 NUM_NXBAR_ENGINE_LS10 147 #define NUM_TILE_PERFMON_MULTICAST_ENGINE_LS10 NUM_NXBAR_ENGINE_LS10 148 #define NUM_TILE_ENGINE_LS10 (12 * NUM_NXBAR_ENGINE_LS10) 149 #define NUM_TILE_PERFMON_ENGINE_LS10 NUM_TILE_ENGINE_LS10 150 #define NUM_TILEOUT_MULTICAST_ENGINE_LS10 NUM_NXBAR_ENGINE_LS10 151 #define NUM_TILEOUT_PERFMON_MULTICAST_ENGINE_LS10 NUM_NXBAR_ENGINE_LS10 152 #define NUM_TILEOUT_ENGINE_LS10 NUM_TILE_ENGINE_LS10 153 #define NUM_TILEOUT_PERFMON_ENGINE_LS10 NUM_TILE_ENGINE_LS10 154 155 #define NUM_NXBAR_BCAST_ENGINE_LS10 1 156 #define NUM_NXBAR_PERFMON_BCAST_ENGINE_LS10 NUM_NXBAR_BCAST_ENGINE_LS10 157 #define NUM_TILE_MULTICAST_BCAST_ENGINE_LS10 NUM_NXBAR_BCAST_ENGINE_LS10 158 #define NUM_TILE_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NXBAR_BCAST_ENGINE_LS10 159 #define NUM_TILE_BCAST_ENGINE_LS10 12 160 #define NUM_TILE_PERFMON_BCAST_ENGINE_LS10 NUM_TILE_BCAST_ENGINE_LS10 161 #define NUM_TILEOUT_MULTICAST_BCAST_ENGINE_LS10 NUM_NXBAR_BCAST_ENGINE_LS10 162 #define NUM_TILEOUT_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NXBAR_BCAST_ENGINE_LS10 163 #define NUM_TILEOUT_BCAST_ENGINE_LS10 NUM_TILE_BCAST_ENGINE_LS10 164 #define NUM_TILEOUT_PERFMON_BCAST_ENGINE_LS10 NUM_TILE_BCAST_ENGINE_LS10 165 #define NUM_MAX_MCFLA_SLOTS_LS10 128 166 167 #define NPORT_TO_LINK_LS10(_device, _npg, _nport) \ 168 ( \ 169 NVSWITCH_ASSERT((_npg < NUM_NPG_ENGINE_LS10)) \ 170 , \ 171 NVSWITCH_ASSERT((_nport < NVSWITCH_NPORT_PER_NPG_LS10)) \ 172 , \ 173 ((_npg) * NVSWITCH_NPORT_PER_NPG_LS10 + (_nport)) \ 174 ) 175 176 #define NVSWITCH_NUM_LINKS_PER_NVLIPT_LS10 (NVSWITCH_NUM_LINKS_LS10/NUM_NVLIPT_ENGINE_LS10) 177 178 #define NVSWITCH_NVLIPT_GET_PUBLIC_ID_LS10(_physlinknum) \ 179 ((_physlinknum)/NVSWITCH_LINKS_PER_NVLIPT_LS10) 180 181 #define NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(_physlinknum) \ 182 ((_physlinknum)%NVSWITCH_NUM_LINKS_PER_NVLIPT_LS10) 183 184 #define NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64_LS10(_nvlipt_idx) \ 185 (NVBIT64(NVSWITCH_LINKS_PER_NVLIPT_LS10) - 1) << (_nvlipt_idx * NVSWITCH_LINKS_PER_NVLIPT_LS10); 186 187 #define DMA_ADDR_WIDTH_LS10 64 188 189 #define SOE_VBIOS_VERSION_MASK 0xFF0000 190 #define SOE_VBIOS_REVLOCK_DISABLE_NPORT_FATAL_INTR 0x370000 191 #define SOE_VBIOS_REVLOCK_ISSUE_INGRESS_STOP 0x4C0000 192 193 // LS10 Saved LED state 194 #define ACCESS_LINK_LED_STATE CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED 195 196 // Access link LED states on LS10 Systems 197 #define ACCESS_LINK_LED_STATE_FAULT 0U 198 #define ACCESS_LINK_LED_STATE_OFF 1U 199 #define ACCESS_LINK_LED_STATE_INITIALIZE 2U 200 #define ACCESS_LINK_LED_STATE_UP_WARM 3U 201 #define ACCESS_LINK_LED_STATE_UP_ACTIVE 4U 202 #define ACCESS_LINK_NUM_LED_STATES 5U 203 204 // 205 // Helpful IO wrappers 206 // 207 208 #define NVSWITCH_NPORT_WR32_LS10(_d, _engidx, _dev, _reg, _data) \ 209 NVSWITCH_ENG_WR32(_d, NPORT, , _engidx, _dev, _reg, _data) 210 211 #define NVSWITCH_NPORT_RD32_LS10(_d, _engidx, _dev, _reg) \ 212 NVSWITCH_ENG_RD32(_d, NPORT, , _engidx, _dev, _reg) 213 214 #define NVSWITCH_MINION_WR32_LS10(_d, _engidx, _dev, _reg, _data) \ 215 NVSWITCH_ENG_WR32(_d, MINION, , _engidx, _dev, _reg, _data) 216 217 #define NVSWITCH_MINION_RD32_LS10(_d, _engidx, _dev, _reg) \ 218 NVSWITCH_ENG_RD32(_d, MINION, , _engidx, _dev, _reg) 219 220 #define NVSWITCH_MINION_WR32_BCAST_LS10(_d, _dev, _reg, _data) \ 221 NVSWITCH_ENG_WR32(_d, MINION, _BCAST, 0, _dev, _reg, _data) 222 223 // 224 // Per-chip device information 225 // 226 227 #define DISCOVERY_TYPE_UNDEFINED 0 228 #define DISCOVERY_TYPE_DISCOVERY 1 229 #define DISCOVERY_TYPE_UNICAST 2 230 #define DISCOVERY_TYPE_BROADCAST 3 231 232 typedef struct 233 { 234 NvBool valid; 235 NvU32 initialized; 236 NvU32 version; 237 NvU32 disc_type; 238 union 239 { 240 struct 241 { 242 NvU32 cluster; 243 NvU32 cluster_id; 244 NvU32 discovery; // Used for top level only 245 } top; 246 struct 247 { 248 NvU32 uc_addr; 249 } uc; 250 struct 251 { 252 NvU32 bc_addr; 253 NvU32 mc_addr[3]; 254 } bc; 255 } info; 256 } ENGINE_DISCOVERY_TYPE_LS10; 257 258 #define NVSWITCH_DECLARE_ENGINE_UC_LS10(_engine) \ 259 ENGINE_DISCOVERY_TYPE_LS10 eng##_engine[NUM_##_engine##_ENGINE_LS10]; 260 261 #define NVSWITCH_DECLARE_ENGINE_LS10(_engine) \ 262 ENGINE_DISCOVERY_TYPE_LS10 eng##_engine[NUM_##_engine##_ENGINE_LS10]; \ 263 ENGINE_DISCOVERY_TYPE_LS10 eng##_engine##_BCAST[NUM_##_engine##_BCAST_ENGINE_LS10]; 264 265 #define NVSWITCH_LIST_LS10_ENGINE_UC(_op) \ 266 _op(PTOP) \ 267 _op(FUSE) \ 268 _op(GIN) \ 269 _op(JTAG) \ 270 _op(PMGR) \ 271 _op(SAW) \ 272 _op(ROM) \ 273 _op(EXTDEV) \ 274 _op(PTIMER) \ 275 _op(SOE) \ 276 _op(SMR) \ 277 _op(SE) \ 278 _op(THERM) \ 279 _op(XAL) \ 280 _op(XAL_FUNC) \ 281 _op(XTL_CONFIG) \ 282 _op(XPL) \ 283 _op(XTL) \ 284 _op(UXL) \ 285 _op(GPU_PTOP) \ 286 _op(PMC) \ 287 _op(PBUS) \ 288 _op(ROM2) \ 289 _op(GPIO) \ 290 _op(FSP) \ 291 _op(CLKS_SYS) \ 292 _op(CLKS_SYSB) \ 293 _op(CLKS_P0) \ 294 _op(CLKS_P0_BCAST) \ 295 _op(SAW_PM) \ 296 _op(PCIE_PM) \ 297 _op(SYS_PRI_HUB) \ 298 _op(SYS_PRI_RS_CTRL) \ 299 _op(SYSB_PRI_HUB) \ 300 _op(SYSB_PRI_RS_CTRL) \ 301 _op(PRI_MASTER_RS) \ 302 303 #define NVSWITCH_LIST_PRI_HUB_LS10_ENGINE(_op) \ 304 _op(PRT_PRI_HUB) \ 305 _op(PRT_PRI_RS_CTRL) \ 306 _op(PRT_PRI_HUB_BCAST) \ 307 _op(PRT_PRI_RS_CTRL_BCAST) \ 308 309 #define NVSWITCH_LIST_NPG_LS10_ENGINE(_op) \ 310 _op(NPG) \ 311 _op(NPG_PERFMON) \ 312 _op(NPORT) \ 313 _op(NPORT_MULTICAST) \ 314 _op(NPORT_PERFMON) \ 315 _op(NPORT_PERFMON_MULTICAST) 316 317 #define NVSWITCH_LIST_NVLW_LS10_ENGINE(_op) \ 318 _op(NVLW) \ 319 _op(NVLIPT) \ 320 _op(MINION) \ 321 _op(CPR) \ 322 _op(NVLW_PERFMON) \ 323 _op(NVLIPT_SYS_PERFMON) \ 324 _op(NVLDL_MULTICAST) \ 325 _op(NVLTLC_MULTICAST) \ 326 _op(NVLIPT_LNK_MULTICAST) \ 327 _op(SYS_PERFMON_MULTICAST) \ 328 _op(TX_PERFMON_MULTICAST) \ 329 _op(RX_PERFMON_MULTICAST) \ 330 _op(NVLDL) \ 331 _op(NVLTLC) \ 332 _op(NVLIPT_LNK) \ 333 _op(SYS_PERFMON) \ 334 _op(TX_PERFMON) \ 335 _op(RX_PERFMON) 336 337 #define NVSWITCH_LIST_NXBAR_LS10_ENGINE(_op) \ 338 _op(NXBAR) \ 339 _op(NXBAR_PERFMON) \ 340 _op(TILE_MULTICAST) \ 341 _op(TILE_PERFMON_MULTICAST) \ 342 _op(TILE) \ 343 _op(TILE_PERFMON) \ 344 _op(TILEOUT_MULTICAST) \ 345 _op(TILEOUT_PERFMON_MULTICAST) \ 346 _op(TILEOUT) \ 347 _op(TILEOUT_PERFMON) 348 349 #define NVSWITCH_LIST_LS10_ENGINE(_op) \ 350 NVSWITCH_LIST_NPG_LS10_ENGINE(_op) \ 351 NVSWITCH_LIST_NVLW_LS10_ENGINE(_op) \ 352 NVSWITCH_LIST_NXBAR_LS10_ENGINE(_op) 353 354 // 355 // The chip-specific engine list is used to generate the code to collect 356 // discovered unit information and coalesce it into the data structures used by 357 // the common IO library (see io_nvswitch.h). 358 // 359 // The PTOP discovery table presents the information on wrappers and sub-units 360 // in a hierarchical manner. The top level discovery contains information 361 // about top level UNICAST units and IP wrappers like NPG, NVLW, and NXBAR. 362 // Individual units within an IP wrapper are described in discovery sub-tables. 363 // Each IP wrapper may have MULTICAST descriptors to allow addressing sub-units 364 // within a wrapper and a cluster of IP wrappers will also have a BCAST 365 // discovery tables, which have MULTICAST descriptors within them. 366 // In order to collect all the useful unit information into a single container, 367 // we need to pick where to find each piece within the parsed discovery table. 368 // Top level IP wrappers like NPG have a BCAST range to broadcast reads/writes, 369 // but IP sub-units like NPORT have a MULTICAST range within the BCAST IP 370 // wrapper to broadcast to all the sub-units in all the IP wrappers. 371 // So in the lists below top level IP wrappers (NPG, NVLW, and NXBAR) point 372 // to the _BCAST IP wrapper, but sub-unit point to the _MULTICAST range inside 373 // the BCAST unit (_MULTICAST_BCAST). 374 // 375 // All IP-based (0-based register manuals) engines need to be listed here to 376 // generate chip-specific handlers as well as in the global common list of all 377 // engines that have ever existed on *ANY* architecture(s) in order for them 378 // use common IO wrappers. 379 // 380 381 #define NVSWITCH_LIST_LS10_ENGINES(_op) \ 382 _op(GIN, ) \ 383 _op(XAL, ) \ 384 _op(XPL, ) \ 385 _op(XTL, ) \ 386 _op(XTL_CONFIG, ) \ 387 _op(SAW, ) \ 388 _op(SOE, ) \ 389 _op(SMR, ) \ 390 \ 391 _op(PRT_PRI_HUB, _BCAST) \ 392 _op(PRT_PRI_RS_CTRL, _BCAST) \ 393 _op(SYS_PRI_HUB, ) \ 394 _op(SYS_PRI_RS_CTRL, ) \ 395 _op(SYSB_PRI_HUB, ) \ 396 _op(SYSB_PRI_RS_CTRL, ) \ 397 _op(PRI_MASTER_RS, ) \ 398 _op(PTIMER, ) \ 399 _op(CLKS_SYS, ) \ 400 _op(CLKS_SYSB, ) \ 401 _op(CLKS_P0, _BCAST) \ 402 \ 403 _op(NPG, _BCAST) \ 404 _op(NPORT, _MULTICAST_BCAST) \ 405 \ 406 _op(NVLW, _BCAST) \ 407 _op(MINION, _BCAST) \ 408 _op(NVLIPT, _BCAST) \ 409 _op(CPR, _BCAST) \ 410 _op(NVLIPT_LNK, _MULTICAST_BCAST) \ 411 _op(NVLTLC, _MULTICAST_BCAST) \ 412 _op(NVLDL, _MULTICAST_BCAST) \ 413 \ 414 _op(NXBAR, _BCAST) \ 415 _op(TILE, _MULTICAST_BCAST) \ 416 _op(TILEOUT, _MULTICAST_BCAST) \ 417 \ 418 _op(NPG_PERFMON, _BCAST) \ 419 _op(NPORT_PERFMON, _MULTICAST_BCAST) \ 420 \ 421 _op(NVLW_PERFMON, _BCAST) \ 422 423 // 424 // These field #defines describe which physical fabric address bits are 425 // relevant to the specific remap table address check/remap operation. 426 // 427 428 #define NV_INGRESS_REMAP_ADDR_PHYS_LS10 51:39 /* LR10: 46:36 */ 429 430 #define NV_INGRESS_REMAP_ADR_OFFSET_PHYS_LS10 38:21 /* LR10: 35:20 */ 431 #define NV_INGRESS_REMAP_ADR_BASE_PHYS_LS10 38:21 /* LR10: 35:20 */ 432 #define NV_INGRESS_REMAP_ADR_LIMIT_PHYS_LS10 38:21 /* LR10: 35:20 */ 433 434 // 435 // Multicast REMAP table is not indexed through the same _RAM_SEL mechanism as 436 // other REMAP tables, but we want to be able to use the same set of APIs for 437 // all the REMAP tables, so define a special RAM_SEL value for MCREMAP that 438 // does not conflict with the existing definitions. 439 // 440 #define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECT_MULTICAST_REMAPRAM (DRF_MASK(NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS) + 1) 441 442 // 443 // NPORT Portstat information 444 // 445 446 // 447 // LS10 supports CREQ0(0), DNGRD(1), ATR(2), ATSD(3), PROBE(4), RSP0(5), CREQ1(6), and RSP1(7) VCs. 448 // But DNGRD(1), ATR(2), ATSD(3), and PROBE(4) will be never used. 449 // 450 #define NVSWITCH_NUM_VCS_LS10 8 451 452 typedef struct 453 { 454 NvU32 count; 455 NvU32 low; 456 NvU32 medium; 457 NvU32 high; 458 NvU32 panic; 459 } 460 NVSWITCH_LATENCY_BINS_LS10; 461 462 typedef struct 463 { 464 NvU32 count; 465 NvU64 start_time_nsec; 466 NvU64 last_read_time_nsec; 467 NVSWITCH_LATENCY_BINS_LS10 accum_latency[NVSWITCH_NUM_LINKS_LS10]; 468 } 469 NVSWITCH_LATENCY_VC_LS10; 470 471 typedef struct 472 { 473 NvU32 sample_interval_msec; 474 NvU64 last_visited_time_nsec; 475 NVSWITCH_LATENCY_VC_LS10 latency[NVSWITCH_NUM_VCS_LS10]; 476 } NVSWITCH_LATENCY_STATS_LS10; 477 478 #define NV_NPORT_PORTSTAT_LS10(_block, _reg, _vc, _hi_lo) (NV_NPORT_PORTSTAT ## _block ## _reg ## _0 ## _hi_lo + \ 479 _vc * (NV_NPORT_PORTSTAT ## _block ## _reg ## _1 ## _hi_lo - NV_NPORT_PORTSTAT ## _block ## _reg ## _0 ## _hi_lo)) 480 481 #define NVSWITCH_NPORT_PORTSTAT_RD32_LS10(_d, _engidx, _block, _reg, _hi_lo, _vc) \ 482 ( \ 483 NVSWITCH_ASSERT(NVSWITCH_IS_LINK_ENG_VALID_LS10(_d, NPORT, _engidx)) \ 484 , \ 485 NVSWITCH_PRINT(_d, MMIO, \ 486 "%s: MEM_RD NPORT_PORTSTAT[%d]: %s,%s,_%s,%s (%06x+%04x)\n", \ 487 __FUNCTION__, \ 488 _engidx, \ 489 #_block, #_reg, #_vc, #_hi_lo, \ 490 NVSWITCH_GET_ENG(_d, NPORT, , _engidx), \ 491 NV_NPORT_PORTSTAT_LS10(_block, _reg, _vc, _hi_lo)) \ 492 , \ 493 nvswitch_reg_read_32(_d, \ 494 NVSWITCH_GET_ENG(_d, NPORT, , _engidx) + \ 495 NV_NPORT_PORTSTAT_LS10(_block, _reg, _vc, _hi_lo)) \ 496 ); \ 497 ((void)(_d)) 498 499 #define NVSWITCH_PORTSTAT_BCAST_WR32_LS10(_d, _block, _reg, _idx, _data) \ 500 { \ 501 NVSWITCH_PRINT(_d, MMIO, \ 502 "%s: BCAST_WR NPORT_PORTSTAT: %s,%s (%06x+%04x) 0x%08x\n", \ 503 __FUNCTION__, \ 504 #_block, #_reg, \ 505 NVSWITCH_GET_ENG(_d, NPORT, _BCAST, 0), \ 506 NV_NPORT_PORTSTAT_LS10(_block, _reg, _idx, ), _data); \ 507 NVSWITCH_OFF_WR32(_d, \ 508 NVSWITCH_GET_ENG(_d, NPORT, _BCAST, 0) + \ 509 NV_NPORT_PORTSTAT_LS10(_block, _reg, _idx, ), _data); \ 510 } 511 512 #define NVSWITCH_DEFERRED_LINK_STATE_CHECK_INTERVAL_NS ((device->bModeContinuousALI ? 15 : 30) *\ 513 NVSWITCH_INTERVAL_1SEC_IN_NS) 514 #define NVSWITCH_DEFERRED_FAULT_UP_CHECK_INTERVAL_NS (12 * NVSWITCH_INTERVAL_1MSEC_IN_NS) 515 516 // Struct used for passing around error masks in error handling functions 517 typedef struct 518 { 519 NvBool bPending; 520 NvU32 regData; 521 } MINION_LINK_INTR; 522 523 typedef struct 524 { 525 NvU32 dl; 526 NvU32 tlcRx0; 527 NvU32 tlcRx0Injected; 528 NvU32 tlcRx1; 529 NvU32 tlcRx1Injected; 530 NvU32 liptLnk; 531 NvU32 liptLnkInjected; 532 MINION_LINK_INTR minionLinkIntr; 533 } NVLINK_LINK_ERROR_INFO_ERR_MASKS, *PNVLINK_LINK_ERROR_INFO_ERR_MASKS; 534 535 typedef struct 536 { 537 NvBool bLinkErrorsCallBackEnabled; 538 NvBool bLinkStateCallBackEnabled; 539 NvU64 lastRetrainTime; 540 NvU64 lastLinkUpTime; 541 } NVLINK_LINK_ERROR_REPORTING_STATE; 542 543 typedef struct 544 { 545 NVLINK_LINK_ERROR_INFO_ERR_MASKS fatalIntrMask; 546 NVLINK_LINK_ERROR_INFO_ERR_MASKS nonFatalIntrMask; 547 } NVLINK_LINK_ERROR_REPORTING_DATA; 548 549 typedef struct 550 { 551 NVLINK_LINK_ERROR_REPORTING_STATE state; 552 NVLINK_LINK_ERROR_REPORTING_DATA data; 553 } NVLINK_LINK_ERROR_REPORTING; 554 555 typedef struct 556 { 557 struct 558 { 559 NVSWITCH_ENGINE_DESCRIPTOR_TYPE common[NVSWITCH_ENGINE_ID_SIZE]; 560 } io; 561 562 NVSWITCH_LIST_LS10_ENGINE_UC(NVSWITCH_DECLARE_ENGINE_UC_LS10) 563 NVSWITCH_LIST_PRI_HUB_LS10_ENGINE(NVSWITCH_DECLARE_ENGINE_UC_LS10) 564 NVSWITCH_LIST_LS10_ENGINE(NVSWITCH_DECLARE_ENGINE_LS10) 565 566 // Interrupts 567 NvU32 intr_minion_dest; 568 569 // VBIOS configuration Data 570 NVSWITCH_BIOS_NVLINK_CONFIG bios_config; 571 572 // GPIO 573 const NVSWITCH_GPIO_INFO *gpio_pin; 574 NvU32 gpio_pin_size; 575 576 // Latency statistics 577 NVSWITCH_LATENCY_STATS_LS10 *latency_stats; 578 579 // External TDIODE info 580 NVSWITCH_TDIODE_INFO_TYPE tdiode; 581 582 // 583 // Book-keep interrupt masks to restore them after reset. 584 // Note: There is no need to book-keep interrupt masks for NVLink units like 585 // DL, MINION, TLC etc. because NVLink init routines would setup them. 586 // 587 struct 588 { 589 NVSWITCH_INTERRUPT_MASK route; 590 NVSWITCH_INTERRUPT_MASK ingress[2]; 591 NVSWITCH_INTERRUPT_MASK egress[2]; 592 NVSWITCH_INTERRUPT_MASK tstate; 593 NVSWITCH_INTERRUPT_MASK sourcetrack; 594 NVSWITCH_INTERRUPT_MASK mc_tstate; 595 NVSWITCH_INTERRUPT_MASK red_tstate; 596 NVSWITCH_INTERRUPT_MASK tile; 597 NVSWITCH_INTERRUPT_MASK tileout; 598 } intr_mask; 599 600 // Ganged Link table 601 NvU64 *ganged_link_table; 602 603 //NVSWITCH Minion core 604 NvU32 minionEngArch; 605 606 NvBool riscvManifestBoot; 607 608 // Nvlink error reporting management 609 NVLINK_LINK_ERROR_REPORTING deferredLinkErrors[NVSWITCH_NUM_LINKS_LS10]; 610 NVSWITCH_DEFERRED_ERROR_REPORTING_ARGS deferredLinkErrorsArgs[NVSWITCH_NUM_LINKS_LS10]; 611 612 } ls10_device; 613 614 // 615 // Helpful IO wrappers 616 // 617 618 #define NVSWITCH_GET_CHIP_DEVICE_LS10(_device) \ 619 ( \ 620 ((_device)->chip_id == NV_PMC_BOOT_42_CHIP_ID_LS10) ? \ 621 ((ls10_device *) _device->chip_device) : \ 622 NULL \ 623 ) 624 625 #define NVSWITCH_ENG_VALID_LS10(_d, _eng, _engidx) \ 626 ( \ 627 ((_engidx < NUM_##_eng##_ENGINE_LS10) && \ 628 (NVSWITCH_GET_CHIP_DEVICE_LS10(_d)->eng##_eng[_engidx].valid)) ? \ 629 NV_TRUE : NV_FALSE \ 630 ) 631 632 #define NVSWITCH_ENG_WR32_LS10(_d, _eng, _bcast, _engidx, _dev, _reg, _data) \ 633 NVSWITCH_ENG_WR32(_d, _eng, _bcast, _engidx, _dev, _reg, _data) 634 635 #define NVSWITCH_ENG_RD32_LS10(_d, _eng, _engidx, _dev, _reg) \ 636 NVSWITCH_ENG_RD32(_d, _eng, , _engidx, _dev, _reg) 637 638 #define NVSWITCH_BCAST_WR32_LS10(_d, _eng, _dev, _reg, _data) \ 639 NVSWITCH_ENG_WR32(_d, _eng, _BCAST, 0, _dev, _reg, _data) 640 641 #define NVSWITCH_BCAST_RD32_LS10(_d, _eng, _dev, _reg) \ 642 NVSWITCH_ENG_RD32(_d, _eng, _BCAST, 0, _dev, _reg) 643 644 #define NVSWITCH_SOE_WR32_LS10(_d, _instance, _dev, _reg, _data) \ 645 NVSWITCH_ENG_WR32(_d, SOE, , _instance, _dev, _reg, _data) 646 647 #define NVSWITCH_SOE_RD32_LS10(_d, _instance, _dev, _reg) \ 648 NVSWITCH_ENG_RD32(_d, SOE, , _instance, _dev, _reg) 649 650 #define NVSWITCH_NPORT_BCAST_WR32_LS10(_d, _dev, _reg, _data) \ 651 NVSWITCH_ENG_WR32(_d, NPORT, _BCAST, 0, _dev, _reg, _data) 652 653 #define NVSWITCH_SAW_WR32_LS10(_d, _dev, _reg, _data) \ 654 NVSWITCH_ENG_WR32(_d, SAW, , 0, _dev, _reg, _data) 655 656 #define NVSWITCH_SAW_RD32_LS10(_d, _dev, _reg) \ 657 NVSWITCH_ENG_RD32(_d, SAW, , 0, _dev, _reg) 658 659 #define NVSWITCH_NPORT_MC_BCAST_WR32_LS10(_d, _dev, _reg, _data) \ 660 NVSWITCH_BCAST_WR32_LS10(_d, NPORT, _dev, _reg, _data) 661 662 // 663 // Tile Column consists of 12 Tile blocks and 11 (really 12) Tileout blocks. 664 // 665 666 #define NUM_NXBAR_TILES_PER_TC_LS10 12 667 #define NUM_NXBAR_TILEOUTS_PER_TC_LS10 12 668 669 #define TILE_INDEX_LS10(_device, _nxbar, _tile) \ 670 ( \ 671 NVSWITCH_ASSERT((_nxbar < NUM_NXBAR_ENGINE_LS10)) \ 672 , \ 673 NVSWITCH_ASSERT((_tile < NUM_NXBAR_TILES_PER_TC_LS10)) \ 674 , \ 675 ((_nxbar) * NUM_NXBAR_TILES_PER_TC_LS10 + (_tile)) \ 676 ) 677 678 #define NVSWITCH_TILE_RD32(_d, _engidx, _dev, _reg) \ 679 NVSWITCH_ENG_RD32(_d, TILE, , _engidx, _dev, _reg) 680 681 #define NVSWITCH_TILE_WR32(_d, _engidx, _dev, _reg, _data) \ 682 NVSWITCH_ENG_WR32(_d, TILE, , _engidx, _dev, _reg, _data) 683 684 #define NVSWITCH_TILEOUT_RD32(_d, _engidx, _dev, _reg) \ 685 NVSWITCH_ENG_RD32(_d, TILEOUT, , _engidx, _dev, _reg) 686 687 #define NVSWITCH_TILEOUT_WR32(_d, _engidx, _dev, _reg, _data) \ 688 NVSWITCH_ENG_WR32(_d, TILEOUT, , _engidx, _dev, _reg, _data) 689 690 // 691 // Per link register access routines 692 // LINK_* MMIO wrappers are used to reference per-link engine instances 693 // 694 695 #define NVSWITCH_IS_LINK_ENG_VALID_LS10(_d, _eng, _linknum) \ 696 NVSWITCH_IS_LINK_ENG_VALID(_d, _linknum, _eng) 697 698 #define NVSWITCH_LINK_OFFSET_LS10(_d, _physlinknum, _eng, _dev, _reg) \ 699 NVSWITCH_LINK_OFFSET(_d, _physlinknum, _eng, _dev, _reg) 700 701 #define NVSWITCH_LINK_WR32_LS10(_d, _physlinknum, _eng, _dev, _reg, _data) \ 702 NVSWITCH_LINK_WR32(_d, _physlinknum, _eng, _dev, _reg, _data) 703 704 #define NVSWITCH_LINK_RD32_LS10(_d, _physlinknum, _eng, _dev, _reg) \ 705 NVSWITCH_LINK_RD32(_d, _physlinknum, _eng, _dev, _reg) 706 707 #define NVSWITCH_LINK_WR32_IDX_LS10(_d, _physlinknum, _eng, _dev, _reg, _idx, _data) \ 708 NVSWITCH_LINK_WR32_IDX(_d, _physlinknum, _eng, _dev, _reg, _idx, _data) 709 710 #define NVSWITCH_LINK_RD32_IDX_LS10(_d, _physlinknum, _eng, _dev, _reg, _idx) \ 711 NVSWITCH_LINK_RD32_IDX(_d, _physlinknum, _eng, _dev, _reg, _idx) 712 713 #define NVSWITCH_MINION_LINK_WR32_LS10(_d, _physlinknum, _dev, _reg, _data) \ 714 NVSWITCH_LINK_WR32(_d, _physlinknum, MINION, _dev, _reg, _data) 715 716 #define NVSWITCH_MINION_LINK_RD32_LS10(_d, _physlinknum, _dev, _reg) \ 717 NVSWITCH_LINK_RD32(_d, _physlinknum, MINION, _dev, _reg) 718 719 // 720 // MINION 721 // 722 723 typedef const struct 724 { 725 NvU32 osCodeOffset; 726 NvU32 osCodeSize; 727 NvU32 osDataOffset; 728 NvU32 osDataSize; 729 NvU32 numApps; 730 NvU32 appCodeStart; 731 NvU32 appDataStart; 732 NvU32 codeOffset; 733 NvU32 codeSize; 734 NvU32 dataOffset; 735 NvU32 dataSize; 736 } FALCON_UCODE_HDR_INFO_LS10, *PFALCON_UCODE_HDR_INFO_LS10; 737 738 typedef const struct 739 { 740 // 741 // Version 1 742 // Version 2 743 // Vesrion 3 = for Partition boot 744 // Vesrion 4 = for eb riscv boot 745 // 746 NvU32 version; // structure version 747 NvU32 bootloaderOffset; 748 NvU32 bootloaderSize; 749 NvU32 bootloaderParamOffset; 750 NvU32 bootloaderParamSize; 751 NvU32 riscvElfOffset; 752 NvU32 riscvElfSize; 753 NvU32 appVersion; // Changelist number associated with the image 754 // 755 // Manifest contains information about Monitor and it is 756 // input to BR 757 // 758 NvU32 manifestOffset; 759 NvU32 manifestSize; 760 // 761 // Monitor Data offset within RISCV image and size 762 // 763 NvU32 monitorDataOffset; 764 NvU32 monitorDataSize; 765 // 766 // Monitor Code offset withtin RISCV image and size 767 // 768 NvU32 monitorCodeOffset; 769 NvU32 monitorCodeSize; 770 NvU32 bIsMonitorEnabled; 771 // 772 // Swbrom Code offset within RISCV image and size 773 // 774 NvU32 swbromCodeOffset; 775 NvU32 swbromCodeSize; 776 // 777 // Swbrom Data offset within RISCV image and size 778 // 779 NvU32 swbromDataOffset; 780 NvU32 swbromDataSize; 781 } RISCV_UCODE_HDR_INFO_LS10, *PRISCV_UCODE_HDR_INFO_LS10; 782 783 // 784 // defines used by internal ls10 functions to get 785 // specific clock status 786 // 787 #define NVSWITCH_PER_LINK_CLOCK_RXCLK 0 788 #define NVSWITCH_PER_LINK_CLOCK_TXCLK 1 789 #define NVSWITCH_PER_LINK_CLOCK_NCISOCCLK 2 790 #define NVSWITCH_PER_LINK_CLOCK_NUM 3 791 #define NVSWITCH_PER_LINK_CLOCK_SET(_name) BIT(NVSWITCH_PER_LINK_CLOCK_##_name) 792 // 793 // HAL functions shared by LR10 and used by LS10 794 // 795 796 #define nvswitch_is_link_valid_ls10 nvswitch_is_link_valid_lr10 797 #define nvswitch_is_link_in_use_ls10 nvswitch_is_link_in_use_lr10 798 799 #define nvswitch_deassert_link_reset_ls10 nvswitch_deassert_link_reset_lr10 800 #define nvswitch_determine_platform_ls10 nvswitch_determine_platform_lr10 801 #define nvswitch_get_swap_clk_default_ls10 nvswitch_get_swap_clk_default_lr10 802 #define nvswitch_post_init_device_setup_ls10 nvswitch_post_init_device_setup_lr10 803 #define nvswitch_set_training_error_info_ls10 nvswitch_set_training_error_info_lr10 804 #define nvswitch_init_scratch_ls10 nvswitch_init_scratch_lr10 805 #define nvswitch_hw_counter_shutdown_ls10 nvswitch_hw_counter_shutdown_lr10 806 #define nvswitch_hw_counter_read_counter_ls10 nvswitch_hw_counter_read_counter_lr10 807 808 #define nvswitch_ecc_writeback_task_ls10 nvswitch_ecc_writeback_task_lr10 809 #define nvswitch_ctrl_get_routing_id_ls10 nvswitch_ctrl_get_routing_id_lr10 810 #define nvswitch_ctrl_set_routing_id_valid_ls10 nvswitch_ctrl_set_routing_id_valid_lr10 811 #define nvswitch_ctrl_set_routing_id_ls10 nvswitch_ctrl_set_routing_id_lr10 812 #define nvswitch_ctrl_set_routing_lan_ls10 nvswitch_ctrl_set_routing_lan_lr10 813 #define nvswitch_ctrl_get_routing_lan_ls10 nvswitch_ctrl_get_routing_lan_lr10 814 #define nvswitch_ctrl_set_routing_lan_valid_ls10 nvswitch_ctrl_set_routing_lan_valid_lr10 815 #define nvswitch_ctrl_set_ingress_request_table_ls10 nvswitch_ctrl_set_ingress_request_table_lr10 816 #define nvswitch_ctrl_get_ingress_request_table_ls10 nvswitch_ctrl_get_ingress_request_table_lr10 817 #define nvswitch_ctrl_set_ingress_request_valid_ls10 nvswitch_ctrl_set_ingress_request_valid_lr10 818 #define nvswitch_ctrl_get_ingress_response_table_ls10 nvswitch_ctrl_get_ingress_response_table_lr10 819 #define nvswitch_ctrl_set_ingress_response_table_ls10 nvswitch_ctrl_set_ingress_response_table_lr10 820 821 #define nvswitch_ctrl_get_info_ls10 nvswitch_ctrl_get_info_lr10 822 823 #define nvswitch_ctrl_set_switch_port_config_ls10 nvswitch_ctrl_set_switch_port_config_lr10 824 #define nvswitch_ctrl_get_throughput_counters_ls10 nvswitch_ctrl_get_throughput_counters_lr10 825 826 #define nvswitch_save_nvlink_seed_data_from_minion_to_inforom_ls10 nvswitch_save_nvlink_seed_data_from_minion_to_inforom_lr10 827 #define nvswitch_store_seed_data_from_inforom_to_corelib_ls10 nvswitch_store_seed_data_from_inforom_to_corelib_lr10 828 #define nvswitch_corelib_clear_link_state_ls10 nvswitch_corelib_clear_link_state_lr10 829 830 #define nvswitch_read_oob_blacklist_state_ls10 nvswitch_read_oob_blacklist_state_lr10 831 832 #define nvswitch_corelib_add_link_ls10 nvswitch_corelib_add_link_lr10 833 #define nvswitch_corelib_remove_link_ls10 nvswitch_corelib_remove_link_lr10 834 #define nvswitch_corelib_set_tl_link_mode_ls10 nvswitch_corelib_set_tl_link_mode_lr10 835 #define nvswitch_corelib_set_rx_mode_ls10 nvswitch_corelib_set_rx_mode_lr10 836 #define nvswitch_corelib_set_rx_detect_ls10 nvswitch_corelib_set_rx_detect_lr10 837 #define nvswitch_corelib_write_discovery_token_ls10 nvswitch_corelib_write_discovery_token_lr10 838 #define nvswitch_corelib_read_discovery_token_ls10 nvswitch_corelib_read_discovery_token_lr10 839 840 #define nvswitch_inforom_ecc_log_error_event_ls10 nvswitch_inforom_ecc_log_error_event_lr10 841 #define nvswitch_inforom_ecc_get_errors_ls10 nvswitch_inforom_ecc_get_errors_lr10 842 #define nvswitch_inforom_bbx_get_sxid_ls10 nvswitch_inforom_bbx_get_sxid_lr10 843 844 #define nvswitch_vbios_read_structure_ls10 nvswitch_vbios_read_structure_lr10 845 846 #define nvswitch_setup_system_registers_ls10 nvswitch_setup_system_registers_lr10 847 848 #define nvswitch_minion_get_initoptimize_status_ls10 nvswitch_minion_get_initoptimize_status_lr10 849 850 #define nvswitch_poll_sublink_state_ls10 nvswitch_poll_sublink_state_lr10 851 #define nvswitch_setup_link_loopback_mode_ls10 nvswitch_setup_link_loopback_mode_lr10 852 853 #define nvswitch_link_lane_reversed_ls10 nvswitch_link_lane_reversed_lr10 854 855 #define nvswitch_i2c_set_hw_speed_mode_ls10 nvswitch_i2c_set_hw_speed_mode_lr10 856 857 #define nvswitch_ctrl_get_err_info_ls10 nvswitch_ctrl_get_err_info_lr10 858 859 NvlStatus nvswitch_ctrl_get_err_info_lr10(nvswitch_device *device, NVSWITCH_NVLINK_GET_ERR_INFO_PARAMS *ret); 860 861 NvBool nvswitch_is_link_valid_lr10(nvswitch_device *device, NvU32 link_id); 862 NvBool nvswitch_is_link_in_use_lr10(nvswitch_device *device, NvU32 link_id); 863 864 NvlStatus nvswitch_initialize_device_state_lr10(nvswitch_device *device); 865 NvlStatus nvswitch_deassert_link_reset_lr10(nvswitch_device *device, nvlink_link *link); 866 void nvswitch_determine_platform_lr10(nvswitch_device *device); 867 NvU32 nvswitch_get_swap_clk_default_lr10(nvswitch_device *device); 868 NvlStatus nvswitch_post_init_device_setup_lr10(nvswitch_device *device); 869 NvlStatus nvswitch_set_training_error_info_lr10(nvswitch_device *device, NVSWITCH_SET_TRAINING_ERROR_INFO_PARAMS *pLinkTrainingErrorInfoParams); 870 void nvswitch_init_scratch_lr10(nvswitch_device *device); 871 void nvswitch_hw_counter_shutdown_lr10(nvswitch_device *device); 872 NvU64 nvswitch_hw_counter_read_counter_lr10(nvswitch_device *device); 873 874 void nvswitch_ecc_writeback_task_lr10(nvswitch_device *device); 875 NvlStatus nvswitch_ctrl_get_routing_id_lr10(nvswitch_device *device, NVSWITCH_GET_ROUTING_ID_PARAMS *params); 876 NvlStatus nvswitch_ctrl_set_routing_id_valid_lr10(nvswitch_device *device, NVSWITCH_SET_ROUTING_ID_VALID *p); 877 NvlStatus nvswitch_ctrl_set_routing_id_lr10(nvswitch_device *device, NVSWITCH_SET_ROUTING_ID *p); 878 NvlStatus nvswitch_ctrl_set_routing_lan_lr10(nvswitch_device *device, NVSWITCH_SET_ROUTING_LAN *p); 879 NvlStatus nvswitch_ctrl_get_routing_lan_lr10(nvswitch_device *device, NVSWITCH_GET_ROUTING_LAN_PARAMS *params); 880 NvlStatus nvswitch_ctrl_set_routing_lan_valid_lr10(nvswitch_device *device, NVSWITCH_SET_ROUTING_LAN_VALID *p); 881 NvlStatus nvswitch_ctrl_set_ingress_request_table_lr10(nvswitch_device *device, NVSWITCH_SET_INGRESS_REQUEST_TABLE *p); 882 NvlStatus nvswitch_ctrl_get_ingress_request_table_lr10(nvswitch_device *device, NVSWITCH_GET_INGRESS_REQUEST_TABLE_PARAMS *params); 883 NvlStatus nvswitch_ctrl_set_ingress_request_valid_lr10(nvswitch_device *device, NVSWITCH_SET_INGRESS_REQUEST_VALID *p); 884 NvlStatus nvswitch_ctrl_get_ingress_response_table_lr10(nvswitch_device *device, NVSWITCH_GET_INGRESS_RESPONSE_TABLE_PARAMS *params); 885 NvlStatus nvswitch_ctrl_set_ingress_response_table_lr10(nvswitch_device *device, NVSWITCH_SET_INGRESS_RESPONSE_TABLE *p); 886 887 NvlStatus nvswitch_ctrl_get_nvlink_status_lr10(nvswitch_device *device, NVSWITCH_GET_NVLINK_STATUS_PARAMS *ret); 888 NvlStatus nvswitch_ctrl_get_nvlink_status_ls10(nvswitch_device *device, NVSWITCH_GET_NVLINK_STATUS_PARAMS *ret); 889 890 NvlStatus nvswitch_ctrl_get_info_lr10(nvswitch_device *device, NVSWITCH_GET_INFO *p); 891 892 NvlStatus nvswitch_ctrl_set_switch_port_config_lr10(nvswitch_device *device, NVSWITCH_SET_SWITCH_PORT_CONFIG *p); 893 NvlStatus nvswitch_ctrl_get_throughput_counters_lr10(nvswitch_device *device, NVSWITCH_GET_THROUGHPUT_COUNTERS_PARAMS *p); 894 void nvswitch_save_nvlink_seed_data_from_minion_to_inforom_lr10(nvswitch_device *device, NvU32 linkId); 895 void nvswitch_store_seed_data_from_inforom_to_corelib_lr10(nvswitch_device *device); 896 NvlStatus nvswitch_read_oob_blacklist_state_lr10(nvswitch_device *device); 897 898 NvlStatus nvswitch_corelib_add_link_lr10(nvlink_link *link); 899 NvlStatus nvswitch_corelib_remove_link_lr10(nvlink_link *link); 900 NvlStatus nvswitch_corelib_get_dl_link_mode_lr10(nvlink_link *link, NvU64 *mode); 901 NvlStatus nvswitch_corelib_set_tl_link_mode_lr10(nvlink_link *link, NvU64 mode, NvU32 flags); 902 NvlStatus nvswitch_corelib_get_tx_mode_lr10(nvlink_link *link, NvU64 *mode, NvU32 *subMode); 903 NvlStatus nvswitch_corelib_set_rx_mode_lr10(nvlink_link *link, NvU64 mode, NvU32 flags); 904 NvlStatus nvswitch_corelib_get_rx_mode_lr10(nvlink_link *link, NvU64 *mode, NvU32 *subMode); 905 NvlStatus nvswitch_corelib_set_rx_detect_lr10(nvlink_link *link, NvU32 flags); 906 NvlStatus nvswitch_corelib_write_discovery_token_lr10(nvlink_link *link, NvU64 token); 907 NvlStatus nvswitch_corelib_read_discovery_token_lr10(nvlink_link *link, NvU64 *token); 908 NvlStatus nvswitch_corelib_set_dl_link_mode_lr10(nvlink_link *link, NvU64 mode, NvU32 flags); 909 NvlStatus nvswitch_corelib_set_tx_mode_lr10(nvlink_link *link, NvU64 mode, NvU32 flags); 910 NvlStatus nvswitch_corelib_get_tl_link_mode_lr10(nvlink_link *link, NvU64 *mode); 911 void nvswitch_init_buffer_ready_lr10(nvswitch_device *device, nvlink_link *link, NvBool bNportBufferReady); 912 913 NvlStatus nvswitch_inforom_ecc_log_error_event_lr10(nvswitch_device *device, INFOROM_ECC_OBJECT *pEccGeneric, INFOROM_NVS_ECC_ERROR_EVENT *err_event); 914 NvlStatus nvswitch_inforom_ecc_get_errors_lr10(nvswitch_device *device, NVSWITCH_GET_ECC_ERROR_COUNTS_PARAMS *params); 915 NvlStatus nvswitch_inforom_bbx_get_sxid_lr10(nvswitch_device *device, NVSWITCH_GET_SXIDS_PARAMS *params); 916 917 void nvswitch_init_dlpl_interrupts_lr10(nvlink_link *link); 918 919 NvlStatus nvswitch_vbios_read_structure_lr10(nvswitch_device *device, void *structure, NvU32 offset, NvU32 *ppacked_size, const char *format); 920 921 NvlStatus nvswitch_setup_system_registers_lr10(nvswitch_device *device); 922 923 NvlStatus nvswitch_minion_get_initoptimize_status_lr10(nvswitch_device *device, NvU32 linkId); 924 925 NvlStatus nvswitch_poll_sublink_state_lr10(nvswitch_device *device, nvlink_link *link); 926 void nvswitch_setup_link_loopback_mode_lr10(nvswitch_device *device, NvU32 linkNumber); 927 928 NvBool nvswitch_link_lane_reversed_lr10(nvswitch_device *device, NvU32 linkId); 929 void nvswitch_store_topology_information_lr10(nvswitch_device *device, nvlink_link *link); 930 931 NvlStatus nvswitch_request_tl_link_state_lr10(nvlink_link *link, NvU32 tlLinkState, NvBool bSync); 932 NvlStatus nvswitch_wait_for_tl_request_ready_lr10(nvlink_link *link); 933 934 NvlStatus nvswitch_parse_bios_image_lr10(nvswitch_device *device); 935 NvU32 nvswitch_i2c_get_port_info_ls10(nvswitch_device *device, NvU32 port); 936 NvU32 nvswitch_i2c_get_port_info_lr10(nvswitch_device *device, NvU32 port); 937 void nvswitch_i2c_set_hw_speed_mode_lr10(nvswitch_device *device, NvU32 port, NvU32 speedMode); 938 NvlStatus nvswitch_ctrl_i2c_indexed_lr10(nvswitch_device *device, NVSWITCH_CTRL_I2C_INDEXED_PARAMS *pParams); 939 void nvswitch_corelib_clear_link_state_lr10(nvlink_link *link); 940 941 // 942 // Internal function declarations 943 // 944 945 NvlStatus nvswitch_corelib_set_dl_link_mode_ls10(nvlink_link *link, NvU64 mode, NvU32 flags); 946 NvlStatus nvswitch_corelib_set_tx_mode_ls10(nvlink_link *link, NvU64 mode, NvU32 flags); 947 void nvswitch_init_lpwr_regs_ls10(nvlink_link *link); 948 void nvswitch_program_l1_scratch_reg_ls10(nvswitch_device *device, NvU32 linkNumber); 949 950 NvlStatus nvswitch_minion_service_falcon_interrupts_ls10(nvswitch_device *device, NvU32 instance); 951 952 NvlStatus nvswitch_device_discovery_ls10(nvswitch_device *device, NvU32 discovery_offset); 953 void nvswitch_filter_discovery_ls10(nvswitch_device *device); 954 NvlStatus nvswitch_process_discovery_ls10(nvswitch_device *device); 955 void nvswitch_lib_enable_interrupts_ls10(nvswitch_device *device); 956 void nvswitch_lib_disable_interrupts_ls10(nvswitch_device *device); 957 NvlStatus nvswitch_lib_service_interrupts_ls10(nvswitch_device *device); 958 NvlStatus nvswitch_lib_check_interrupts_ls10(nvswitch_device *device); 959 void nvswitch_initialize_interrupt_tree_ls10(nvswitch_device *device); 960 void nvswitch_corelib_training_complete_ls10(nvlink_link *link); 961 NvlStatus nvswitch_init_nport_ls10(nvswitch_device *device); 962 NvlStatus nvswitch_corelib_get_rx_detect_ls10(nvlink_link *link); 963 void nvswitch_reset_persistent_link_hw_state_ls10(nvswitch_device *device, NvU32 linkNumber); 964 NvlStatus nvswitch_minion_get_rxdet_status_ls10(nvswitch_device *device, NvU32 linkId); 965 NvlStatus nvswitch_minion_restore_seed_data_ls10(nvswitch_device *device, NvU32 linkId, NvU32 *seedData); 966 NvlStatus nvswitch_minion_set_sim_mode_ls10(nvswitch_device *device, nvlink_link *link); 967 NvlStatus nvswitch_minion_set_smf_settings_ls10(nvswitch_device *device, nvlink_link *link); 968 NvlStatus nvswitch_minion_select_uphy_tables_ls10(nvswitch_device *device, nvlink_link *link); 969 NvlStatus nvswitch_set_training_mode_ls10(nvswitch_device *device); 970 NvlStatus nvswitch_corelib_get_tl_link_mode_ls10(nvlink_link *link, NvU64 *mode); 971 NvU32 nvswitch_get_sublink_width_ls10(nvswitch_device *device,NvU32 linkNumber); 972 NvlStatus nvswitch_parse_bios_image_ls10(nvswitch_device *device); 973 NvBool nvswitch_is_link_in_reset_ls10(nvswitch_device *device, nvlink_link *link); 974 void nvswitch_corelib_get_uphy_load_ls10(nvlink_link *link, NvBool *bUnlocked); 975 NvlStatus nvswitch_ctrl_get_nvlink_lp_counters_ls10(nvswitch_device *device, NVSWITCH_GET_NVLINK_LP_COUNTERS_PARAMS *params); 976 void nvswitch_init_buffer_ready_ls10(nvswitch_device *device, nvlink_link *link, NvBool bNportBufferReady); 977 void nvswitch_apply_recal_settings_ls10(nvswitch_device *device, nvlink_link *link); 978 NvlStatus nvswitch_corelib_get_dl_link_mode_ls10(nvlink_link *link, NvU64 *mode); 979 NvlStatus nvswitch_corelib_get_tx_mode_ls10(nvlink_link *link, NvU64 *mode, NvU32 *subMode); 980 NvlStatus nvswitch_corelib_get_rx_mode_ls10(nvlink_link *link, NvU64 *mode, NvU32 *subMode); 981 NvlStatus nvswitch_ctrl_get_sw_info_ls10(nvswitch_device *device, NVSWITCH_GET_SW_INFO_PARAMS *p); 982 NvlStatus nvswitch_launch_ALI_link_training_ls10(nvswitch_device *device, nvlink_link *link, NvBool bSync); 983 NvlStatus nvswitch_service_nvldl_fatal_link_ls10(nvswitch_device *device, NvU32 nvliptInstance, NvU32 link); 984 NvlStatus nvswitch_ctrl_inband_send_data_ls10(nvswitch_device *device, NVSWITCH_INBAND_SEND_DATA_PARAMS *p); 985 NvlStatus nvswitch_ctrl_inband_read_data_ls10(nvswitch_device *device, NVSWITCH_INBAND_READ_DATA_PARAMS *p); 986 void nvswitch_send_inband_nack_ls10(nvswitch_device *device, NvU32 *msghdr, NvU32 linkId); 987 NvU32 nvswitch_get_max_persistent_message_count_ls10(nvswitch_device *device); 988 NvlStatus nvswitch_service_minion_link_ls10(nvswitch_device *device, NvU32 nvliptInstance); 989 void nvswitch_apply_recal_settings_ls10(nvswitch_device *device, nvlink_link *link); 990 void nvswitch_store_topology_information_ls10(nvswitch_device *device, nvlink_link *link); 991 NvlStatus nvswitch_ctrl_i2c_indexed_ls10(nvswitch_device *device, NVSWITCH_CTRL_I2C_INDEXED_PARAMS *pParams); 992 NvBool nvswitch_i2c_is_device_access_allowed_ls10(nvswitch_device *device, NvU32 port, NvU8 addr, NvBool bIsRead); 993 NvlStatus nvswitch_minion_get_ali_debug_registers_ls10(nvswitch_device *device, nvlink_link *link, NVSWITCH_MINION_ALI_DEBUG_REGISTERS *params); 994 void nvswitch_execute_unilateral_link_shutdown_ls10(nvlink_link *link); 995 void nvswitch_setup_link_system_registers_ls10(nvswitch_device *device, nvlink_link *link); 996 void nvswitch_load_link_disable_settings_ls10(nvswitch_device *device, nvlink_link *link); 997 void nvswitch_link_disable_interrupts_ls10(nvswitch_device *device, NvU32 link); 998 void nvswitch_init_dlpl_interrupts_ls10(nvlink_link *link); 999 void nvswitch_set_dlpl_interrupts_ls10(nvlink_link *link); 1000 void nvswitch_service_minion_all_links_ls10(nvswitch_device *device); 1001 NvlStatus nvswitch_ctrl_get_board_part_number_ls10(nvswitch_device *device, NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p); 1002 void nvswitch_create_deferred_link_state_check_task_ls10(nvswitch_device *device, NvU32 nvlipt_instance, NvU32 link); 1003 NvlStatus nvswitch_request_tl_link_state_ls10(nvlink_link *link, NvU32 tlLinkState, NvBool bSync); 1004 NvlStatus nvswitch_ctrl_get_link_l1_capability_ls10(nvswitch_device *device, NvU32 linkId, NvBool *isL1Capable); 1005 NvlStatus nvswitch_ctrl_get_link_l1_threshold_ls10(nvswitch_device *device, NvU32 linkNum, NvU32 *lpThreshold); 1006 NvlStatus nvswitch_ctrl_set_link_l1_threshold_ls10(nvlink_link *link, NvU32 lpEntryThreshold); 1007 NvlStatus nvswitch_get_board_id_ls10(nvswitch_device *device, NvU16 *boardId); 1008 1009 // 1010 // SU generated functions 1011 // 1012 1013 NvlStatus nvswitch_nvs_top_prod_ls10(nvswitch_device *device); 1014 NvlStatus nvswitch_apply_prod_nvlw_ls10(nvswitch_device *device); 1015 NvlStatus nvswitch_apply_prod_nxbar_ls10(nvswitch_device *device); 1016 1017 NvlStatus nvswitch_launch_ALI_ls10(nvswitch_device *device); 1018 1019 NvlStatus nvswitch_ctrl_set_mc_rid_table_ls10(nvswitch_device *device, NVSWITCH_SET_MC_RID_TABLE_PARAMS *p); 1020 NvlStatus nvswitch_ctrl_get_mc_rid_table_ls10(nvswitch_device *device, NVSWITCH_GET_MC_RID_TABLE_PARAMS *p); 1021 1022 void nvswitch_service_minion_all_links_ls10(nvswitch_device *device); 1023 1024 NvBool nvswitch_is_inforom_supported_ls10(nvswitch_device *device); 1025 void nvswitch_set_error_rate_threshold_ls10(nvlink_link *link, NvBool bIsDefault); 1026 void nvswitch_configure_error_rate_threshold_interrupt_ls10(nvlink_link *link, NvBool bEnable); 1027 NvlStatus nvswitch_reset_and_train_link_ls10(nvswitch_device *device, nvlink_link *link); 1028 NvBool nvswitch_are_link_clocks_on_ls10(nvswitch_device *device, nvlink_link *link, NvU32 clocksMask); 1029 NvBool nvswitch_does_link_need_termination_enabled_ls10(nvswitch_device *device, nvlink_link *link); 1030 NvlStatus nvswitch_link_termination_setup_ls10(nvswitch_device *device, nvlink_link* link); 1031 void nvswitch_get_error_rate_threshold_ls10(nvlink_link *link); 1032 void nvswitch_fsp_update_cmdq_head_tail_ls10(nvswitch_device *device, NvU32 queueHead, NvU32 queueTail); 1033 void nvswitch_fsp_get_cmdq_head_tail_ls10(nvswitch_device *device, NvU32 *pQueueHead, NvU32 *pQueueTail); 1034 void nvswitch_fsp_update_msgq_head_tail_ls10(nvswitch_device *device, NvU32 msgqHead, NvU32 msgqTail); 1035 void nvswitch_fsp_get_msgq_head_tail_ls10(nvswitch_device *device, NvU32 *pMsgqHead, NvU32 *pMsgqTail); 1036 NvU32 nvswitch_fsp_get_channel_size_ls10(nvswitch_device *device); 1037 NvU8 nvswitch_fsp_nvdm_to_seid_ls10(nvswitch_device *device, NvU8 nvdmType); 1038 NvU32 nvswitch_fsp_create_mctp_header_ls10(nvswitch_device *device, NvU8 som, NvU8 eom, NvU8 seid, NvU8 seq); 1039 NvU32 nvswitch_fsp_create_nvdm_header_ls10(nvswitch_device *device, NvU32 nvdmType); 1040 NvlStatus nvswitch_fsp_get_packet_info_ls10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size, NvU8 *pPacketState, NvU8 *pTag); 1041 NvlStatus nvswitch_fsp_validate_mctp_payload_header_ls10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); 1042 NvlStatus nvswitch_fsp_process_nvdm_msg_ls10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); 1043 NvlStatus nvswitch_fsp_process_cmd_response_ls10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); 1044 NvlStatus nvswitch_fsp_config_ememc_ls10(nvswitch_device *device, NvU32 offset, NvBool bAincw, NvBool bAincr); 1045 NvlStatus nvswitch_fsp_write_to_emem_ls10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); 1046 NvlStatus nvswitch_fsp_read_from_emem_ls10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); 1047 NvlStatus nvswitch_fsp_error_code_to_nvlstatus_map_ls10(nvswitch_device *device, NvU32 errorCode); 1048 NvlStatus nvswitch_fsprpc_get_caps_ls10(nvswitch_device *device, NVSWITCH_FSPRPC_GET_CAPS_PARAMS *params); 1049 NvlStatus nvswitch_detect_tnvl_mode_ls10(nvswitch_device *device); 1050 NvBool nvswitch_is_tnvl_mode_enabled_ls10(nvswitch_device *device); 1051 NvBool nvswitch_is_tnvl_mode_locked_ls10(nvswitch_device *device); 1052 NvlStatus nvswitch_tnvl_get_attestation_certificate_chain_ls10(nvswitch_device *device, NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN_PARAMS *params); 1053 NvlStatus nvswitch_tnvl_get_attestation_report_ls10(nvswitch_device *device, NVSWITCH_GET_ATTESTATION_REPORT_PARAMS *params); 1054 NvlStatus nvswitch_tnvl_send_fsp_lock_config_ls10(nvswitch_device *device); 1055 NvlStatus nvswitch_tnvl_get_status_ls10(nvswitch_device *device, NVSWITCH_GET_TNVL_STATUS_PARAMS *params); 1056 1057 NvlStatus nvswitch_ctrl_get_soe_heartbeat_ls10(nvswitch_device *device, NVSWITCH_GET_SOE_HEARTBEAT_PARAMS *p); 1058 NvlStatus nvswitch_cci_enable_iobist_ls10(nvswitch_device *device, NvU32 linkNumber, NvBool bEnable); 1059 NvlStatus nvswitch_cci_initialization_sequence_ls10(nvswitch_device *device, NvU32 linkNumber); 1060 NvlStatus nvswitch_cci_deinitialization_sequence_ls10(nvswitch_device *device, NvU32 linkNumber); 1061 void nvswitch_update_link_state_led_ls10(nvswitch_device *device); 1062 void nvswitch_led_shutdown_ls10(nvswitch_device *device); 1063 1064 #endif //_LS10_H_ 1065 1066