1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2005-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 #pragma once 24 25 #include <nvtypes.h> 26 27 // 28 // This file was generated with FINN, an NVIDIA coding tool. 29 // Source file: ctrl/ctrl0000/ctrl0000system.finn 30 // 31 32 #include "ctrl/ctrlxxxx.h" 33 #include "ctrl/ctrl0000/ctrl0000base.h" 34 35 /* NV01_ROOT (client) system control commands and parameters */ 36 37 /* 38 * NV0000_CTRL_CMD_SYSTEM_GET_FEATURES 39 * 40 * This command returns a mask of supported features for the SYSTEM category 41 * of the 0000 class. 42 * 43 * Valid features include: 44 * 45 * NV0000_CTRL_GET_FEATURES_SLI 46 * When this bit is set, SLI is supported. 47 * NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT 48 * When this bit is set, EFI has initialized core channel 49 * NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED 50 * When this bit is set, RM test only code is supported. 51 * 52 * Possible status values returned are: 53 * NV_OK 54 * NV_ERR_INVALID_STATE 55 */ 56 #define NV0000_CTRL_CMD_SYSTEM_GET_FEATURES (0x1f0U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID" */ 57 58 #define NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID (0xF0U) 59 60 typedef struct NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS { 61 NvU32 featuresMask; 62 } NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS; 63 64 65 66 /* Valid feature values */ 67 #define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI 0:0 68 #define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE (0x00000000U) 69 #define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE (0x00000001U) 70 71 #define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT 2:2 72 #define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE (0x00000000U) 73 #define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE (0x00000001U) 74 75 #define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING 3:3 76 #define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_FALSE (0x00000000U) 77 #define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_TRUE (0x00000001U) 78 79 #define NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED 4:4 80 #define NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_FALSE (0x00000000U) 81 #define NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_TRUE (0x00000001U) 82 /* 83 * NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION 84 * 85 * This command returns the current driver information. 86 * The first time this is called the size of strings is 87 * set with the greater of NV_BUILD_BRANCH_VERSION and 88 * NV_DISPLAY_DRIVER_TITLE. The client then allocates memory 89 * of size sizeOfStrings for pVersionBuffer and pTitleBuffer 90 * and calls the command again to receive driver info. 91 * 92 * sizeOfStrings 93 * This field returns the size in bytes of the pVersionBuffer and 94 * pTitleBuffer strings. 95 * pDriverVersionBuffer 96 * This field returns the version (NV_VERSION_STRING). 97 * pVersionBuffer 98 * This field returns the version (NV_BUILD_BRANCH_VERSION). 99 * pTitleBuffer 100 * This field returns the title (NV_DISPLAY_DRIVER_TITLE). 101 * changelistNumber 102 * This field returns the changelist value (NV_BUILD_CHANGELIST_NUM). 103 * officialChangelistNumber 104 * This field returns the last official changelist value 105 * (NV_LAST_OFFICIAL_CHANGELIST_NUM). 106 * 107 * Possible status values returned are: 108 * NV_OK 109 * NV_ERR_INVALID_PARAM_STRUCT 110 */ 111 112 #define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION (0x101U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID" */ 113 114 #define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID (0x1U) 115 116 typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS { 117 NvU32 sizeOfStrings; 118 NV_DECLARE_ALIGNED(NvP64 pDriverVersionBuffer, 8); 119 NV_DECLARE_ALIGNED(NvP64 pVersionBuffer, 8); 120 NV_DECLARE_ALIGNED(NvP64 pTitleBuffer, 8); 121 NvU32 changelistNumber; 122 NvU32 officialChangelistNumber; 123 } NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS; 124 125 /* 126 * NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO 127 * 128 * This command returns system CPU information. 129 * 130 * type 131 * This field returns the processor type. 132 * Legal processor types include: 133 * Intel processors: 134 * P55 : P55C - MMX 135 * P6 : PPro 136 * P2 : PentiumII 137 * P2XC : Xeon & Celeron 138 * CELA : Celeron-A 139 * P3 : Pentium-III 140 * P3_INTL2 : Pentium-III w/integrated L2 (fullspeed, on die, 256K) 141 * P4 : Pentium 4 142 * CORE2 : Core2 Duo Conroe 143 * AMD processors 144 * K62 : K6-2 w/ 3DNow 145 * IDT/Centaur processors 146 * C6 : WinChip C6 147 * C62 : WinChip 2 w/ 3DNow 148 * Cyrix processors 149 * GX : MediaGX 150 * M1 : 6x86 151 * M2 : M2 152 * MGX : MediaGX w/ MMX 153 * Transmeta processors 154 * TM_CRUSOE : Transmeta Crusoe(tm) 155 * PowerPC processors 156 * PPC603 : PowerPC 603 157 * PPC604 : PowerPC 604 158 * PPC750 : PowerPC 750 159 * 160 * capabilities 161 * This field returns the capabilities of the processor. 162 * Legal processor capabilities include: 163 * MMX : supports MMX 164 * SSE : supports SSE 165 * 3DNOW : supports 3DNow 166 * SSE2 : supports SSE2 167 * SFENCE : supports SFENCE 168 * WRITE_COMBINING : supports write-combining 169 * ALTIVEC : supports ALTIVEC 170 * PUT_NEEDS_IO : requires OUT inst w/PUT updates 171 * NEEDS_WC_WORKAROUND : requires workaround for P4 write-combining bug 172 * 3DNOW_EXT : supports 3DNow Extensions 173 * MMX_EXT : supports MMX Extensions 174 * CMOV : supports CMOV 175 * CLFLUSH : supports CLFLUSH 176 * SSE3 : supports SSE3 177 * NEEDS_WAR_124888 : requires write to GPU while spinning on 178 * : GPU value 179 * HT : support hyper-threading 180 * clock 181 * This field returns the processor speed in MHz. 182 * L1DataCacheSize 183 * This field returns the level 1 data (or unified) cache size 184 * in kilobytes. 185 * L2DataCacheSize 186 * This field returns the level 2 data (or unified) cache size 187 * in kilobytes. 188 * dataCacheLineSize 189 * This field returns the bytes per line in the level 1 data cache. 190 * numLogicalCpus 191 * This field returns the number of logical processors. On Intel x86 192 * systems that support it, this value will incorporate the current state 193 * of HyperThreading. 194 * numPhysicalCpus 195 * This field returns the number of physical processors. 196 * name 197 * This field returns the CPU name in ASCII string format. 198 * family 199 * Vendor defined Family and Extended Family combined 200 * model 201 * Vendor defined Model and Extended Model combined 202 * stepping 203 * Silicon stepping 204 * bCCEnabled 205 * Confidentail compute enabled/disabled state 206 * 207 * Possible status values returned are: 208 * NV_OK 209 * NV_ERR_INVALID_PARAM_STRUCT 210 */ 211 #define NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO (0x102U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID" */ 212 213 #define NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID (0x2U) 214 215 typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS { 216 NvU32 type; /* processor type */ 217 NvU32 capabilities; /* processor caps */ 218 NvU32 clock; /* processor speed (MHz) */ 219 NvU32 L1DataCacheSize; /* L1 dcache size (KB) */ 220 NvU32 L2DataCacheSize; /* L2 dcache size (KB) */ 221 NvU32 dataCacheLineSize; /* L1 dcache bytes/line */ 222 NvU32 numLogicalCpus; /* logial processor cnt */ 223 NvU32 numPhysicalCpus; /* physical processor cnt*/ 224 NvU8 name[52]; /* embedded cpu name */ 225 NvU32 family; /* Vendor defined Family and Extended Family combined */ 226 NvU32 model; /* Vendor defined Model and Extended Model combined */ 227 NvU8 stepping; /* Silicon stepping */ 228 NvU32 coresOnDie; /* cpu cores per die */ 229 NvBool bCCEnabled; /* CC enabled on cpu */ 230 } NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS; 231 232 // Macros for CPU family information 233 #define NV0000_CTRL_SYSTEM_CPU_FAMILY 3:0 234 #define NV0000_CTRL_SYSTEM_CPU_EXTENDED_FAMILY 11:4 235 236 // Macros for CPU model information 237 #define NV0000_CTRL_SYSTEM_CPU_MODEL 3:0 238 #define NV0000_CTRL_SYSTEM_CPU_EXTENDED_MODEL 7:4 239 240 // Macros for AMD CPU information 241 #define NV0000_CTRL_SYSTEM_CPU_ID_AMD_FAMILY 0xF 242 #define NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_FAMILY 0xA 243 #define NV0000_CTRL_SYSTEM_CPU_ID_AMD_MODEL 0x0 244 #define NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_MODEL 0x4 245 246 // Macros for Intel CPU information 247 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_FAMILY 0x6 248 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_FAMILY 0x0 249 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_S_MODEL 0x7 250 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_P_MODEL 0xA 251 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_MODEL 0x9 252 253 /* processor type values */ 254 #define NV0000_CTRL_SYSTEM_CPU_TYPE_UNKNOWN (0x00000000U) 255 /* Intel types */ 256 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P5 (0x00000001U) 257 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P55 (0x00000002U) 258 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P6 (0x00000003U) 259 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P2 (0x00000004U) 260 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P2XC (0x00000005U) 261 #define NV0000_CTRL_SYSTEM_CPU_TYPE_CELA (0x00000006U) 262 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P3 (0x00000007U) 263 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P3_INTL2 (0x00000008U) 264 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P4 (0x00000009U) 265 #define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2 (0x00000010U) 266 #define NV0000_CTRL_SYSTEM_CPU_TYPE_CELN_M16H (0x00000011U) 267 #define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2_EXTRM (0x00000012U) 268 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM (0x00000013U) 269 #define NV0000_CTRL_SYSTEM_CPU_TYPE_XEON_SPR (0x00000014U) 270 /* AMD types */ 271 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K5 (0x00000030U) 272 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K6 (0x00000031U) 273 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K62 (0x00000032U) 274 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K63 (0x00000033U) 275 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K7 (0x00000034U) 276 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K8 (0x00000035U) 277 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K10 (0x00000036U) 278 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K11 (0x00000037U) 279 #define NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN (0x00000038U) 280 /* IDT/Centaur types */ 281 #define NV0000_CTRL_SYSTEM_CPU_TYPE_C6 (0x00000060U) 282 #define NV0000_CTRL_SYSTEM_CPU_TYPE_C62 (0x00000061U) 283 /* Cyrix types */ 284 #define NV0000_CTRL_SYSTEM_CPU_TYPE_GX (0x00000070U) 285 #define NV0000_CTRL_SYSTEM_CPU_TYPE_M1 (0x00000071U) 286 #define NV0000_CTRL_SYSTEM_CPU_TYPE_M2 (0x00000072U) 287 #define NV0000_CTRL_SYSTEM_CPU_TYPE_MGX (0x00000073U) 288 /* Transmeta types */ 289 #define NV0000_CTRL_SYSTEM_CPU_TYPE_TM_CRUSOE (0x00000080U) 290 /* IBM types */ 291 #define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC603 (0x00000090U) 292 #define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC604 (0x00000091U) 293 #define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC750 (0x00000092U) 294 #define NV0000_CTRL_SYSTEM_CPU_TYPE_POWERN (0x00000093U) 295 /* Unknown ARM architecture CPU type */ 296 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_UNKNOWN (0xA0000000U) 297 /* ARM Ltd types */ 298 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A9 (0xA0000009U) 299 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A15 (0xA000000FU) 300 /* NVIDIA types */ 301 #define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_1_0 (0xA0001000U) 302 #define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_2_0 (0xA0002000U) 303 304 /* Generic types */ 305 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC (0xA00FF000U) 306 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC (0xA00FF001U) 307 308 /* processor capabilities */ 309 #define NV0000_CTRL_SYSTEM_CPU_CAP_MMX (0x00000001U) 310 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE (0x00000002U) 311 #define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW (0x00000004U) 312 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 (0x00000008U) 313 #define NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE (0x00000010U) 314 #define NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING (0x00000020U) 315 #define NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC (0x00000040U) 316 #define NV0000_CTRL_SYSTEM_CPU_CAP_PUT_NEEDS_IO (0x00000080U) 317 #define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WC_WORKAROUND (0x00000100U) 318 #define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT (0x00000200U) 319 #define NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT (0x00000400U) 320 #define NV0000_CTRL_SYSTEM_CPU_CAP_CMOV (0x00000800U) 321 #define NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH (0x00001000U) 322 #define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_190854 (0x00002000U) /* deprecated */ 323 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 (0x00004000U) 324 #define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_124888 (0x00008000U) 325 #define NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE (0x00010000U) 326 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 (0x00020000U) 327 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 (0x00040000U) 328 #define NV0000_CTRL_SYSTEM_CPU_CAP_AVX (0x00080000U) 329 #define NV0000_CTRL_SYSTEM_CPU_CAP_ERMS (0x00100000U) 330 331 /* 332 * NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO 333 * 334 * This command returns system chipset information. 335 * 336 * vendorId 337 * This parameter returns the vendor identification for the chipset. 338 * A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the chipset 339 * cannot be identified. 340 * deviceId 341 * This parameter returns the device identification for the chipset. 342 * A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the chipset 343 * cannot be identified. 344 * subSysVendorId 345 * This parameter returns the subsystem vendor identification for the 346 * chipset. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the 347 * chipset cannot be identified. 348 * subSysDeviceId 349 * This parameter returns the subsystem device identification for the 350 * chipset. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the 351 * chipset cannot be identified. 352 * HBvendorId 353 * This parameter returns the vendor identification for the chipset's 354 * host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates 355 * the chipset's host bridge cannot be identified. 356 * HBdeviceId 357 * This parameter returns the device identification for the chipset's 358 * host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates 359 * the chipset's host bridge cannot be identified. 360 * HBsubSysVendorId 361 * This parameter returns the subsystem vendor identification for the 362 * chipset's host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID 363 * indicates the chipset's host bridge cannot be identified. 364 * HBsubSysDeviceId 365 * This parameter returns the subsystem device identification for the 366 * chipset's host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID 367 * indicates the chipset's host bridge cannot be identified. 368 * sliBondId 369 * This parameter returns the SLI bond identification for the chipset. 370 * vendorNameString 371 * This parameter returns the vendor name string. 372 * chipsetNameString 373 * This parameter returns the vendor name string. 374 * sliBondNameString 375 * This parameter returns the SLI bond name string. 376 * flag 377 * This parameter specifies NV0000_CTRL_SYSTEM_CHIPSET_FLAG_XXX flags: 378 * _HAS_RESIZABLE_BAR_ISSUE_YES: Chipset where the use of resizable BAR1 379 * should be disabled - bug 3440153 380 * 381 * Possible status values returned are: 382 * NV_OK 383 * NV_ERR_INVALID_PARAM_STRUCT 384 * NV_ERR_INVALID_ARGUMENT 385 * NV_ERR_OPERATING_SYSTEM 386 */ 387 #define NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO (0x104U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID" */ 388 389 /* maximum name string length */ 390 #define NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH (0x0000020U) 391 392 /* invalid id */ 393 #define NV0000_SYSTEM_CHIPSET_INVALID_ID (0xffffU) 394 395 #define NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID (0x4U) 396 397 typedef struct NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS { 398 NvU16 vendorId; 399 NvU16 deviceId; 400 NvU16 subSysVendorId; 401 NvU16 subSysDeviceId; 402 NvU16 HBvendorId; 403 NvU16 HBdeviceId; 404 NvU16 HBsubSysVendorId; 405 NvU16 HBsubSysDeviceId; 406 NvU32 sliBondId; 407 NvU8 vendorNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; 408 NvU8 subSysVendorNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; 409 NvU8 chipsetNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; 410 NvU8 sliBondNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; 411 NvU32 flags; 412 } NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS; 413 414 #define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE 0:0 415 #define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_NO (0x00000000U) 416 #define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_YES (0x00000001U) 417 418 419 420 /* 421 * NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT 422 * 423 * This command returns whether the VRR cookie is present in the SBIOS. 424 * 425 * bIsPresent (out) 426 * This parameter contains whether the VRR cookie is present in the SBIOS. 427 * 428 * Possible status values returned are: 429 * NV_OK 430 * NV_ERR_INVALID_REQUEST 431 * NV_ERR_NOT_SUPPORTED 432 */ 433 434 #define NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT (0x107U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS_MESSAGE_ID" */ 435 436 #define NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS_MESSAGE_ID (0x7U) 437 438 typedef struct NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS { 439 NvBool bIsPresent; 440 } NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS; 441 442 /* 443 * NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES 444 * 445 * This command is used to retrieve the measured times spent holding and waiting for 446 * the main RM locks (API and GPU). 447 * 448 * waitApiLock 449 * Total time spent by RM API's waiting to acquire the API lock 450 * 451 * holdRoApiLock 452 * Total time spent by RM API's holding the API lock in RO mode. 453 * 454 * holdRwApiLock 455 * Total time spent by RM API's holding the API lock in RW mode. 456 * 457 * waitGpuLock 458 * Total time spent by RM API's waiting to acquire one or more GPU locks. 459 * 460 * holdGpuLock 461 * Total time spent by RM API's holding one or more GPU locks. 462 * 463 * 464 * Possible status values returned are: 465 * NV_OK 466 * NV_ERR_NOT_SUPPORTED 467 */ 468 469 #define NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES (0x109U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID" */ 470 471 #define NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID (0x9U) 472 473 typedef struct NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS { 474 NV_DECLARE_ALIGNED(NvU64 waitApiLock, 8); 475 NV_DECLARE_ALIGNED(NvU64 holdRoApiLock, 8); 476 NV_DECLARE_ALIGNED(NvU64 holdRwApiLock, 8); 477 NV_DECLARE_ALIGNED(NvU64 waitGpuLock, 8); 478 NV_DECLARE_ALIGNED(NvU64 holdGpuLock, 8); 479 } NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS; 480 481 /* 482 * NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST 483 * 484 * This command is used to retrieve the set of system-level classes 485 * supported by the platform. 486 * 487 * numClasses 488 * This parameter returns the number of valid entries in the returned 489 * classes[] list. This parameter will not exceed 490 * Nv0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE. 491 * classes 492 * This parameter returns the list of supported classes 493 * 494 * Possible status values returned are: 495 * NV_OK 496 * NV_ERR_INVALID_PARAM_STRUCT 497 */ 498 499 #define NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST (0x108U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID" */ 500 501 /* maximum number of classes returned in classes[] array */ 502 #define NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE (32U) 503 504 #define NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID (0x8U) 505 506 typedef struct NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS { 507 NvU32 numClasses; 508 NvU32 classes[NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE]; 509 } NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS; 510 511 /* 512 * NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT 513 * 514 * This command is used to send triggered mobile related system events 515 * to the RM. 516 * 517 * eventType 518 * This parameter indicates the triggered event type. This parameter 519 * should specify a valid NV0000_CTRL_SYSTEM_EVENT_TYPE value. 520 * eventData 521 * This parameter specifies the type-dependent event data associated 522 * with EventType. This parameter should specify a valid 523 * NV0000_CTRL_SYSTEM_EVENT_DATA value. 524 * bEventDataForced 525 * This parameter specifies what we have to do, Whether trust current 526 * Lid/Dock state or not. This parameter should specify a valid 527 * NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED value. 528 529 * Possible status values returned are: 530 * NV_OK 531 * NV_ERR_INVALID_PARAM_STRUCT 532 * NV_ERR_INVALID_ARGUMENT 533 * 534 * Sync this up (#defines) with one in nvapi.spec! 535 * (NV_ACPI_EVENT_TYPE & NV_ACPI_EVENT_DATA) 536 */ 537 #define NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT (0x110U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID" */ 538 539 #define NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID (0x10U) 540 541 typedef struct NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS { 542 NvU32 eventType; 543 NvU32 eventData; 544 NvBool bEventDataForced; 545 } NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS; 546 547 /* valid eventType values */ 548 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_LID_STATE (0x00000000U) 549 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_POWER_SOURCE (0x00000001U) 550 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_DOCK_STATE (0x00000002U) 551 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_LID (0x00000003U) 552 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_DOCK (0x00000004U) 553 554 /* valid eventData values */ 555 #define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_OPEN (0x00000000U) 556 #define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_CLOSED (0x00000001U) 557 #define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_BATTERY (0x00000000U) 558 #define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_AC (0x00000001U) 559 #define NV0000_CTRL_SYSTEM_EVENT_DATA_UNDOCKED (0x00000000U) 560 #define NV0000_CTRL_SYSTEM_EVENT_DATA_DOCKED (0x00000001U) 561 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DSM (0x00000000U) 562 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DCS (0x00000001U) 563 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_NVIF (0x00000002U) 564 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_ACPI (0x00000003U) 565 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL (0x00000004U) 566 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_COUNT (0x5U) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL + 1)" */ 567 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DSM (0x00000000U) 568 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DCS (0x00000001U) 569 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_NVIF (0x00000002U) 570 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_ACPI (0x00000003U) 571 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL (0x00000004U) 572 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_COUNT (0x5U) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL + 1)" */ 573 574 /* valid bEventDataForced values */ 575 #define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_FALSE (0x00000000U) 576 #define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_TRUE (0x00000001U) 577 578 /* 579 * NV000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE 580 * 581 * This command is used to query the platform type. 582 * 583 * systemType 584 * This parameter returns the type of the system. 585 * Legal values for this parameter include: 586 * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP 587 * The system is a desktop platform. 588 * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC 589 * The system is a mobile (non-Toshiba) platform. 590 * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP 591 * The system is a mobile Toshiba platform. 592 * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC 593 * The system is a system-on-a-chip (SOC) platform. 594 * 595 596 * Possible status values returned are: 597 * NV_OK 598 * NV_ERR_INVALID_PARAM_STRUCT 599 * NV_ERR_INVALID_ARGUMENT 600 */ 601 #define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE (0x111U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID" */ 602 603 #define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID (0x11U) 604 605 typedef struct NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS { 606 NvU32 systemType; 607 } NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS; 608 609 /* valid systemType values */ 610 #define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP (0x000000U) 611 #define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC (0x000001U) 612 #define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_TOSHIBA (0x000002U) 613 #define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC (0x000003U) 614 615 616 617 618 /* 619 * NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL 620 * 621 * This command controls the current RmMsg filters. 622 * 623 * It is only supported if RmMsg is enabled (e.g. debug builds). 624 * 625 * cmd 626 * GET - Gets the current RmMsg filter string. 627 * SET - Sets the current RmMsg filter string. 628 * 629 * count 630 * The length of the RmMsg filter string. 631 * 632 * data 633 * The RmMsg filter string. 634 * 635 * Possible status values returned are: 636 * NV_OK 637 * NV_ERR_INVALID_ARGUMENT 638 * NV_ERR_NOT_SUPPORTED 639 */ 640 #define NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL (0x121U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID" */ 641 642 #define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE 512U 643 644 #define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_GET (0x00000000U) 645 #define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_SET (0x00000001U) 646 647 #define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID (0x21U) 648 649 typedef struct NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS { 650 NvU32 cmd; 651 NvU32 count; 652 NvU8 data[NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE]; 653 } NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS; 654 655 /* 656 * NV0000_CTRL_SYSTEM_HWBC_INFO 657 * 658 * This structure contains information about the HWBC (BR04) specified by 659 * hwbcId. 660 * 661 * hwbcId 662 * This field specifies the HWBC ID. 663 * firmwareVersion 664 * This field returns the version of the firmware on the HWBC (BR04), if 665 * present. This is a packed binary number of the form 0x12345678, which 666 * corresponds to a firmware version of 12.34.56.78. 667 * subordinateBus 668 * This field returns the subordinate bus number of the HWBC (BR04). 669 * secondaryBus 670 * This field returns the secondary bus number of the HWBC (BR04). 671 * 672 * Possible status values returned are: 673 * NV_OK 674 * NV_ERR_INVALID_ARGUMENT 675 */ 676 677 typedef struct NV0000_CTRL_SYSTEM_HWBC_INFO { 678 NvU32 hwbcId; 679 NvU32 firmwareVersion; 680 NvU32 subordinateBus; 681 NvU32 secondaryBus; 682 } NV0000_CTRL_SYSTEM_HWBC_INFO; 683 684 #define NV0000_CTRL_SYSTEM_HWBC_INVALID_ID (0xFFFFFFFFU) 685 686 /* 687 * NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO 688 * 689 * This command returns information about all Hardware Broadcast (HWBC) 690 * devices present in the system that are BR04s. To get the complete 691 * list of HWBCs in the system, all GPUs present in the system must be 692 * initialized. See the description of NV0000_CTRL_CMD_GPU_ATTACH_IDS to 693 * accomplish this. 694 * 695 * hwbcInfo 696 * This field is an array of NV0000_CTRL_SYSTEM_HWBC_INFO structures into 697 * which HWBC information is placed. There is one entry for each HWBC 698 * present in the system. Valid entries are contiguous, invalid entries 699 * have the hwbcId equal to NV0000_CTRL_SYSTEM_HWBC_INVALID_ID. If no HWBC 700 * is present in the system, all the entries would be marked invalid, but 701 * the return value would still be SUCCESS. 702 * 703 * Possible status values returned are: 704 * NV_OK 705 * NV_ERR_INVALID_ARGUMENT 706 */ 707 #define NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO (0x124U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID" */ 708 709 #define NV0000_CTRL_SYSTEM_MAX_HWBCS (0x00000080U) 710 711 #define NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID (0x24U) 712 713 typedef struct NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS { 714 NV0000_CTRL_SYSTEM_HWBC_INFO hwbcInfo[NV0000_CTRL_SYSTEM_MAX_HWBCS]; 715 } NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS; 716 717 /* 718 * NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL 719 * 720 * This command is used to control GPS functionality. It allows control of 721 * GPU Performance Scaling (GPS), changing its operational parameters and read 722 * most GPS dynamic parameters. 723 * 724 * command 725 * This parameter specifies the command to execute. Invalid commands 726 * result in the return of an NV_ERR_INVALID_ARGUMENT status. 727 * locale 728 * This parameter indicates the specific locale to which the command 729 * 'command' is to be applied. 730 * Supported range of CPU/GPU {i = 0, ..., 255} 731 * data 732 * This parameter contains a command-specific data payload. It can 733 * be used to input data as well as output data. 734 * 735 * Possible status values returned are: 736 * NV_OK 737 * NV_ERR_INVALID_COMMAND 738 * NV_ERR_INVALID_STATE 739 * NV_ERR_INVALID_DATA 740 * NV_ERR_INVALID_REQUEST 741 * NV_ERR_NOT_SUPPORTED 742 */ 743 #define NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL (0x122U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID" */ 744 745 #define NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID (0x22U) 746 747 typedef struct NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS { 748 NvU16 command; 749 NvU16 locale; 750 NvU32 data; 751 } NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS; 752 753 /* 754 * Valid command values : 755 * 756 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT 757 * Is used to check if GPS was correctly initialized. 758 * Possible return (OUT) values are: 759 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO 760 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES 761 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC 762 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC 763 * Are used to stop/start GPS functionality and to get current status. 764 * Possible IN/OUT values are: 765 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP 766 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START 767 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS 768 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS 769 * Are used to control execution of GPS actions and to get current status. 770 * Possible IN/OUT values are: 771 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF 772 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON 773 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC 774 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC 775 * Are used to switch current GPS logic and to retrieve current logic. 776 * Possible IN/OUT values are: 777 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF 778 * Will cause that all GPS actions will be NULL. 779 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY 780 * Fuzzy logic will determine GPS actions based on current ruleset. 781 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC 782 * Deterministic logic will define GPS actions based on current ruleset. 783 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE 784 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE 785 * Are used to set/retrieve system control preference. 786 * Possible IN/OUT values are: 787 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU 788 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU 789 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH 790 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT 791 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT 792 * Are used to set/retrieve GPU2CPU pstate limits. 793 * IN/OUT values are four bytes packed into a 32-bit data field. 794 * The CPU cap index for GPU pstate 0 is in the lowest byte, the CPU cap 795 * index for the GPU pstate 3 is in the highest byte, etc. One 796 * special value is to disable the override to the GPU2CPU map: 797 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE 798 * Is used to stop/start GPS PMU functionality. 799 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE 800 * Is used to get the current status of PMU GPS. 801 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE 802 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER 803 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER 804 * Are used to set/retrieve max power [mW] that system can provide. 805 * This is hardcoded GPS safety feature and logic/rules does not apply 806 * to this threshold. 807 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET 808 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET 809 * Are used to set/retrieve current system cooling budget [mW]. 810 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD 811 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD 812 * Are used to set/retrieve integration interval [sec]. 813 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET 814 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET 815 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT 816 * Are used to set/retrieve used ruleset [#]. Value is checked 817 * against MAX number of rules for currently used GPS logic. Also COUNT 818 * provides a way to find out how many rules exist for the current control 819 * system. 820 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST 821 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST 822 * Is used to set/get a delay relative to now during which to allow unbound 823 * CPU performance. Units are seconds. 824 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE 825 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE 826 * Is used to override/get the actual power supply mode (AC/Battery). 827 * Possible IN/OUT values are: 828 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL 829 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC 830 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT 831 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO 832 * Is used to get the Ventura system information for VCT tool 833 * Returned 32bit value should be treated as bitmask and decoded in 834 * following way: 835 * Encoding details are defined in objgps.h refer to 836 * NV_GPS_SYS_SUPPORT_INFO and corresponding bit defines. 837 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTION 838 * Is used to get the supported sub-functions defined in SBIOS. Returned 839 * value is a bitmask where each bit corresponds to different function: 840 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT 841 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS 842 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS 843 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC 844 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC 845 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB 846 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS 847 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER 848 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA 849 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE 850 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG 851 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL 852 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN 853 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE 854 * Are used to retrieve appropriate power measurements and their derivatives 855 * in [mW] for required locale. _BURDEN is defined only for _LOCALE_SYSTEM. 856 * _INTERMEDIATE is not defined for _LOCALE_SYSTEM, and takes an In value as 857 * index. 858 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS 859 * Is used to retrieve parameters when adjusting raw sensor power reading. 860 * The values may come from SBIOS, VBIOS, registry or driver default. 861 * Possible IN value is the index of interested parameter. 862 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP 863 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA 864 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE 865 * Are used to retrieve appropriate temperature measurements and their 866 * derivatives in [1/1000 Celsius]. 867 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE 868 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP 869 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN 870 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX 871 * Are used to retrieve CPU(x)/GPU(x) p-state or it's limits. 872 * Not applicable to _LOCALE_SYSTEM. 873 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION 874 * Is used to retrieve last GPS action for given domain. 875 * Not applicable to _LOCALE_SYSTEM. 876 * Possible return (OUT) values are: 877 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 878 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 879 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING 880 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT 881 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 882 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 883 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM 884 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM 885 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE 886 * Is used to set the power sensor simulator state. 887 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE 888 * Is used to get the power simulator sensor simulator state. 889 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA 890 * Is used to set power sensor simulator data 891 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA 892 * Is used to get power sensor simulator data 893 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK 894 * Is used to respond to the ACPI event triggered by SBIOS. RM will 895 * request value for budget and status, validate them, apply them 896 * and send ACK back to SBIOS. 897 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT 898 * Is a test cmd that should notify SBIOS to send ACPI event requesting 899 * budget and status change. 900 */ 901 #define NV0000_CTRL_CMD_SYSTEM_GPS_INVALID (0xFFFFU) 902 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT (0x0000U) 903 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC (0x0001U) 904 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC (0x0002U) 905 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS (0x0003U) 906 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS (0x0004U) 907 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC (0x0005U) 908 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC (0x0006U) 909 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE (0x0007U) 910 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE (0x0008U) 911 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT (0x0009U) 912 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT (0x000AU) 913 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE (0x000BU) 914 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE (0x000CU) 915 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER (0x0100U) 916 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER (0x0101U) 917 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET (0x0102U) 918 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET (0x0103U) 919 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD (0x0104U) 920 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD (0x0105U) 921 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET (0x0106U) 922 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET (0x0107U) 923 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT (0x0108U) 924 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST (0x0109U) 925 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST (0x010AU) 926 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE (0x010BU) 927 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE (0x010CU) 928 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO (0x010DU) 929 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTIONS (0x010EU) 930 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER (0x0200U) 931 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA (0x0201U) 932 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE (0x0202U) 933 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG (0x0203U) 934 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL (0x0204U) 935 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN (0x0205U) 936 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE (0x0206U) 937 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS (0x0210U) 938 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP (0x0220U) 939 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA (0x0221U) 940 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE (0x0222U) 941 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE (0x0240U) 942 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP (0x0241U) 943 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN (0x0242U) 944 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX (0x0243U) 945 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION (0x0244U) 946 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_SLFM_PRESENT (0x0245U) 947 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE (0x0250U) 948 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE (0x0251U) 949 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA (0x0252U) 950 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA (0x0253U) 951 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK (0x0320U) 952 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT (0x0321U) 953 954 /* valid LOCALE values */ 955 #define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_INVALID (0xFFFFU) 956 #define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_SYSTEM (0x0000U) 957 #define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_CPU(i) (0x0100+((i)%0x100)) 958 #define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_GPU(i) (0x0200+((i)%0x100)) 959 960 /* valid data values for enums */ 961 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID (0x80000000U) 962 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO (0x00000000U) 963 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES (0x00000001U) 964 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP (0x00000000U) 965 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START (0x00000001U) 966 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF (0x00000000U) 967 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON (0x00000001U) 968 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF (0x00000000U) 969 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY (0x00000001U) 970 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC (0x00000002U) 971 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU (0x00000000U) 972 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU (0x00000001U) 973 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH (0x00000002U) 974 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE (0xFFFFFFFFU) 975 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_OFF (0x00000000U) 976 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_ON (0x00000001U) 977 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL (0x00000000U) 978 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC (0x00000001U) 979 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT (0x00000002U) 980 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT (0x00000001U) 981 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS (0x00000002U) 982 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS (0x00000004U) 983 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC (0x00000008U) 984 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC (0x00000010U) 985 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB (0x00000020U) 986 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS (0x00000040U) 987 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 (0x00000000U) 988 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 (0x00000001U) 989 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING (0x00000002U) 990 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT (0x00000003U) 991 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 (0x00000004U) 992 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 (0x00000005U) 993 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM (0x00000006U) 994 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM (0x00000007U) 995 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_NO (0x00000000U) 996 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_YES (0x00000001U) 997 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_OFF (0x00000000U) 998 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_ON (0x00000001U) 999 1000 /* 1001 * NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL 1002 * 1003 * This command allows execution of multiple GpsControl commands within one 1004 * RmControl call. For practical reasons # of commands is limited to 16. 1005 * This command shares defines with NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL. 1006 * 1007 * cmdCount 1008 * Number of commands that should be executed. 1009 * Less or equal to NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX. 1010 * 1011 * succeeded 1012 * Number of commands that were succesully executed. 1013 * Less or equal to NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX. 1014 * Failing commands return NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID 1015 * in their data field. 1016 * 1017 * cmdData 1018 * Array of commands with following structure: 1019 * command 1020 * This parameter specifies the command to execute. 1021 * Invalid commands result in the return of an 1022 * NV_ERR_INVALID_ARGUMENT status. 1023 * locale 1024 * This parameter indicates the specific locale to which 1025 * the command 'command' is to be applied. 1026 * Supported range of CPU/GPU {i = 0, ..., 255} 1027 * data 1028 * This parameter contains a command-specific data payload. 1029 * It is used both to input data as well as to output data. 1030 * 1031 * Possible status values returned are: 1032 * NV_OK 1033 * NV_ERR_INVALID_REQUEST 1034 * NV_ERR_NOT_SUPPORTED 1035 */ 1036 #define NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL (0x123U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID" */ 1037 1038 #define NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX (16U) 1039 #define NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID (0x23U) 1040 1041 typedef struct NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS { 1042 NvU32 cmdCount; 1043 NvU32 succeeded; 1044 1045 struct { 1046 NvU16 command; 1047 NvU16 locale; 1048 NvU32 data; 1049 } cmdData[NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX]; 1050 } NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS; 1051 1052 1053 /* 1054 * Deprecated. Please use NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 instead. 1055 */ 1056 #define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS (0x127U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID" */ 1057 1058 /* 1059 * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED must remain equal to the square of 1060 * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS due to Check RM parsing issues. 1061 * NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS is the maximum size of GPU groups 1062 * allowed for batched P2P caps queries provided by the RM control 1063 * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX. 1064 */ 1065 #define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS 32U 1066 #define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED 1024U 1067 #define NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS 8U 1068 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER 0xffffffffU 1069 1070 /* P2P capabilities status index values */ 1071 #define NV0000_CTRL_P2P_CAPS_INDEX_READ 0U 1072 #define NV0000_CTRL_P2P_CAPS_INDEX_WRITE 1U 1073 #define NV0000_CTRL_P2P_CAPS_INDEX_NVLINK 2U 1074 #define NV0000_CTRL_P2P_CAPS_INDEX_ATOMICS 3U 1075 #define NV0000_CTRL_P2P_CAPS_INDEX_PROP 4U 1076 #define NV0000_CTRL_P2P_CAPS_INDEX_LOOPBACK 5U 1077 #define NV0000_CTRL_P2P_CAPS_INDEX_PCI 6U 1078 #define NV0000_CTRL_P2P_CAPS_INDEX_C2C 7U 1079 #define NV0000_CTRL_P2P_CAPS_INDEX_PCI_BAR1 8U 1080 1081 #define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE 9U 1082 1083 1084 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID (0x27U) 1085 1086 typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS { 1087 NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 1088 NvU32 gpuCount; 1089 NvU32 p2pCaps; 1090 NvU32 p2pOptimalReadCEs; 1091 NvU32 p2pOptimalWriteCEs; 1092 NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; 1093 NV_DECLARE_ALIGNED(NvP64 busPeerIds, 8); 1094 NV_DECLARE_ALIGNED(NvP64 busEgmPeerIds, 8); 1095 } NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS; 1096 1097 /* valid p2pCaps values */ 1098 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED 0:0 1099 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_FALSE (0x00000000U) 1100 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_TRUE (0x00000001U) 1101 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED 1:1 1102 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_FALSE (0x00000000U) 1103 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_TRUE (0x00000001U) 1104 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED 2:2 1105 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_FALSE (0x00000000U) 1106 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_TRUE (0x00000001U) 1107 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED 3:3 1108 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_FALSE (0x00000000U) 1109 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_TRUE (0x00000001U) 1110 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED 4:4 1111 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_FALSE (0x00000000U) 1112 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_TRUE (0x00000001U) 1113 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED 5:5 1114 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_FALSE (0x00000000U) 1115 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_TRUE (0x00000001U) 1116 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED 6:6 1117 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_FALSE (0x00000000U) 1118 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_TRUE (0x00000001U) 1119 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED 7:7 1120 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_FALSE (0x00000000U) 1121 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_TRUE (0x00000001U) 1122 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED 8:8 1123 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_FALSE (0x00000000U) 1124 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_TRUE (0x00000001U) 1125 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED 9:9 1126 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_FALSE (0x00000000U) 1127 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_TRUE (0x00000001U) 1128 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED 10:10 1129 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_FALSE (0x00000000U) 1130 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_TRUE (0x00000001U) 1131 1132 1133 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED 12:12 1134 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_FALSE (0x00000000U) 1135 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_TRUE (0x00000001U) 1136 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED 13:13 1137 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_FALSE (0x00000000U) 1138 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_TRUE (0x00000001U) 1139 1140 /* P2P status codes */ 1141 #define NV0000_P2P_CAPS_STATUS_OK (0x00U) 1142 #define NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED (0x01U) 1143 #define NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED (0x02U) 1144 #define NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED (0x03U) 1145 #define NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY (0x04U) 1146 #define NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED (0x05U) 1147 1148 /* 1149 * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 1150 * 1151 * This command returns peer to peer capabilities present between GPUs. 1152 * Valid requests must present a list of GPU Ids. 1153 * 1154 * [in] gpuIds 1155 * This member contains the array of GPU IDs for which we query the P2P 1156 * capabilities. Valid entries are contiguous, beginning with the first 1157 * entry in the list. 1158 * [in] gpuCount 1159 * This member contains the number of GPU IDs stored in the gpuIds[] array. 1160 * [out] p2pCaps 1161 * This member returns the peer to peer capabilities discovered between the 1162 * GPUs. Valid p2pCaps values include: 1163 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED 1164 * When this bit is set, peer to peer writes between subdevices owned 1165 * by this device are supported. 1166 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED 1167 * When this bit is set, peer to peer reads between subdevices owned 1168 * by this device are supported. 1169 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED 1170 * When this bit is set, peer to peer PROP between subdevices owned 1171 * by this device are supported. This is enabled by default 1172 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED 1173 * When this bit is set, PCI is supported for all P2P between subdevices 1174 * owned by this device. 1175 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED 1176 * When this bit is set, NVLINK is supported for all P2P between subdevices 1177 * owned by this device. 1178 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED 1179 * When this bit is set, peer to peer atomics between subdevices owned 1180 * by this device are supported. 1181 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED 1182 * When this bit is set, peer to peer loopback is supported for subdevices 1183 * owned by this device. 1184 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED 1185 * When this bit is set, indirect peer to peer writes between subdevices 1186 * owned by this device are supported. 1187 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED 1188 * When this bit is set, indirect peer to peer reads between subdevices 1189 * owned by this device are supported. 1190 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED 1191 * When this bit is set, indirect peer to peer atomics between 1192 * subdevices owned by this device are supported. 1193 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED 1194 * When this bit is set, indirect NVLINK is supported for subdevices 1195 * owned by this device. 1196 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED 1197 * When this bit is set, C2C P2P is supported between the GPUs 1198 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_BAR1_SUPPORTED 1199 * When this bit is set, BAR1 P2P is supported between the GPUs 1200 * mentioned in @ref gpuIds 1201 * [out] p2pOptimalReadCEs 1202 * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink 1203 * [out] p2pOptimalWriteCEs 1204 * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink 1205 * [out] p2pCapsStatus 1206 * This member returns status of all supported p2p capabilities. Valid 1207 * status values include: 1208 * NV0000_P2P_CAPS_STATUS_OK 1209 * P2P capability is supported. 1210 * NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED 1211 * Chipset doesn't support p2p capability. 1212 * NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED 1213 * GPU doesn't support p2p capability. 1214 * NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED 1215 * IOH topology isn't supported. For e.g. root ports are on different 1216 * IOH. 1217 * NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY 1218 * P2P Capability is disabled by a regkey. 1219 * NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED 1220 * P2P Capability is not supported. 1221 * NV0000_P2P_CAPS_STATUS_NVLINK_SETUP_FAILED 1222 * Indicates that NvLink P2P link setup failed. 1223 * [out] busPeerIds 1224 * Peer ID matrix. It is a one-dimentional array. 1225 * busPeerIds[X * gpuCount + Y] maps from index X to index Y in 1226 * the gpuIds[] table. For invalid or non-existent peer busPeerIds[] 1227 * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. 1228 * [out] busEgmPeerIds 1229 * EGM Peer ID matrix. It is a one-dimentional array. 1230 * busEgmPeerIds[X * gpuCount + Y] maps from index X to index Y in 1231 * the gpuIds[] table. For invalid or non-existent peer busEgmPeerIds[] 1232 * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. 1233 * 1234 * Possible status values returned are: 1235 * NV_OK 1236 * NV_ERR_INVALID_ARGUMENT 1237 * NV_ERR_INVALID_PARAM_STRUCT 1238 */ 1239 1240 1241 1242 #define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 (0x12bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID" */ 1243 1244 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID (0x2BU) 1245 1246 typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS { 1247 NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 1248 NvU32 gpuCount; 1249 NvU32 p2pCaps; 1250 NvU32 p2pOptimalReadCEs; 1251 NvU32 p2pOptimalWriteCEs; 1252 NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; 1253 NvU32 busPeerIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED]; 1254 NvU32 busEgmPeerIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED]; 1255 } NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS; 1256 1257 /* 1258 * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX 1259 * 1260 * This command returns peer to peer capabilities present between all pairs of 1261 * GPU IDs {(a, b) : a in gpuIdGrpA and b in gpuIdGrpB}. This can be used to 1262 * collect all P2P capabilities in the system - see the SRT: 1263 * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX_TEST 1264 * for a demonstration. 1265 * 1266 * The call will query for all pairs between set A and set B, and returns 1267 * results in both link directions. The results are two-dimensional arrays where 1268 * the first dimension is the index within the set-A array of one GPU ID under 1269 * consideration, and the second dimension is the index within the set-B array 1270 * of the other GPU ID under consideration. 1271 * 1272 * That is, the result arrays are *ALWAYS* to be indexed first with the set-A 1273 * index, then with the set-B index. The B-to-A direction of results are put in 1274 * the b2aOptimal(Read|Write)CEs. This makes it unnecessary to call the query 1275 * twice, since the usual use case requires both directions. 1276 * 1277 * If a set is being compared against itself (by setting grpBCount to 0), then 1278 * the result matrices are symmetric - it doesn't matter which index is first. 1279 * However, the choice of indices is effectively a choice of which ID is "B" and 1280 * which is "A" for the "a2b" and "b2a" directional results. 1281 * 1282 * [in] grpACount 1283 * This member contains the number of GPU IDs stored in the gpuIdGrpA[] 1284 * array. Must be >= 0. 1285 * [in] grpBCount 1286 * This member contains the number of GPU IDs stored in the gpuIdGrpB[] 1287 * array. Can be == 0 to specify a check of group A against itself. 1288 * [in] gpuIdGrpA 1289 * This member contains the array of GPU IDs in "group A", each of which 1290 * will have its P2P capabilities returned with respect to each GPU ID in 1291 * "group B". Valid entries are contiguous, beginning with the first entry 1292 * in the list. 1293 * [in] gpuIdGrpB 1294 * This member contains the array of GPU IDs in "group B", each of which 1295 * will have its P2P capabilities returned with respect to each GPU ID in 1296 * "group A". Valid entries are contiguous, beginning with the first entry 1297 * in the list. May be equal to gpuIdGrpA, but best performance requires 1298 * that the caller specifies grpBCount = 0 in this case, and ignores this. 1299 * [out] p2pCaps 1300 * This member returns the peer to peer capabilities discovered between the 1301 * pairs of input GPUs between the groups, indexed by [A_index][B_index]. 1302 * Valid p2pCaps values include: 1303 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED 1304 * When this bit is set, peer to peer writes between subdevices owned 1305 * by this device are supported. 1306 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED 1307 * When this bit is set, peer to peer reads between subdevices owned 1308 * by this device are supported. 1309 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED 1310 * When this bit is set, peer to peer PROP between subdevices owned 1311 * by this device are supported. This is enabled by default 1312 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED 1313 * When this bit is set, PCI is supported for all P2P between subdevices 1314 * owned by this device. 1315 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED 1316 * When this bit is set, NVLINK is supported for all P2P between subdevices 1317 * owned by this device. 1318 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED 1319 * When this bit is set, peer to peer atomics between subdevices owned 1320 * by this device are supported. 1321 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED 1322 * When this bit is set, peer to peer loopback is supported for subdevices 1323 * owned by this device. 1324 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED 1325 * When this bit is set, indirect peer to peer writes between subdevices 1326 * owned by this device are supported. 1327 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED 1328 * When this bit is set, indirect peer to peer reads between subdevices 1329 * owned by this device are supported. 1330 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED 1331 * When this bit is set, indirect peer to peer atomics between 1332 * subdevices owned by this device are supported. 1333 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED 1334 * When this bit is set, indirect NVLINK is supported for subdevices 1335 * owned by this device. 1336 * [out] a2bOptimalReadCes 1337 * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink 1338 * in the A-to-B direction. 1339 * [out] a2bOptimalWriteCes 1340 * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink 1341 * in the A-to-B direction. 1342 * [out] b2aOptimalReadCes 1343 * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink 1344 * in the B-to-A direction. 1345 * [out] b2aOptimalWriteCes 1346 * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink 1347 * in the B-to-A direction. 1348 * 1349 * Possible status values returned are: 1350 * NV_OK 1351 * NV_ERR_INVALID_ARGUMENT 1352 * NV_ERR_INVALID_PARAM_STRUCT 1353 */ 1354 1355 1356 1357 #define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX (0x13aU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID" */ 1358 1359 typedef NvU32 NV0000_CTRL_P2P_CAPS_MATRIX_ROW[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1360 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID (0x3AU) 1361 1362 typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS { 1363 NvU32 grpACount; 1364 NvU32 grpBCount; 1365 NvU32 gpuIdGrpA[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1366 NvU32 gpuIdGrpB[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1367 NV0000_CTRL_P2P_CAPS_MATRIX_ROW p2pCaps[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1368 NV0000_CTRL_P2P_CAPS_MATRIX_ROW a2bOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1369 NV0000_CTRL_P2P_CAPS_MATRIX_ROW a2bOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1370 NV0000_CTRL_P2P_CAPS_MATRIX_ROW b2aOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1371 NV0000_CTRL_P2P_CAPS_MATRIX_ROW b2aOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1372 } NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS; 1373 1374 /* 1375 * NV0000_CTRL_CMD_SYSTEM_GPS_CTRL 1376 * 1377 * This command is used to execute general GPS Functions, most dealing with 1378 * calling SBIOS, or retrieving cached sensor and GPS state data. 1379 * 1380 * version 1381 * This parameter specifies the version of the interface. Legal values 1382 * for this parameter are 1. 1383 * cmd 1384 * This parameter specifies the GPS API to be invoked. 1385 * Valid values for this parameter are: 1386 * NV0000_CTRL_GPS_CMD_GET_THERM_LIMIT 1387 * This command gets the temperature limit for thermal controller. When 1388 * this command is specified the input parameter contains ???. 1389 * NV0000_CTRL_GPS_CMD_SET_THERM_LIMIT 1390 * This command set the temperature limit for thermal controller. When 1391 * this command is specified the input parameter contains ???. 1392 * input 1393 * This parameter specifies the cmd-specific input value. 1394 * result 1395 * This parameter returns the cmd-specific output value. 1396 * 1397 * Possible status values returned are: 1398 * NV_OK 1399 * NV_ERR_INVALID_PARAM_STRUCT 1400 * NV_ERR_INVALID_ARGUMENT 1401 */ 1402 1403 #define NV0000_CTRL_CMD_SYSTEM_GPS_CTRL (0x12aU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID" */ 1404 1405 #define NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID (0x2AU) 1406 1407 typedef struct NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS { 1408 NvU32 cmd; 1409 NvS32 input[2]; 1410 NvS32 result[4]; 1411 } NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS; 1412 1413 /* valid version values */ 1414 #define NV0000_CTRL_GPS_PSHARE_PARAMS_PSP_CURRENT_VERSION (0x00010000U) 1415 1416 /* valid cmd values */ 1417 #define NV0000_CTRL_GPS_CMD_TYPE_GET_THERM_LIMIT (0x00000002U) 1418 #define NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000U) 1419 #define NV0000_CTRL_GPS_RESULT_THERMAL_LIMIT (0x00000000U) 1420 #define NV0000_CTRL_GPS_RESULT_MIN_LIMIT (0x00000001U) 1421 #define NV0000_CTRL_GPS_RESULT_MAX_LIMIT (0x00000002U) 1422 #define NV0000_CTRL_GPS_RESULT_LIMIT_SOURCE (0x00000003U) 1423 1424 #define NV0000_CTRL_GPS_CMD_TYPE_SET_THERM_LIMIT (0x00000003U) 1425 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1426 #define NV0000_CTRL_GPS_INPUT_THERMAL_LIMIT (0x00000001U) 1427 1428 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA (0x00000004U) 1429 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1430 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DOWN_N_DELTA (0x00000000U) 1431 1432 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA (0x00000005U) 1433 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1434 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DOWN_N_DELTA (0x00000001U) 1435 1436 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA (0x00000006U) 1437 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1438 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_HOLD_DELTA (0x00000000U) 1439 1440 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA (0x00000007U) 1441 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1442 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_HOLD_DELTA (0x00000001U) 1443 1444 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA (0x00000008U) 1445 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1446 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_UP_DELTA (0x00000000U) 1447 1448 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA (0x00000009U) 1449 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1450 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_UP_DELTA (0x00000001U) 1451 1452 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA (0x0000000AU) 1453 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1454 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_ENGAGE_DELTA (0x00000000U) 1455 1456 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA (0x0000000BU) 1457 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1458 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_ENGAGE_DELTA (0x00000001U) 1459 1460 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000CU) 1461 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1462 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) 1463 1464 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000DU) 1465 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1466 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) 1467 1468 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_STATUS (0x00000016U) 1469 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_STATUS (0x00000000U) 1470 1471 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_STATUS (0x00000017U) 1472 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_STATUS (0x00000000U) 1473 1474 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM (0x00000018U) 1475 #define NV0000_CTRL_GPS_RESULT_CPU_SET_UTIL_AVG_NUM (0x00000000U) 1476 1477 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM (0x00000019U) 1478 #define NV0000_CTRL_GPS_INPUT_CPU_GET_UTIL_AVG_NUM (0x00000000U) 1479 1480 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PERF_SENSOR (0x0000001AU) 1481 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1482 #define NV0000_CTRL_GPS_INPUT_NEXT_EXPECTED_POLL (0x00000001U) 1483 #define NV0000_CTRL_GPS_RESULT_PERF_SENSOR_VALUE (0x00000000U) 1484 #define NV0000_CTRL_GPS_RESULT_PERF_SENSOR_AVAILABLE (0x00000001U) 1485 1486 #define NV0000_CTRL_GPS_CMD_TYPE_CALL_ACPI (0x0000001BU) 1487 #define NV0000_CTRL_GPS_INPUT_ACPI_CMD (0x00000000U) 1488 #define NV0000_CTRL_GPS_INPUT_ACPI_PARAM_IN (0x00000001U) 1489 #define NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_1 (0x00000000U) 1490 #define NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_2 (0x00000001U) 1491 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_STATUS (0x00000000U) 1492 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_VERSION (0x00000001U) 1493 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_SZ (0x00000002U) 1494 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_SZ (0x00000000U) 1495 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_COUNT (0x00000001U) 1496 1497 #define NV0000_CTRL_GPS_CMD_TYPE_SET_IGPU_TURBO (0x0000001CU) 1498 #define NV0000_CTRL_GPS_INPUT_SET_IGPU_TURBO (0x00000000U) 1499 1500 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERIOD (0x00000026U) 1501 #define NV0000_CTRL_GPS_INPUT_TEMP_PERIOD (0x00000000U) 1502 1503 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERIOD (0x00000027U) 1504 #define NV0000_CTRL_GPS_RESULT_TEMP_PERIOD (0x00000000U) 1505 1506 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_NUDGE_FACTOR (0x00000028U) 1507 #define NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_UP (0x00000000U) 1508 #define NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_DOWN (0x00000001U) 1509 1510 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_NUDGE_FACTOR (0x00000029U) 1511 #define NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_UP (0x00000000U) 1512 #define NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_DOWN (0x00000001U) 1513 1514 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES (0x0000002AU) 1515 #define NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) 1516 #define NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) 1517 1518 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES (0x0000002BU) 1519 #define NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) 1520 #define NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) 1521 1522 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERF_LIMITS (0x0000002CU) 1523 #define NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_UPPER (0x00000000U) 1524 #define NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_LOWER (0x00000001U) 1525 1526 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERF_LIMITS (0x0000002DU) 1527 #define NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_UPPER (0x00000000U) 1528 #define NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_LOWER (0x00000001U) 1529 1530 #define NV0000_CTRL_GPS_CMD_TYPE_SET_PM1_AVAILABLE (0x0000002EU) 1531 #define NV0000_CTRL_GPS_INPUT_PM1_AVAILABLE (0x00000000U) 1532 1533 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PM1_AVAILABLE (0x0000002FU) 1534 #define NV0000_CTRL_GPS_OUTPUT_PM1_AVAILABLE (0x00000000U) 1535 1536 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS (0x00000044U) 1537 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) 1538 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 (0x00000001U) 1539 1540 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS (0x00000045U) 1541 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) 1542 1543 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT (0x00000046U) 1544 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ (0000000000U) 1545 1546 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT (0x00000047U) 1547 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ (0000000000U) 1548 1549 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM (0x00000048U) 1550 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_INDEX (0000000000U) 1551 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_AVAILABLE_MASK (0000000001U) 1552 1553 #define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM (0x00000049U) 1554 #define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX (0000000000U) 1555 #define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX_MAX (2U) 1556 1557 #define NV0000_CTRL_GPS_PPM_INDEX 7:0 1558 #define NV0000_CTRL_GPS_PPM_INDEX_MAXPERF (0U) 1559 #define NV0000_CTRL_GPS_PPM_INDEX_BALANCED (1U) 1560 #define NV0000_CTRL_GPS_PPM_INDEX_QUIET (2U) 1561 #define NV0000_CTRL_GPS_PPM_INDEX_INVALID (0xFFU) 1562 #define NV0000_CTRL_GPS_PPM_MASK 15:8 1563 #define NV0000_CTRL_GPS_PPM_MASK_INVALID (0U) 1564 1565 /* valid PS_STATUS result values */ 1566 #define NV0000_CTRL_GPS_CMD_PS_STATUS_OFF (0U) 1567 #define NV0000_CTRL_GPS_CMD_PS_STATUS_ON (1U) 1568 1569 1570 /* 1571 * NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS 1572 * 1573 * This command allows privileged users to update the values of 1574 * security settings governing RM behavior. 1575 * 1576 * Possible status values returned are: 1577 * NV_OK 1578 * NV_ERR_INVALID_ARGUMENT, 1579 * NV_ERR_INVALID_OBJECT_HANDLE 1580 * NV_ERR_NOT_SUPPORTED 1581 * NV_ERR_INSUFFICIENT_PERMISSIONS 1582 * 1583 * Please note: as implied above, administrator privileges are 1584 * required to modify security settings. 1585 */ 1586 #define NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS (0x129U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID" */ 1587 1588 #define GPS_MAX_COUNTERS_PER_BLOCK 32U 1589 #define NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID (0x29U) 1590 1591 typedef struct NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS { 1592 NvU32 objHndl; 1593 NvU32 blockId; 1594 NvU32 nextExpectedSampleTimems; 1595 NvU32 countersReq; 1596 NvU32 countersReturned; 1597 NvU32 counterBlock[GPS_MAX_COUNTERS_PER_BLOCK]; 1598 } NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS; 1599 1600 #define NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS (0x12cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID" */ 1601 1602 #define NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID (0x2CU) 1603 1604 typedef NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS; 1605 1606 #define NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS (0x12eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID" */ 1607 1608 #define NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID (0x2EU) 1609 1610 typedef NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS; 1611 1612 /* 1613 * NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI 1614 * 1615 * This command allows users to call GPS ACPI commands for testing purposes. 1616 * 1617 * cmd 1618 * This parameter specifies the GPS ACPI command to execute. 1619 * 1620 * input 1621 * This parameter specified the cmd-dependent input value. 1622 * 1623 * resultSz 1624 * This parameter returns the size (in bytes) of the valid data 1625 * returned in the result parameter. 1626 * 1627 * result 1628 * This parameter returns the results of the specified cmd. 1629 * The maximum size (in bytes) of this returned data will 1630 * not exceed GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 1631 * 1632 * GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 1633 * The size of buffer (result) in unit of NvU32. 1634 * The smallest value is sizeof(PSS_ENTRY)*ACPI_PSS_ENTRY_MAX. 1635 * Since the prior one is 24 bytes, and the later one is 48, 1636 * this value cannot be smaller than 288. 1637 * 1638 * Possible status values returned are: 1639 * NV_OK 1640 * NV_ERR_INVALID_ARGUMENT, 1641 * NV_ERR_INVALID_OBJECT_HANDLE 1642 * NV_ERR_NOT_SUPPORTED 1643 * NV_ERR_INSUFFICIENT_PERMISSIONS 1644 * 1645 */ 1646 #define GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U 1647 #define NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID (0x2DU) 1648 1649 typedef struct NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS { 1650 NvU32 cmd; 1651 NvU32 input; 1652 NvU32 resultSz; 1653 NvU32 result[GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE]; 1654 } NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS; 1655 1656 #define NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI (0x12dU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID" */ 1657 1658 /* 1659 * NV0000_CTRL_SYSTEM_PARAM_* 1660 * 1661 * The following is a list of system-level parameters (often sensors) that the 1662 * driver can be made aware of. They are primarily intended to be used by system 1663 * power-balancing algorithms that require system-wide visibility in order to 1664 * function. The names and values used here are established and specified in 1665 * several different NVIDIA documents that are made externally available. Thus, 1666 * updates to this list must be made with great caution. The only permissible 1667 * change is to append new parameters. Reordering is strictly prohibited. 1668 * 1669 * Brief Parameter Summary: 1670 * TGPU - GPU temperature (NvTemp) 1671 * PDTS - CPU package temperature (NvTemp) 1672 * SFAN - System fan speed (% of maximum fan speed) 1673 * SKNT - Skin temperature (NvTemp) 1674 * CPUE - CPU energy counter (NvU32) 1675 * TMP1 - Additional temperature sensor 1 (NvTemp) 1676 * TMP2 - Additional temperature sensor 2 (NvTemp) 1677 * CTGP - Mode 2 power limit offset (NvU32) 1678 * PPMD - Power mode data (NvU32) 1679 */ 1680 #define NV0000_CTRL_SYSTEM_PARAM_TGPU (0x00000000U) 1681 #define NV0000_CTRL_SYSTEM_PARAM_PDTS (0x00000001U) 1682 #define NV0000_CTRL_SYSTEM_PARAM_SFAN (0x00000002U) 1683 #define NV0000_CTRL_SYSTEM_PARAM_SKNT (0x00000003U) 1684 #define NV0000_CTRL_SYSTEM_PARAM_CPUE (0x00000004U) 1685 #define NV0000_CTRL_SYSTEM_PARAM_TMP1 (0x00000005U) 1686 #define NV0000_CTRL_SYSTEM_PARAM_TMP2 (0x00000006U) 1687 #define NV0000_CTRL_SYSTEM_PARAM_CTGP (0x00000007U) 1688 #define NV0000_CTRL_SYSTEM_PARAM_PPMD (0x00000008U) 1689 #define NV0000_CTRL_SYSTEM_PARAM_COUNT (0x00000009U) 1690 1691 /* 1692 * NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD 1693 * 1694 * This command is used to execute general ACPI methods. 1695 * 1696 * method 1697 * This parameter identifies the MXM ACPI API to be invoked. 1698 * Valid values for this parameter are: 1699 * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS 1700 * This value specifies that the DSM NVOP subfunction OPTIMUSCAPS 1701 * API is to be invoked. 1702 * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG 1703 * This value specifies that the DSM NVOP subfunction OPTIMUSFLAG 1704 * API is to be invoked. This API will set a Flag in sbios to Indicate 1705 * that HD Audio Controller is disable/Enabled from GPU Config space. 1706 * This flag will be used by sbios to restore Audio state after resuming 1707 * from s3/s4. 1708 * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS 1709 * This value specifies that the DSM JT subfunction FUNC_CAPS is to 1710 * to be invoked to get the SBIOS capabilities 1711 * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY 1712 * This value specifies that the DSM JT subfunction FUNC_PLATPOLICY is 1713 * to be invoked to set and get the various platform policies for JT. 1714 * Refer to the JT spec in more detail on various policies. 1715 * inData 1716 * This parameter specifies the method-specific input buffer. Data is 1717 * passed to the specified API using this buffer. 1718 * inDataSize 1719 * This parameter specifies the size of the inData buffer in bytes. 1720 * outStatus 1721 * This parameter returns the status code from the associated ACPI call. 1722 * outData 1723 * This parameter specifies the method-specific output buffer. Data 1724 * is returned by the specified API using this buffer. 1725 * outDataSize 1726 * This parameter specifies the size of the outData buffer in bytes. 1727 * 1728 * Possible status values returned are: 1729 * NV_OK 1730 * NV_ERR_INVALID_PARAM_STRUCT 1731 * NV_ERR_INVALID_ARGUMENT 1732 */ 1733 1734 #define NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD (0x130U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID" */ 1735 1736 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID (0x30U) 1737 1738 typedef struct NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS { 1739 NvU32 method; 1740 NV_DECLARE_ALIGNED(NvP64 inData, 8); 1741 NvU16 inDataSize; 1742 NvU32 outStatus; 1743 NV_DECLARE_ALIGNED(NvP64 outData, 8); 1744 NvU16 outDataSize; 1745 } NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS; 1746 1747 /* valid method parameter values */ 1748 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS (0x00000000U) 1749 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG (0x00000001U) 1750 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS (0x00000002U) 1751 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY (0x00000003U) 1752 /* 1753 * NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS 1754 * 1755 * This command can be used to instruct the RM to enable/disable specific module 1756 * of ETW events. 1757 * 1758 * moduleMask 1759 * This parameter specifies the module of events we would like to 1760 * enable/disable. 1761 * 1762 * Possible status values returned are: 1763 * NV_OK 1764 */ 1765 #define NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS (0x131U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID" */ 1766 1767 #define NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID (0x31U) 1768 1769 typedef struct NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS { 1770 NvU32 moduleMask; 1771 } NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS; 1772 1773 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ALL (0x00000001U) 1774 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NOFREQ (0x00000002U) 1775 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_FLUSH (0x00000004U) 1776 1777 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PERF (0x00000010U) 1778 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ELPG (0x00000020U) 1779 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVDPS (0x00000040U) 1780 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_POWER (0x00000080U) 1781 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_DISP (0x00000100U) 1782 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RMAPI (0x00000200U) 1783 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_INTR (0x00000400U) 1784 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_LOCK (0x00000800U) 1785 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RCJOURNAL (0x00001000U) 1786 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GENERIC (0x00002000U) 1787 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_THERM (0x00004000U) 1788 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GPS (0x00008000U) 1789 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PCIE (0x00010000U) 1790 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVTELEMETRY (0x00020000U) 1791 1792 /* 1793 * NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA 1794 * 1795 * This command is used to read FRL data based on need. 1796 * 1797 * nextSampleNumber 1798 * This parameter returns the counter of next sample which is being filled. 1799 * samples 1800 * This parameter returns the frame time, render time, target time, client ID 1801 * with one reserve bit for future use. 1802 * 1803 * Possible status values returned are: 1804 * NV_OK 1805 * NV_ERR_NOT_SUPPORTED 1806 */ 1807 1808 #define NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA (0x12fU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID" */ 1809 1810 #define NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE 64U 1811 1812 typedef struct NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE { 1813 NvU16 frameTime; 1814 NvU16 renderTime; 1815 NvU16 targetTime; 1816 NvU8 sleepTime; 1817 NvU8 sampleNumber; 1818 } NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE; 1819 1820 #define NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID (0x2FU) 1821 1822 typedef struct NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS { 1823 NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE samples[NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE]; 1824 NvU8 nextSampleNumber; 1825 } NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS; 1826 1827 /* 1828 * NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA 1829 * 1830 * This command is used to write FRM data based on need. 1831 * 1832 * frameTime 1833 * This parameter contains the frame time of current frame. 1834 * renderTime 1835 * This parameter contains the render time of current frame. 1836 * targetTime 1837 * This parameter contains the target time of current frame. 1838 * sleepTime 1839 * This parameter contains the sleep duration inserted by FRL for the latest frame. 1840 * 1841 * Possible status values returned are: 1842 * NV_OK 1843 * NV_ERR_NOT_SUPPORTED 1844 */ 1845 1846 #define NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA (0x132U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID" */ 1847 1848 #define NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID (0x32U) 1849 1850 typedef struct NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS { 1851 NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE sampleData; 1852 } NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS; 1853 1854 /* 1855 * NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO 1856 * 1857 * This command returns the current host driver, host OS and 1858 * plugin information. It is only valid when VGX is setup. 1859 * szHostDriverVersionBuffer 1860 * This field returns the host driver version (NV_VERSION_STRING). 1861 * szHostVersionBuffer 1862 * This field returns the host driver version (NV_BUILD_BRANCH_VERSION). 1863 * szHostTitleBuffer 1864 * This field returns the host driver title (NV_DISPLAY_DRIVER_TITLE). 1865 * szPluginTitleBuffer 1866 * This field returns the plugin build title (NV_DISPLAY_DRIVER_TITLE). 1867 * szHostUnameBuffer 1868 * This field returns the call of 'uname' on the host OS. 1869 * iHostChangelistNumber 1870 * This field returns the changelist value of the host driver (NV_BUILD_CHANGELIST_NUM). 1871 * iPluginChangelistNumber 1872 * This field returns the changelist value of the plugin (NV_BUILD_CHANGELIST_NUM). 1873 * 1874 * Possible status values returned are: 1875 * NV_OK 1876 * NV_ERR_INVALID_PARAM_STRUCT 1877 */ 1878 1879 #define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE 256U 1880 #define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO (0x133U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID" */ 1881 1882 #define NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID (0x33U) 1883 1884 typedef struct NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS { 1885 char szHostDriverVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1886 char szHostVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1887 char szHostTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1888 char szPluginTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1889 char szHostUnameBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1890 NvU32 iHostChangelistNumber; 1891 NvU32 iPluginChangelistNumber; 1892 } NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS; 1893 1894 /* 1895 * NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS 1896 * 1897 * This command returns the power status of the GPUs in the system, successfully attached or not because of 1898 * insufficient power. It is supported on Kepler and up only. 1899 * gpuCount 1900 * This field returns the count into the following arrays. 1901 * busNumber 1902 * This field returns the busNumber of a GPU. 1903 * gpuExternalPowerStatus 1904 * This field returns the corresponding external power status: 1905 * NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED 1906 * NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED 1907 * 1908 * Possible status values returned are: 1909 * NV_OK 1910 * NV_ERR_INVALID_PARAM_STRUCT 1911 * NV_ERR_NOT_SUPPORTED 1912 */ 1913 1914 #define NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS (0x134U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID" */ 1915 1916 #define NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID (0x34U) 1917 1918 typedef struct NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS { 1919 NvU8 gpuCount; 1920 NvU8 gpuBus[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 1921 NvU8 gpuExternalPowerStatus[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 1922 } NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS; 1923 1924 /* Valid gpuExternalPowerStatus values */ 1925 #define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED 0U 1926 #define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED 1U 1927 1928 /* 1929 * NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS 1930 * 1931 * This command returns the caller's API access privileges using 1932 * this client handle. 1933 * 1934 * privStatus 1935 * This parameter returns a mask of possible access privileges: 1936 * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_PRIV_USER_FLAG 1937 * The caller is running with elevated privileges 1938 * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_ROOT_HANDLE_FLAG 1939 * Client is of NV01_ROOT class. 1940 * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG 1941 * Client has PRIV bit set. 1942 * 1943 * Possible status values returned are: 1944 * NV_OK 1945 * NV_ERR_INVALID_PARAM_STRUCT 1946 */ 1947 1948 1949 #define NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS (0x135U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID" */ 1950 1951 #define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID (0x35U) 1952 1953 typedef struct NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS { 1954 NvU8 privStatusFlags; 1955 } NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS; 1956 1957 1958 /* Valid privStatus values */ 1959 #define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_USER_FLAG (0x00000001U) 1960 #define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_KERNEL_HANDLE_FLAG (0x00000002U) 1961 #define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG (0x00000004U) 1962 1963 /* 1964 * NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS 1965 * 1966 * The fabric manager (FM) notifies RM that fabric (system) is ready for peer to 1967 * peer (P2P) use or still initializing the fabric. This command allows clients 1968 * to query fabric status to allow P2P operations. 1969 * 1970 * Note, on systems where FM isn't used, RM just returns _SKIP. 1971 * 1972 * fabricStatus 1973 * This parameter returns current fabric status: 1974 * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP 1975 * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED 1976 * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS 1977 * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED 1978 * 1979 * Possible status values returned are: 1980 * NV_OK 1981 * NV_ERR_INVALID_ARGUMENT 1982 * NV_ERR_INVALID_OBJECT_HANDLE 1983 * NV_ERR_NOT_SUPPORTED 1984 * NV_ERR_INSUFFICIENT_PERMISSIONS 1985 * NV_ERR_INVALID_PARAM_STRUCT 1986 */ 1987 1988 typedef enum NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS { 1989 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP = 1, 1990 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED = 2, 1991 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS = 3, 1992 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED = 4, 1993 } NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS; 1994 1995 #define NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS (0x136U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID" */ 1996 1997 #define NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID (0x36U) 1998 1999 typedef struct NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS { 2000 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS fabricStatus; 2001 } NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS; 2002 2003 /* 2004 * NV0000_CTRL_VGPU_GET_VGPU_VERSION_INFO 2005 * 2006 * This command is used to query the range of VGX version supported. 2007 * 2008 * host_min_supported_version 2009 * The minimum vGPU version supported by host driver 2010 * host_max_supported_version 2011 * The maximum vGPU version supported by host driver 2012 * user_min_supported_version 2013 * The minimum vGPU version set by user for vGPU support 2014 * user_max_supported_version 2015 * The maximum vGPU version set by user for vGPU support 2016 * 2017 * Possible status values returned are: 2018 * NV_OK 2019 * NV_ERR_INVALID_REQUEST 2020 */ 2021 #define NV0000_CTRL_VGPU_GET_VGPU_VERSION (0x137U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID" */ 2022 2023 /* 2024 * NV0000_CTRL_VGPU_GET_VGPU_VERSION 2025 */ 2026 #define NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID (0x37U) 2027 2028 typedef struct NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS { 2029 NvU32 host_min_supported_version; 2030 NvU32 host_max_supported_version; 2031 NvU32 user_min_supported_version; 2032 NvU32 user_max_supported_version; 2033 } NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS; 2034 2035 /* 2036 * NV0000_CTRL_VGPU_SET_VGPU_VERSION 2037 * 2038 * This command is used to query whether pGPU is live migration capable or not. 2039 * 2040 * min_version 2041 * The minimum vGPU version to be supported being set 2042 * max_version 2043 * The maximum vGPU version to be supported being set 2044 * 2045 * Possible status values returned are: 2046 * NV_OK 2047 * NV_ERR_INVALID_REQUEST 2048 */ 2049 #define NV0000_CTRL_VGPU_SET_VGPU_VERSION (0x138U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID" */ 2050 2051 /* 2052 * NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS 2053 */ 2054 #define NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID (0x38U) 2055 2056 typedef struct NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS { 2057 NvU32 min_version; 2058 NvU32 max_version; 2059 } NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS; 2060 2061 /* 2062 * NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID 2063 * 2064 * This command is used to get a unique identifier for the instance of RM. 2065 * The returned value will only change when the driver is reloaded. A previous 2066 * value will never be reused on a given machine. 2067 * 2068 * rm_instance_id; 2069 * The instance ID of the current RM instance 2070 * 2071 * Possible status values returned are: 2072 * NV_OK 2073 */ 2074 #define NV0000_CTRL_CMD_SYSTEM_GET_RM_INSTANCE_ID (0x139U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID" */ 2075 2076 /* 2077 * NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS 2078 */ 2079 #define NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID (0x39U) 2080 2081 typedef struct NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS { 2082 NV_DECLARE_ALIGNED(NvU64 rm_instance_id, 8); 2083 } NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS; 2084 2085 /* 2086 * NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO 2087 * 2088 * This API is used to get the TPP(total processing power) and 2089 * the rated TGP(total GPU power) from SBIOS. 2090 * 2091 * NVPCF is an acronym for Nvidia Platform Controllers and Framework 2092 * which implements platform level policies. NVPCF is implemented in 2093 * a kernel driver on windows. It is implemented in a user mode app 2094 * called nvidia-powerd on Linux. 2095 * 2096 * Valid subFunc ids for NVPCF 1x include : 2097 * NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED 2098 * NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS 2099 * 2100 * Valid subFunc ids for NVPCF 2x include : 2101 * NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED 2102 * NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS 2103 * NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES 2104 * 2105 * Possible status values returned are: 2106 * NV_OK 2107 * NV_ERR_INVALID_REQUEST 2108 * NV_ERR_NOT_SUPPORTED 2109 */ 2110 #define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO (0x13bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID" */ 2111 2112 #define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID (0x3BU) 2113 2114 typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS { 2115 /* GPU ID */ 2116 NvU32 gpuId; 2117 2118 /* Total processing power including CPU and GPU */ 2119 NvU32 tpp; 2120 2121 /* Rated total GPU Power */ 2122 NvU32 ratedTgp; 2123 2124 /* NVPCF subfunction id */ 2125 NvU32 subFunc; 2126 2127 /* Configurable TGP offset, in mW */ 2128 NvS32 ctgpOffsetmW; 2129 2130 /* TPP, as offset in mW */ 2131 NvS32 targetTppOffsetmW; 2132 2133 /* Maximum allowed output, as offset in mW */ 2134 NvS32 maxOutputOffsetmW; 2135 2136 /* Minimum allowed output, as offset in mW */ 2137 NvS32 minOutputOffsetmW; 2138 2139 /* Configurable TGP offset, on battery, in milli-Watts. */ 2140 NvS32 ctgpBattOffsetmW; 2141 2142 /* Target total processing power on battery, offset, in milli-Watts. */ 2143 NvS32 targetTppBattOffsetmW; 2144 2145 /* 2146 * If value specified is larger than the statically assigned ROS reserve in 2147 * the system power limits table, this will take affect. 2148 * 2149 * A value of zero naturally works as a clear as it will be lesser than the 2150 * statically assigned value. 2151 */ 2152 NvU32 dcRosReserveOverridemW; 2153 2154 /* 2155 * This is the active arbitrated long timescale limit provided by Qboost and 2156 * honored by JPAC/JPPC 2157 */ 2158 NvU32 dcTspLongTimescaleLimitmA; 2159 2160 /* 2161 * This is the active arbitrated short timescale limit provided by Qboost and 2162 * honored by RM/PMU 2163 */ 2164 NvU32 dcTspShortTimescaleLimitmA; 2165 2166 /* Require DB on DC to use system power limits table */ 2167 NvBool bRequireDcSysPowerLimitsTable; 2168 2169 /* Dynamic params can override ROS reserve used in DB-DC */ 2170 NvBool bAllowDcRestOfSystemReserveOverride; 2171 2172 /* Is DC-TSP supported? */ 2173 NvBool bSupportDcTsp; 2174 2175 /* Dynamic Boost AC support */ 2176 NvBool bEnableForAC; 2177 2178 /* Dynamic Boost DC support */ 2179 NvBool bEnableForDC; 2180 2181 /* The System Controller Table Version */ 2182 NvU8 version; 2183 2184 /* Base sampling period */ 2185 NvU16 samplingPeriodmS; 2186 2187 /* Sampling Multiplier */ 2188 NvU16 samplingMulti; 2189 2190 /* Fitler function type */ 2191 NvU8 filterType; 2192 2193 union { 2194 2195 /* weight */ 2196 NvU8 weight; 2197 2198 /* windowSize */ 2199 NvU8 windowSize; 2200 } filterParam; 2201 2202 /* Reserved */ 2203 NvU16 filterReserved; 2204 2205 /* Controller Type Dynamic Boost Controller */ 2206 NvBool bIsBoostController; 2207 2208 /* Increase power limit ratio */ 2209 NvU16 incRatio; 2210 2211 /* Decrease power limit ratio */ 2212 NvU16 decRatio; 2213 2214 /* Dynamic Boost Controller DC Support */ 2215 NvBool bSupportBatt; 2216 2217 /* CPU type(Intel/AMD) */ 2218 NvU8 cpuType; 2219 2220 /* GPU type(Nvidia) */ 2221 NvU8 gpuType; 2222 } NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS; 2223 2224 /* Define the filter types */ 2225 #define CONTROLLER_FILTER_TYPE_EMWA 0U 2226 #define CONTROLLER_FILTER_TYPE_MOVING_MAX 1U 2227 2228 /* Valid NVPCF subfunction case */ 2229 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE 2U 2230 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE 3U 2231 2232 /* NVPCF subfunction to get the static data tables */ 2233 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CASE 4U 2234 2235 /* Valid NVPCF subfunction ids */ 2236 #define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED (0x00000000) 2237 #define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS (0x00000002) 2238 2239 /* 2240 * Defines for get supported sub functions bit fields 2241 */ 2242 #define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED 0:0 2243 #define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES 1 2244 #define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO 0 2245 2246 /*! 2247 * Config DSM 2x version specific defines 2248 */ 2249 #define NVPCF0100_CTRL_CONFIG_DSM_2X_VERSION (0x00000200) 2250 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED (0x00000000) 2251 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES (0x00000001) 2252 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS (0x00000002) 2253 2254 /*! 2255 * Defines the max buffer size for config 2256 */ 2257 #define NVPCF0100_CTRL_CONFIG_2X_BUFF_SIZE_MAX (255) 2258 2259 /* 2260 * NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT 2261 * 2262 * This API is used to sync the external fabric management status with 2263 * GSP-RM 2264 * 2265 * bExternalFabricMgmt 2266 * Whether fabric is externally managed 2267 * 2268 * Possible status values returned are: 2269 * NV_OK 2270 */ 2271 #define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT (0x13cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID" */ 2272 2273 #define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID (0x3CU) 2274 2275 typedef struct NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS { 2276 NvBool bExternalFabricMgmt; 2277 } NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS; 2278 2279 /* 2280 * NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO 2281 * 2282 * This API is used to get information about the RM client 2283 * database. 2284 * 2285 * clientCount [OUT] 2286 * This field indicates the number of clients currently allocated. 2287 * 2288 * resourceCount [OUT] 2289 * This field indicates the number of resources currently allocated 2290 * across all clients. 2291 * 2292 */ 2293 #define NV0000_CTRL_CMD_SYSTEM_GET_CLIENT_DATABASE_INFO (0x13dU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID" */ 2294 2295 #define NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID (0x3DU) 2296 2297 typedef struct NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS { 2298 NvU32 clientCount; 2299 NV_DECLARE_ALIGNED(NvU64 resourceCount, 8); 2300 } NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS; 2301 2302 /* 2303 * NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 2304 * 2305 * This command returns the current driver information in 2306 * statically sized character arrays. 2307 * 2308 * driverVersionBuffer 2309 * This field returns the version (NV_VERSION_STRING). 2310 * versionBuffer 2311 * This field returns the version (NV_BUILD_BRANCH_VERSION). 2312 * driverBranch 2313 * This field returns the branch (NV_BUILD_BRANCH). 2314 * titleBuffer 2315 * This field returns the title (NV_DISPLAY_DRIVER_TITLE). 2316 * changelistNumber 2317 * This field returns the changelist value (NV_BUILD_CHANGELIST_NUM). 2318 * officialChangelistNumber 2319 * This field returns the last official changelist value 2320 * (NV_LAST_OFFICIAL_CHANGELIST_NUM). 2321 * 2322 * Possible status values returned are: 2323 * NV_OK 2324 */ 2325 2326 #define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE 256U 2327 #define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 (0x13eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID" */ 2328 2329 #define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID (0x3EU) 2330 2331 typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS { 2332 char driverVersionBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; 2333 char versionBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; 2334 char driverBranch[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; 2335 char titleBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; 2336 NvU32 changelistNumber; 2337 NvU32 officialChangelistNumber; 2338 } NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS; 2339 2340 /* 2341 * NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL 2342 * 2343 * This API is used to get/set RMCTRL cache mode 2344 * 2345 * cmd [IN] 2346 * GET - Gets RMCTRL cache mode 2347 * SET - Sets RMCTRL cache mode 2348 * 2349 * mode [IN/OUT] 2350 * On GET, this field is the output of current RMCTRL cache mode 2351 * On SET, this field indicates the mode to set RMCTRL cache to 2352 * Valid values for this parameter are: 2353 * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE 2354 * No get/set action to cache. 2355 * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE 2356 * Try to get from cache at the beginning of the control. 2357 * Set cache after control finished if the control has not been cached. 2358 * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY 2359 * Do not get from cache. Set cache when control call finished. 2360 * When setting the cache, verify the value in the cache is the same 2361 * with the current control value if the control is already cached. 2362 * 2363 * Possible status values returned are: 2364 * NV_OK 2365 * NV_ERR_INVALID_ARGUMENT 2366 */ 2367 #define NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL (0x13fU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID" */ 2368 2369 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID (0x3FU) 2370 2371 typedef struct NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS { 2372 NvU32 cmd; 2373 NvU32 mode; 2374 } NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS; 2375 2376 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_GET (0x00000000U) 2377 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_SET (0x00000001U) 2378 2379 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE (0x00000000U) 2380 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE (0x00000001U) 2381 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY (0x00000002U) 2382 2383 /* 2384 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL 2385 * 2386 * This command is used to control PFM_REQ_HNDLR functionality. It allows control of 2387 * GPU Performance Scaling (PFM_REQ_HNDLR), changing its operational parameters and read 2388 * most PFM_REQ_HNDLR dynamic parameters. 2389 * 2390 * command 2391 * This parameter specifies the command to execute. Invalid commands 2392 * result in the return of an NV_ERR_INVALID_ARGUMENT status. 2393 * locale 2394 * This parameter indicates the specific locale to which the command 2395 * 'command' is to be applied. 2396 * Supported range of CPU/GPU {i = 0, ..., 255} 2397 * data 2398 * This parameter contains a command-specific data payload. It can 2399 * be used to input data as well as output data. 2400 * 2401 * Possible status values returned are: 2402 * NV_OK 2403 * NV_ERR_INVALID_COMMAND 2404 * NV_ERR_INVALID_STATE 2405 * NV_ERR_INVALID_DATA 2406 * NV_ERR_INVALID_REQUEST 2407 * NV_ERR_NOT_SUPPORTED 2408 */ 2409 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL (0x140U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID" */ 2410 2411 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID (0x40U) 2412 2413 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS { 2414 NvU16 command; 2415 NvU16 locale; 2416 NvU32 data; 2417 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS; 2418 2419 /* 2420 * Valid command values : 2421 * 2422 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT 2423 * Is used to check if PFM_REQ_HNDLR was correctly initialized. 2424 * Possible return (OUT) values are: 2425 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO 2426 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES 2427 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC 2428 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC 2429 * Are used to stop/start PFM_REQ_HNDLR functionality and to get current status. 2430 * Possible IN/OUT values are: 2431 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP 2432 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START 2433 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS 2434 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS 2435 * Are used to control execution of PFM_REQ_HNDLR actions and to get current status. 2436 * Possible IN/OUT values are: 2437 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF 2438 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON 2439 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC 2440 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC 2441 * Are used to switch current PFM_REQ_HNDLR logic and to retrieve current logic. 2442 * Possible IN/OUT values are: 2443 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF 2444 * Will cause that all PFM_REQ_HNDLR actions will be NULL. 2445 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY 2446 * Fuzzy logic will determine PFM_REQ_HNDLR actions based on current ruleset. 2447 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC 2448 * Deterministic logic will define PFM_REQ_HNDLR actions based on current ruleset. 2449 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE 2450 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE 2451 * Are used to set/retrieve system control preference. 2452 * Possible IN/OUT values are: 2453 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU 2454 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU 2455 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH 2456 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT 2457 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT 2458 * Are used to set/retrieve GPU2CPU pstate limits. 2459 * IN/OUT values are four bytes packed into a 32-bit data field. 2460 * The CPU cap index for GPU pstate 0 is in the lowest byte, the CPU cap 2461 * index for the GPU pstate 3 is in the highest byte, etc. One 2462 * special value is to disable the override to the GPU2CPU map: 2463 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE 2464 * Is used to stop/start PFM_REQ_HNDLR PMU functionality. 2465 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE 2466 * Is used to get the current status of PMU PFM_REQ_HNDLR. 2467 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE 2468 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER 2469 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER 2470 * Are used to set/retrieve max power [mW] that system can provide. 2471 * This is hardcoded PFM_REQ_HNDLR safety feature and logic/rules does not apply 2472 * to this threshold. 2473 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET 2474 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET 2475 * Are used to set/retrieve current system cooling budget [mW]. 2476 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD 2477 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD 2478 * Are used to set/retrieve integration interval [sec]. 2479 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET 2480 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET 2481 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT 2482 * Are used to set/retrieve used ruleset [#]. Value is checked 2483 * against MAX number of rules for currently used PFM_REQ_HNDLR logic. Also COUNT 2484 * provides a way to find out how many rules exist for the current control 2485 * system. 2486 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST 2487 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST 2488 * Is used to set/get a delay relative to now during which to allow unbound 2489 * CPU performance. Units are seconds. 2490 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE 2491 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE 2492 * Is used to override/get the actual power supply mode (AC/Battery). 2493 * Possible IN/OUT values are: 2494 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL 2495 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC 2496 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT 2497 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO 2498 * Is used to get the Ventura system information for VCT tool 2499 * Returned 32bit value should be treated as bitmask and decoded in 2500 * following way: 2501 * Encoding details are defined in objPFM_REQ_HNDLR.h refer to 2502 * NV_PFM_REQ_HNDLR_SYS_SUPPORT_INFO and corresponding bit defines. 2503 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTION 2504 * Is used to get the supported sub-functions defined in SBIOS. Returned 2505 * value is a bitmask where each bit corresponds to different function: 2506 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT 2507 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS 2508 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS 2509 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC 2510 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC 2511 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB 2512 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS 2513 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER 2514 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA 2515 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE 2516 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG 2517 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL 2518 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN 2519 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE 2520 * Are used to retrieve appropriate power measurements and their derivatives 2521 * in [mW] for required locale. _BURDEN is defined only for _LOCALE_SYSTEM. 2522 * _INTERMEDIATE is not defined for _LOCALE_SYSTEM, and takes an In value as 2523 * index. 2524 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS 2525 * Is used to retrieve parameters when adjusting raw sensor power reading. 2526 * The values may come from SBIOS, VBIOS, registry or driver default. 2527 * Possible IN value is the index of interested parameter. 2528 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP 2529 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA 2530 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE 2531 * Are used to retrieve appropriate temperature measurements and their 2532 * derivatives in [1/1000 Celsius]. 2533 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE 2534 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP 2535 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN 2536 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX 2537 * Are used to retrieve CPU(x)/GPU(x) p-state or it's limits. 2538 * Not applicable to _LOCALE_SYSTEM. 2539 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION 2540 * Is used to retrieve last PFM_REQ_HNDLR action for given domain. 2541 * Not applicable to _LOCALE_SYSTEM. 2542 * Possible return (OUT) values are: 2543 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 2544 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 2545 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING 2546 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT 2547 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 2548 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 2549 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM 2550 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM 2551 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE 2552 * Is used to set the power sensor simulator state. 2553 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE 2554 * Is used to get the power simulator sensor simulator state. 2555 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA 2556 * Is used to set power sensor simulator data 2557 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA 2558 * Is used to get power sensor simulator data 2559 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK 2560 * Is used to respond to the ACPI event triggered by SBIOS. RM will 2561 * request value for budget and status, validate them, apply them 2562 * and send ACK back to SBIOS. 2563 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT 2564 * Is a test cmd that should notify SBIOS to send ACPI event requesting 2565 * budget and status change. 2566 */ 2567 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_INVALID (0xFFFFU) 2568 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT (0x0000U) 2569 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC (0x0001U) 2570 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC (0x0002U) 2571 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS (0x0003U) 2572 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS (0x0004U) 2573 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC (0x0005U) 2574 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC (0x0006U) 2575 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE (0x0007U) 2576 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE (0x0008U) 2577 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT (0x0009U) 2578 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT (0x000AU) 2579 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE (0x000BU) 2580 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE (0x000CU) 2581 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER (0x0100U) 2582 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER (0x0101U) 2583 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET (0x0102U) 2584 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET (0x0103U) 2585 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD (0x0104U) 2586 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD (0x0105U) 2587 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET (0x0106U) 2588 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET (0x0107U) 2589 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT (0x0108U) 2590 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST (0x0109U) 2591 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST (0x010AU) 2592 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE (0x010BU) 2593 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE (0x010CU) 2594 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO (0x010DU) 2595 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTIONS (0x010EU) 2596 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER (0x0200U) 2597 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA (0x0201U) 2598 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE (0x0202U) 2599 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG (0x0203U) 2600 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL (0x0204U) 2601 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN (0x0205U) 2602 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE (0x0206U) 2603 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS (0x0210U) 2604 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP (0x0220U) 2605 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA (0x0221U) 2606 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE (0x0222U) 2607 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE (0x0240U) 2608 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP (0x0241U) 2609 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN (0x0242U) 2610 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX (0x0243U) 2611 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION (0x0244U) 2612 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_SLFM_PRESENT (0x0245U) 2613 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE (0x0250U) 2614 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE (0x0251U) 2615 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA (0x0252U) 2616 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA (0x0253U) 2617 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK (0x0320U) 2618 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT (0x0321U) 2619 2620 /* valid LOCALE values */ 2621 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_INVALID (0xFFFFU) 2622 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_SYSTEM (0x0000U) 2623 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_CPU(i) (0x0100+((i)%0x100)) 2624 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_GPU(i) (0x0200+((i)%0x100)) 2625 2626 /* valid data values for enums */ 2627 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID (0x80000000U) 2628 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO (0x00000000U) 2629 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES (0x00000001U) 2630 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP (0x00000000U) 2631 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START (0x00000001U) 2632 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF (0x00000000U) 2633 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON (0x00000001U) 2634 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF (0x00000000U) 2635 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY (0x00000001U) 2636 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC (0x00000002U) 2637 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU (0x00000000U) 2638 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU (0x00000001U) 2639 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH (0x00000002U) 2640 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE (0xFFFFFFFFU) 2641 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_OFF (0x00000000U) 2642 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_ON (0x00000001U) 2643 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL (0x00000000U) 2644 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC (0x00000001U) 2645 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT (0x00000002U) 2646 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT (0x00000001U) 2647 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS (0x00000002U) 2648 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS (0x00000004U) 2649 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC (0x00000008U) 2650 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC (0x00000010U) 2651 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB (0x00000020U) 2652 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS (0x00000040U) 2653 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 (0x00000000U) 2654 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 (0x00000001U) 2655 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING (0x00000002U) 2656 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT (0x00000003U) 2657 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 (0x00000004U) 2658 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 (0x00000005U) 2659 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM (0x00000006U) 2660 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM (0x00000007U) 2661 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_NO (0x00000000U) 2662 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_YES (0x00000001U) 2663 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_OFF (0x00000000U) 2664 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_ON (0x00000001U) 2665 2666 /* 2667 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL 2668 * 2669 * This command allows execution of multiple PFM_REQ_HNDLRControl commands within one 2670 * RmControl call. For practical reasons # of commands is limited to 16. 2671 * This command shares defines with NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL. 2672 * 2673 * cmdCount 2674 * Number of commands that should be executed. 2675 * Less or equal to NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX. 2676 * 2677 * succeeded 2678 * Number of commands that were succesully executed. 2679 * Less or equal to NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX. 2680 * Failing commands return NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID 2681 * in their data field. 2682 * 2683 * cmdData 2684 * Array of commands with following structure: 2685 * command 2686 * This parameter specifies the command to execute. 2687 * Invalid commands result in the return of an 2688 * NV_ERR_INVALID_ARGUMENT status. 2689 * locale 2690 * This parameter indicates the specific locale to which 2691 * the command 'command' is to be applied. 2692 * Supported range of CPU/GPU {i = 0, ..., 255} 2693 * data 2694 * This parameter contains a command-specific data payload. 2695 * It is used both to input data as well as to output data. 2696 * 2697 * Possible status values returned are: 2698 * NV_OK 2699 * NV_ERR_INVALID_REQUEST 2700 * NV_ERR_NOT_SUPPORTED 2701 */ 2702 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL (0x141U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID" */ 2703 2704 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX (16U) 2705 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID (0x41U) 2706 2707 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS { 2708 NvU32 cmdCount; 2709 NvU32 succeeded; 2710 2711 struct { 2712 NvU16 command; 2713 NvU16 locale; 2714 NvU32 data; 2715 } cmdData[NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX]; 2716 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS; 2717 2718 /* 2719 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL 2720 * 2721 * This command is used to execute general PFM_REQ_HNDLR Functions, most dealing with 2722 * calling SBIOS, or retrieving cached sensor and PFM_REQ_HNDLR state data. 2723 * 2724 * version 2725 * This parameter specifies the version of the interface. Legal values 2726 * for this parameter are 1. 2727 * cmd 2728 * This parameter specifies the PFM_REQ_HNDLR API to be invoked. 2729 * Valid values for this parameter are: 2730 * NV0000_CTRL_PFM_REQ_HNDLR_CMD_GET_THERM_LIMIT 2731 * This command gets the temperature limit for thermal controller. When 2732 * this command is specified the input parameter contains ???. 2733 * NV0000_CTRL_PFM_REQ_HNDLR_CMD_SET_THERM_LIMIT 2734 * This command set the temperature limit for thermal controller. When 2735 * this command is specified the input parameter contains ???. 2736 * input 2737 * This parameter specifies the cmd-specific input value. 2738 * result 2739 * This parameter returns the cmd-specific output value. 2740 * 2741 * Possible status values returned are: 2742 * NV_OK 2743 * NV_ERR_INVALID_PARAM_STRUCT 2744 * NV_ERR_INVALID_ARGUMENT 2745 */ 2746 2747 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL (0x142U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID" */ 2748 2749 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID (0x42U) 2750 2751 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS { 2752 NvU32 cmd; 2753 NvS32 input[2]; 2754 NvS32 result[4]; 2755 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS; 2756 2757 /* valid version values */ 2758 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_PSP_CURRENT_VERSION (0x00010000U) 2759 2760 /* valid cmd values */ 2761 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_THERM_LIMIT (0x00000002U) 2762 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000U) 2763 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_THERMAL_LIMIT (0x00000000U) 2764 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MIN_LIMIT (0x00000001U) 2765 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MAX_LIMIT (0x00000002U) 2766 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE (0x00000003U) 2767 2768 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_THERM_LIMIT (0x00000003U) 2769 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2770 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_THERMAL_LIMIT (0x00000001U) 2771 2772 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA (0x00000004U) 2773 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2774 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DOWN_N_DELTA (0x00000000U) 2775 2776 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA (0x00000005U) 2777 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2778 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DOWN_N_DELTA (0x00000001U) 2779 2780 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA (0x00000006U) 2781 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2782 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_HOLD_DELTA (0x00000000U) 2783 2784 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA (0x00000007U) 2785 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2786 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_HOLD_DELTA (0x00000001U) 2787 2788 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA (0x00000008U) 2789 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2790 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_UP_DELTA (0x00000000U) 2791 2792 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA (0x00000009U) 2793 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2794 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_UP_DELTA (0x00000001U) 2795 2796 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA (0x0000000AU) 2797 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2798 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_ENGAGE_DELTA (0x00000000U) 2799 2800 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA (0x0000000BU) 2801 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2802 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_ENGAGE_DELTA (0x00000001U) 2803 2804 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000CU) 2805 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2806 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) 2807 2808 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000DU) 2809 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2810 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) 2811 2812 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_STATUS (0x00000016U) 2813 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_STATUS (0x00000000U) 2814 2815 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_STATUS (0x00000017U) 2816 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_STATUS (0x00000000U) 2817 2818 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM (0x00000018U) 2819 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_CPU_SET_UTIL_AVG_NUM (0x00000000U) 2820 2821 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM (0x00000019U) 2822 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_CPU_GET_UTIL_AVG_NUM (0x00000000U) 2823 2824 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PERF_SENSOR (0x0000001AU) 2825 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2826 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_NEXT_EXPECTED_POLL (0x00000001U) 2827 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_VALUE (0x00000000U) 2828 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_AVAILABLE (0x00000001U) 2829 2830 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_CALL_ACPI (0x0000001BU) 2831 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_CMD (0x00000000U) 2832 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_PARAM_IN (0x00000001U) 2833 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_1 (0x00000000U) 2834 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_2 (0x00000001U) 2835 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_STATUS (0x00000000U) 2836 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_VERSION (0x00000001U) 2837 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_SZ (0x00000002U) 2838 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_SZ (0x00000000U) 2839 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_COUNT (0x00000001U) 2840 2841 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_IGPU_TURBO (0x0000001CU) 2842 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SET_IGPU_TURBO (0x00000000U) 2843 2844 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERIOD (0x00000026U) 2845 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERIOD (0x00000000U) 2846 2847 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERIOD (0x00000027U) 2848 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERIOD (0x00000000U) 2849 2850 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_NUDGE_FACTOR (0x00000028U) 2851 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_UP (0x00000000U) 2852 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_DOWN (0x00000001U) 2853 2854 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_NUDGE_FACTOR (0x00000029U) 2855 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_UP (0x00000000U) 2856 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_DOWN (0x00000001U) 2857 2858 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES (0x0000002AU) 2859 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) 2860 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) 2861 2862 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES (0x0000002BU) 2863 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) 2864 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) 2865 2866 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERF_LIMITS (0x0000002CU) 2867 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_UPPER (0x00000000U) 2868 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_LOWER (0x00000001U) 2869 2870 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERF_LIMITS (0x0000002DU) 2871 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_UPPER (0x00000000U) 2872 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_LOWER (0x00000001U) 2873 2874 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PM1_AVAILABLE (0x0000002EU) 2875 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_PM1_AVAILABLE (0x00000000U) 2876 2877 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PM1_AVAILABLE (0x0000002FU) 2878 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE (0x00000000U) 2879 2880 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS (0x00000044U) 2881 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) 2882 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 (0x00000001U) 2883 2884 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS (0x00000045U) 2885 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) 2886 2887 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT (0x00000046U) 2888 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ (0000000000U) 2889 2890 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT (0x00000047U) 2891 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ (0000000000U) 2892 2893 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM (0x00000048U) 2894 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_INDEX (0000000000U) 2895 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_AVAILABLE_MASK (0000000001U) 2896 2897 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM (0x00000049U) 2898 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX (0000000000U) 2899 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX_MAX (2U) 2900 2901 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX 7:0 2902 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_MAXPERF (0U) 2903 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_BALANCED (1U) 2904 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_QUIET (2U) 2905 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID (0xFFU) 2906 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK 15:8 2907 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK_INVALID (0U) 2908 2909 /* valid PS_STATUS result values */ 2910 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_OFF (0U) 2911 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_ON (1U) 2912 2913 #define PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK 32U 2914 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS { 2915 NvU32 objHndl; 2916 NvU32 blockId; 2917 NvU32 nextExpectedSampleTimems; 2918 NvU32 countersReq; 2919 NvU32 countersReturned; 2920 NvU32 counterBlock[PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK]; 2921 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS; 2922 2923 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS (0x146U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID" */ 2924 2925 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID (0x46U) 2926 2927 typedef NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS; 2928 2929 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS (0x147U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID" */ 2930 2931 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID (0x47U) 2932 2933 typedef NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS; 2934 2935 /* 2936 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI 2937 * 2938 * This command allows users to call PFM_REQ_HNDLR ACPI commands for testing purposes. 2939 * 2940 * cmd 2941 * This parameter specifies the PFM_REQ_HNDLR ACPI command to execute. 2942 * 2943 * input 2944 * This parameter specified the cmd-dependent input value. 2945 * 2946 * resultSz 2947 * This parameter returns the size (in bytes) of the valid data 2948 * returned in the result parameter. 2949 * 2950 * result 2951 * This parameter returns the results of the specified cmd. 2952 * The maximum size (in bytes) of this returned data will 2953 * not exceed PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 2954 * 2955 * PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 2956 * The size of buffer (result) in unit of NvU32. 2957 * The smallest value is sizeof(PSS_ENTRY)*ACPI_PSS_ENTRY_MAX. 2958 * Since the prior one is 24 bytes, and the later one is 48, 2959 * this value cannot be smaller than 288. 2960 * 2961 * Possible status values returned are: 2962 * NV_OK 2963 * NV_ERR_INVALID_ARGUMENT, 2964 * NV_ERR_INVALID_OBJECT_HANDLE 2965 * NV_ERR_NOT_SUPPORTED 2966 * NV_ERR_INSUFFICIENT_PERMISSIONS 2967 * 2968 */ 2969 #define PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U 2970 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID (0x43U) 2971 2972 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS { 2973 NvU32 cmd; 2974 NvU32 input; 2975 NvU32 resultSz; 2976 NvU32 result[PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE]; 2977 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS; 2978 2979 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI (0x143U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID" */ 2980 2981 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PFM_REQ_HNDLR (0x00008000U) 2982 2983 /* 2984 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA 2985 * 2986 * This command is used to read FRL data based on need. 2987 * 2988 * nextSampleNumber 2989 * This parameter returns the counter of next sample which is being filled. 2990 * samples 2991 * This parameter returns the frame time, render time, target time, client ID 2992 * with one reserve bit for future use. 2993 * 2994 * Possible status values returned are: 2995 * NV_OK 2996 * NV_ERR_NOT_SUPPORTED 2997 */ 2998 2999 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA (0x144U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID" */ 3000 3001 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE 64U 3002 3003 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE { 3004 NvU16 frameTime; 3005 NvU16 renderTime; 3006 NvU16 targetTime; 3007 NvU8 sleepTime; 3008 NvU8 sampleNumber; 3009 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE; 3010 3011 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID (0x44U) 3012 3013 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS { 3014 NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE samples[NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE]; 3015 NvU8 nextSampleNumber; 3016 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS; 3017 3018 /* 3019 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA 3020 * 3021 * This command is used to write FRM data based on need. 3022 * 3023 * frameTime 3024 * This parameter contains the frame time of current frame. 3025 * renderTime 3026 * This parameter contains the render time of current frame. 3027 * targetTime 3028 * This parameter contains the target time of current frame. 3029 * sleepTime 3030 * This parameter contains the sleep duration inserted by FRL for the latest frame. 3031 * 3032 * Possible status values returned are: 3033 * NV_OK 3034 * NV_ERR_NOT_SUPPORTED 3035 */ 3036 3037 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA (0x145U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID" */ 3038 3039 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID (0x45U) 3040 3041 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS { 3042 NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE sampleData; 3043 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS; 3044 3045 /* _ctrl0000system_h_ */ 3046