1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2005-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 #pragma once 24 25 #include <nvtypes.h> 26 27 // 28 // This file was generated with FINN, an NVIDIA coding tool. 29 // Source file: ctrl/ctrl0000/ctrl0000system.finn 30 // 31 32 #include "ctrl/ctrlxxxx.h" 33 #include "ctrl/ctrl0000/ctrl0000base.h" 34 35 /* NV01_ROOT (client) system control commands and parameters */ 36 37 /* 38 * NV0000_CTRL_CMD_SYSTEM_GET_FEATURES 39 * 40 * This command returns a mask of supported features for the SYSTEM category 41 * of the 0000 class. 42 * 43 * Valid features include: 44 * 45 * NV0000_CTRL_GET_FEATURES_SLI 46 * When this bit is set, SLI is supported. 47 * NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT 48 * When this bit is set, EFI has initialized core channel 49 * NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED 50 * When this bit is set, RM test only code is supported. 51 * 52 * Possible status values returned are: 53 * NV_OK 54 * NV_ERR_INVALID_STATE 55 */ 56 #define NV0000_CTRL_CMD_SYSTEM_GET_FEATURES (0x1f0U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID" */ 57 58 #define NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID (0xF0U) 59 60 typedef struct NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS { 61 NvU32 featuresMask; 62 } NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS; 63 64 65 66 /* Valid feature values */ 67 #define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI 0:0 68 #define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE (0x00000000U) 69 #define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE (0x00000001U) 70 71 #define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT 2:2 72 #define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE (0x00000000U) 73 #define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE (0x00000001U) 74 75 #define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING 3:3 76 #define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_FALSE (0x00000000U) 77 #define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_TRUE (0x00000001U) 78 79 #define NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED 4:4 80 #define NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_FALSE (0x00000000U) 81 #define NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_TRUE (0x00000001U) 82 /* 83 * NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION 84 * 85 * This command returns the current driver information. 86 * The first time this is called the size of strings is 87 * set with the greater of NV_BUILD_BRANCH_VERSION and 88 * NV_DISPLAY_DRIVER_TITLE. The client then allocates memory 89 * of size sizeOfStrings for pVersionBuffer and pTitleBuffer 90 * and calls the command again to receive driver info. 91 * 92 * sizeOfStrings 93 * This field returns the size in bytes of the pVersionBuffer and 94 * pTitleBuffer strings. 95 * pDriverVersionBuffer 96 * This field returns the version (NV_VERSION_STRING). 97 * pVersionBuffer 98 * This field returns the version (NV_BUILD_BRANCH_VERSION). 99 * pTitleBuffer 100 * This field returns the title (NV_DISPLAY_DRIVER_TITLE). 101 * changelistNumber 102 * This field returns the changelist value (NV_BUILD_CHANGELIST_NUM). 103 * officialChangelistNumber 104 * This field returns the last official changelist value 105 * (NV_LAST_OFFICIAL_CHANGELIST_NUM). 106 * 107 * Possible status values returned are: 108 * NV_OK 109 * NV_ERR_INVALID_PARAM_STRUCT 110 */ 111 112 #define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION (0x101U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID" */ 113 114 #define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID (0x1U) 115 116 typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS { 117 NvU32 sizeOfStrings; 118 NV_DECLARE_ALIGNED(NvP64 pDriverVersionBuffer, 8); 119 NV_DECLARE_ALIGNED(NvP64 pVersionBuffer, 8); 120 NV_DECLARE_ALIGNED(NvP64 pTitleBuffer, 8); 121 NvU32 changelistNumber; 122 NvU32 officialChangelistNumber; 123 } NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS; 124 125 typedef enum NV0000_CTRL_SYSTEM_SH_SOC_TYPE { 126 NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NA = 0, 127 NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NV_GRACE = 1, 128 129 } NV0000_CTRL_SYSTEM_SH_SOC_TYPE; 130 131 /* 132 * NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO 133 * 134 * This command returns system CPU information. 135 * 136 * type 137 * This field returns the processor type. 138 * Legal processor types include: 139 * Intel processors: 140 * P55 : P55C - MMX 141 * P6 : PPro 142 * P2 : PentiumII 143 * P2XC : Xeon & Celeron 144 * CELA : Celeron-A 145 * P3 : Pentium-III 146 * P3_INTL2 : Pentium-III w/integrated L2 (fullspeed, on die, 256K) 147 * P4 : Pentium 4 148 * CORE2 : Core2 Duo Conroe 149 * AMD processors 150 * K62 : K6-2 w/ 3DNow 151 * IDT/Centaur processors 152 * C6 : WinChip C6 153 * C62 : WinChip 2 w/ 3DNow 154 * Cyrix processors 155 * GX : MediaGX 156 * M1 : 6x86 157 * M2 : M2 158 * MGX : MediaGX w/ MMX 159 * Transmeta processors 160 * TM_CRUSOE : Transmeta Crusoe(tm) 161 * PowerPC processors 162 * PPC603 : PowerPC 603 163 * PPC604 : PowerPC 604 164 * PPC750 : PowerPC 750 165 * 166 * capabilities 167 * This field returns the capabilities of the processor. 168 * Legal processor capabilities include: 169 * MMX : supports MMX 170 * SSE : supports SSE 171 * 3DNOW : supports 3DNow 172 * SSE2 : supports SSE2 173 * SFENCE : supports SFENCE 174 * WRITE_COMBINING : supports write-combining 175 * ALTIVEC : supports ALTIVEC 176 * PUT_NEEDS_IO : requires OUT inst w/PUT updates 177 * NEEDS_WC_WORKAROUND : requires workaround for P4 write-combining bug 178 * 3DNOW_EXT : supports 3DNow Extensions 179 * MMX_EXT : supports MMX Extensions 180 * CMOV : supports CMOV 181 * CLFLUSH : supports CLFLUSH 182 * SSE3 : supports SSE3 183 * NEEDS_WAR_124888 : requires write to GPU while spinning on 184 * : GPU value 185 * HT : support hyper-threading 186 * clock 187 * This field returns the processor speed in MHz. 188 * L1DataCacheSize 189 * This field returns the level 1 data (or unified) cache size 190 * in kilobytes. 191 * L2DataCacheSize 192 * This field returns the level 2 data (or unified) cache size 193 * in kilobytes. 194 * dataCacheLineSize 195 * This field returns the bytes per line in the level 1 data cache. 196 * numLogicalCpus 197 * This field returns the number of logical processors. On Intel x86 198 * systems that support it, this value will incorporate the current state 199 * of HyperThreading. 200 * numPhysicalCpus 201 * This field returns the number of physical processors. 202 * name 203 * This field returns the CPU name in ASCII string format. 204 * family 205 * Vendor defined Family and Extended Family combined 206 * model 207 * Vendor defined Model and Extended Model combined 208 * stepping 209 * Silicon stepping 210 * bCCEnabled 211 * Confidentail compute enabled/disabled state 212 * selfHostedSocType 213 * SoC type NV0000_CTRL_SYSTEM_SH_SOC_TYPE* in case of self hosted systems 214 * 215 * Possible status values returned are: 216 * NV_OK 217 * NV_ERR_INVALID_PARAM_STRUCT 218 */ 219 #define NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO (0x102U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID" */ 220 221 #define NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID (0x2U) 222 223 typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS { 224 NvU32 type; /* processor type */ 225 NvU32 capabilities; /* processor caps */ 226 NvU32 clock; /* processor speed (MHz) */ 227 NvU32 L1DataCacheSize; /* L1 dcache size (KB) */ 228 NvU32 L2DataCacheSize; /* L2 dcache size (KB) */ 229 NvU32 dataCacheLineSize; /* L1 dcache bytes/line */ 230 NvU32 numLogicalCpus; /* logial processor cnt */ 231 NvU32 numPhysicalCpus; /* physical processor cnt*/ 232 NvU8 name[52]; /* embedded cpu name */ 233 NvU32 family; /* Vendor defined Family and Extended Family combined */ 234 NvU32 model; /* Vendor defined Model and Extended Model combined */ 235 NvU8 stepping; /* Silicon stepping */ 236 NvU32 coresOnDie; /* cpu cores per die */ 237 NvBool bCCEnabled; /* CC enabled on cpu */ 238 NV0000_CTRL_SYSTEM_SH_SOC_TYPE selfHostedSocType; /* SoC type in case of self hosted systems */ 239 } NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS; 240 241 // Macros for CPU family information 242 #define NV0000_CTRL_SYSTEM_CPU_FAMILY 3:0 243 #define NV0000_CTRL_SYSTEM_CPU_EXTENDED_FAMILY 11:4 244 245 // Macros for CPU model information 246 #define NV0000_CTRL_SYSTEM_CPU_MODEL 3:0 247 #define NV0000_CTRL_SYSTEM_CPU_EXTENDED_MODEL 7:4 248 249 // Macros for AMD CPU information 250 #define NV0000_CTRL_SYSTEM_CPU_ID_AMD_FAMILY 0xF 251 #define NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_FAMILY 0xA 252 #define NV0000_CTRL_SYSTEM_CPU_ID_AMD_MODEL 0x0 253 #define NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_MODEL 0x4 254 255 // Macros for Intel CPU information 256 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_FAMILY 0x6 257 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_FAMILY 0x0 258 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_S_MODEL 0x7 259 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_P_MODEL 0xA 260 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_MODEL 0x9 261 262 /* processor type values */ 263 #define NV0000_CTRL_SYSTEM_CPU_TYPE_UNKNOWN (0x00000000U) 264 /* Intel types */ 265 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P5 (0x00000001U) 266 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P55 (0x00000002U) 267 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P6 (0x00000003U) 268 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P2 (0x00000004U) 269 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P2XC (0x00000005U) 270 #define NV0000_CTRL_SYSTEM_CPU_TYPE_CELA (0x00000006U) 271 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P3 (0x00000007U) 272 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P3_INTL2 (0x00000008U) 273 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P4 (0x00000009U) 274 #define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2 (0x00000010U) 275 #define NV0000_CTRL_SYSTEM_CPU_TYPE_CELN_M16H (0x00000011U) 276 #define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2_EXTRM (0x00000012U) 277 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM (0x00000013U) 278 #define NV0000_CTRL_SYSTEM_CPU_TYPE_XEON_SPR (0x00000014U) 279 /* AMD types */ 280 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K5 (0x00000030U) 281 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K6 (0x00000031U) 282 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K62 (0x00000032U) 283 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K63 (0x00000033U) 284 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K7 (0x00000034U) 285 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K8 (0x00000035U) 286 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K10 (0x00000036U) 287 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K11 (0x00000037U) 288 #define NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN (0x00000038U) 289 /* IDT/Centaur types */ 290 #define NV0000_CTRL_SYSTEM_CPU_TYPE_C6 (0x00000060U) 291 #define NV0000_CTRL_SYSTEM_CPU_TYPE_C62 (0x00000061U) 292 /* Cyrix types */ 293 #define NV0000_CTRL_SYSTEM_CPU_TYPE_GX (0x00000070U) 294 #define NV0000_CTRL_SYSTEM_CPU_TYPE_M1 (0x00000071U) 295 #define NV0000_CTRL_SYSTEM_CPU_TYPE_M2 (0x00000072U) 296 #define NV0000_CTRL_SYSTEM_CPU_TYPE_MGX (0x00000073U) 297 /* Transmeta types */ 298 #define NV0000_CTRL_SYSTEM_CPU_TYPE_TM_CRUSOE (0x00000080U) 299 /* IBM types */ 300 #define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC603 (0x00000090U) 301 #define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC604 (0x00000091U) 302 #define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC750 (0x00000092U) 303 #define NV0000_CTRL_SYSTEM_CPU_TYPE_POWERN (0x00000093U) 304 /* Unknown ARM architecture CPU type */ 305 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_UNKNOWN (0xA0000000U) 306 /* ARM Ltd types */ 307 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A9 (0xA0000009U) 308 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A15 (0xA000000FU) 309 /* NVIDIA types */ 310 #define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_1_0 (0xA0001000U) 311 #define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_2_0 (0xA0002000U) 312 313 /* Generic types */ 314 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC (0xA00FF000U) 315 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC (0xA00FF001U) 316 317 /* processor capabilities */ 318 #define NV0000_CTRL_SYSTEM_CPU_CAP_MMX (0x00000001U) 319 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE (0x00000002U) 320 #define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW (0x00000004U) 321 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 (0x00000008U) 322 #define NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE (0x00000010U) 323 #define NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING (0x00000020U) 324 #define NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC (0x00000040U) 325 #define NV0000_CTRL_SYSTEM_CPU_CAP_PUT_NEEDS_IO (0x00000080U) 326 #define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WC_WORKAROUND (0x00000100U) 327 #define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT (0x00000200U) 328 #define NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT (0x00000400U) 329 #define NV0000_CTRL_SYSTEM_CPU_CAP_CMOV (0x00000800U) 330 #define NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH (0x00001000U) 331 #define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_190854 (0x00002000U) /* deprecated */ 332 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 (0x00004000U) 333 #define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_124888 (0x00008000U) 334 #define NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE (0x00010000U) 335 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 (0x00020000U) 336 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 (0x00040000U) 337 #define NV0000_CTRL_SYSTEM_CPU_CAP_AVX (0x00080000U) 338 #define NV0000_CTRL_SYSTEM_CPU_CAP_ERMS (0x00100000U) 339 340 /* 341 * NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO 342 * 343 * This command returns system chipset information. 344 * 345 * vendorId 346 * This parameter returns the vendor identification for the chipset. 347 * A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the chipset 348 * cannot be identified. 349 * deviceId 350 * This parameter returns the device identification for the chipset. 351 * A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the chipset 352 * cannot be identified. 353 * subSysVendorId 354 * This parameter returns the subsystem vendor identification for the 355 * chipset. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the 356 * chipset cannot be identified. 357 * subSysDeviceId 358 * This parameter returns the subsystem device identification for the 359 * chipset. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the 360 * chipset cannot be identified. 361 * HBvendorId 362 * This parameter returns the vendor identification for the chipset's 363 * host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates 364 * the chipset's host bridge cannot be identified. 365 * HBdeviceId 366 * This parameter returns the device identification for the chipset's 367 * host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates 368 * the chipset's host bridge cannot be identified. 369 * HBsubSysVendorId 370 * This parameter returns the subsystem vendor identification for the 371 * chipset's host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID 372 * indicates the chipset's host bridge cannot be identified. 373 * HBsubSysDeviceId 374 * This parameter returns the subsystem device identification for the 375 * chipset's host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID 376 * indicates the chipset's host bridge cannot be identified. 377 * sliBondId 378 * This parameter returns the SLI bond identification for the chipset. 379 * vendorNameString 380 * This parameter returns the vendor name string. 381 * chipsetNameString 382 * This parameter returns the vendor name string. 383 * sliBondNameString 384 * This parameter returns the SLI bond name string. 385 * flag 386 * This parameter specifies NV0000_CTRL_SYSTEM_CHIPSET_FLAG_XXX flags: 387 * _HAS_RESIZABLE_BAR_ISSUE_YES: Chipset where the use of resizable BAR1 388 * should be disabled - bug 3440153 389 * 390 * Possible status values returned are: 391 * NV_OK 392 * NV_ERR_INVALID_PARAM_STRUCT 393 * NV_ERR_INVALID_ARGUMENT 394 * NV_ERR_OPERATING_SYSTEM 395 */ 396 #define NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO (0x104U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID" */ 397 398 /* maximum name string length */ 399 #define NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH (0x0000020U) 400 401 /* invalid id */ 402 #define NV0000_SYSTEM_CHIPSET_INVALID_ID (0xffffU) 403 404 #define NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID (0x4U) 405 406 typedef struct NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS { 407 NvU16 vendorId; 408 NvU16 deviceId; 409 NvU16 subSysVendorId; 410 NvU16 subSysDeviceId; 411 NvU16 HBvendorId; 412 NvU16 HBdeviceId; 413 NvU16 HBsubSysVendorId; 414 NvU16 HBsubSysDeviceId; 415 NvU32 sliBondId; 416 NvU8 vendorNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; 417 NvU8 subSysVendorNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; 418 NvU8 chipsetNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; 419 NvU8 sliBondNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; 420 NvU32 flags; 421 } NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS; 422 423 #define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE 0:0 424 #define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_NO (0x00000000U) 425 #define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_YES (0x00000001U) 426 427 428 429 /* 430 * NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT 431 * 432 * This command returns whether the VRR cookie is present in the SBIOS. 433 * 434 * bIsPresent (out) 435 * This parameter contains whether the VRR cookie is present in the SBIOS. 436 * 437 * Possible status values returned are: 438 * NV_OK 439 * NV_ERR_INVALID_REQUEST 440 * NV_ERR_NOT_SUPPORTED 441 */ 442 443 #define NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT (0x107U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS_MESSAGE_ID" */ 444 445 #define NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS_MESSAGE_ID (0x7U) 446 447 typedef struct NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS { 448 NvBool bIsPresent; 449 } NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS; 450 451 /* 452 * NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES 453 * 454 * This command is used to retrieve the measured times spent holding and waiting for 455 * the main RM locks (API and GPU). 456 * 457 * waitApiLock 458 * Total time spent by RM API's waiting to acquire the API lock 459 * 460 * holdRoApiLock 461 * Total time spent by RM API's holding the API lock in RO mode. 462 * 463 * holdRwApiLock 464 * Total time spent by RM API's holding the API lock in RW mode. 465 * 466 * waitGpuLock 467 * Total time spent by RM API's waiting to acquire one or more GPU locks. 468 * 469 * holdGpuLock 470 * Total time spent by RM API's holding one or more GPU locks. 471 * 472 * 473 * Possible status values returned are: 474 * NV_OK 475 * NV_ERR_NOT_SUPPORTED 476 */ 477 478 #define NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES (0x109U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID" */ 479 480 #define NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID (0x9U) 481 482 typedef struct NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS { 483 NV_DECLARE_ALIGNED(NvU64 waitApiLock, 8); 484 NV_DECLARE_ALIGNED(NvU64 holdRoApiLock, 8); 485 NV_DECLARE_ALIGNED(NvU64 holdRwApiLock, 8); 486 NV_DECLARE_ALIGNED(NvU64 waitGpuLock, 8); 487 NV_DECLARE_ALIGNED(NvU64 holdGpuLock, 8); 488 } NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS; 489 490 /* 491 * NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST 492 * 493 * This command is used to retrieve the set of system-level classes 494 * supported by the platform. 495 * 496 * numClasses 497 * This parameter returns the number of valid entries in the returned 498 * classes[] list. This parameter will not exceed 499 * Nv0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE. 500 * classes 501 * This parameter returns the list of supported classes 502 * 503 * Possible status values returned are: 504 * NV_OK 505 * NV_ERR_INVALID_PARAM_STRUCT 506 */ 507 508 #define NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST (0x108U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID" */ 509 510 /* maximum number of classes returned in classes[] array */ 511 #define NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE (32U) 512 513 #define NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID (0x8U) 514 515 typedef struct NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS { 516 NvU32 numClasses; 517 NvU32 classes[NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE]; 518 } NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS; 519 520 /* 521 * NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT 522 * 523 * This command is used to send triggered mobile related system events 524 * to the RM. 525 * 526 * eventType 527 * This parameter indicates the triggered event type. This parameter 528 * should specify a valid NV0000_CTRL_SYSTEM_EVENT_TYPE value. 529 * eventData 530 * This parameter specifies the type-dependent event data associated 531 * with EventType. This parameter should specify a valid 532 * NV0000_CTRL_SYSTEM_EVENT_DATA value. 533 * bEventDataForced 534 * This parameter specifies what we have to do, Whether trust current 535 * Lid/Dock state or not. This parameter should specify a valid 536 * NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED value. 537 538 * Possible status values returned are: 539 * NV_OK 540 * NV_ERR_INVALID_PARAM_STRUCT 541 * NV_ERR_INVALID_ARGUMENT 542 * 543 * Sync this up (#defines) with one in nvapi.spec! 544 * (NV_ACPI_EVENT_TYPE & NV_ACPI_EVENT_DATA) 545 */ 546 #define NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT (0x110U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID" */ 547 548 #define NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID (0x10U) 549 550 typedef struct NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS { 551 NvU32 eventType; 552 NvU32 eventData; 553 NvBool bEventDataForced; 554 } NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS; 555 556 /* valid eventType values */ 557 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_LID_STATE (0x00000000U) 558 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_POWER_SOURCE (0x00000001U) 559 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_DOCK_STATE (0x00000002U) 560 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_LID (0x00000003U) 561 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_DOCK (0x00000004U) 562 563 /* valid eventData values */ 564 #define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_OPEN (0x00000000U) 565 #define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_CLOSED (0x00000001U) 566 #define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_BATTERY (0x00000000U) 567 #define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_AC (0x00000001U) 568 #define NV0000_CTRL_SYSTEM_EVENT_DATA_UNDOCKED (0x00000000U) 569 #define NV0000_CTRL_SYSTEM_EVENT_DATA_DOCKED (0x00000001U) 570 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DSM (0x00000000U) 571 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DCS (0x00000001U) 572 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_NVIF (0x00000002U) 573 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_ACPI (0x00000003U) 574 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL (0x00000004U) 575 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_COUNT (0x5U) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL + 1)" */ 576 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DSM (0x00000000U) 577 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DCS (0x00000001U) 578 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_NVIF (0x00000002U) 579 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_ACPI (0x00000003U) 580 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL (0x00000004U) 581 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_COUNT (0x5U) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL + 1)" */ 582 583 /* valid bEventDataForced values */ 584 #define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_FALSE (0x00000000U) 585 #define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_TRUE (0x00000001U) 586 587 /* 588 * NV000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE 589 * 590 * This command is used to query the platform type. 591 * 592 * systemType 593 * This parameter returns the type of the system. 594 * Legal values for this parameter include: 595 * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP 596 * The system is a desktop platform. 597 * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC 598 * The system is a mobile (non-Toshiba) platform. 599 * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP 600 * The system is a mobile Toshiba platform. 601 * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC 602 * The system is a system-on-a-chip (SOC) platform. 603 * 604 605 * Possible status values returned are: 606 * NV_OK 607 * NV_ERR_INVALID_PARAM_STRUCT 608 * NV_ERR_INVALID_ARGUMENT 609 */ 610 #define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE (0x111U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID" */ 611 612 #define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID (0x11U) 613 614 typedef struct NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS { 615 NvU32 systemType; 616 } NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS; 617 618 /* valid systemType values */ 619 #define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP (0x000000U) 620 #define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC (0x000001U) 621 #define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_TOSHIBA (0x000002U) 622 #define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC (0x000003U) 623 624 625 626 627 /* 628 * NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL 629 * 630 * This command controls the current RmMsg filters. 631 * 632 * It is only supported if RmMsg is enabled (e.g. debug builds). 633 * 634 * cmd 635 * GET - Gets the current RmMsg filter string. 636 * SET - Sets the current RmMsg filter string. 637 * 638 * count 639 * The length of the RmMsg filter string. 640 * 641 * data 642 * The RmMsg filter string. 643 * 644 * Possible status values returned are: 645 * NV_OK 646 * NV_ERR_INVALID_ARGUMENT 647 * NV_ERR_NOT_SUPPORTED 648 */ 649 #define NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL (0x121U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID" */ 650 651 #define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE 512U 652 653 #define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_GET (0x00000000U) 654 #define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_SET (0x00000001U) 655 656 #define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID (0x21U) 657 658 typedef struct NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS { 659 NvU32 cmd; 660 NvU32 count; 661 NvU8 data[NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE]; 662 } NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS; 663 664 /* 665 * NV0000_CTRL_SYSTEM_HWBC_INFO 666 * 667 * This structure contains information about the HWBC (BR04) specified by 668 * hwbcId. 669 * 670 * hwbcId 671 * This field specifies the HWBC ID. 672 * firmwareVersion 673 * This field returns the version of the firmware on the HWBC (BR04), if 674 * present. This is a packed binary number of the form 0x12345678, which 675 * corresponds to a firmware version of 12.34.56.78. 676 * subordinateBus 677 * This field returns the subordinate bus number of the HWBC (BR04). 678 * secondaryBus 679 * This field returns the secondary bus number of the HWBC (BR04). 680 * 681 * Possible status values returned are: 682 * NV_OK 683 * NV_ERR_INVALID_ARGUMENT 684 */ 685 686 typedef struct NV0000_CTRL_SYSTEM_HWBC_INFO { 687 NvU32 hwbcId; 688 NvU32 firmwareVersion; 689 NvU32 subordinateBus; 690 NvU32 secondaryBus; 691 } NV0000_CTRL_SYSTEM_HWBC_INFO; 692 693 #define NV0000_CTRL_SYSTEM_HWBC_INVALID_ID (0xFFFFFFFFU) 694 695 /* 696 * NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO 697 * 698 * This command returns information about all Hardware Broadcast (HWBC) 699 * devices present in the system that are BR04s. To get the complete 700 * list of HWBCs in the system, all GPUs present in the system must be 701 * initialized. See the description of NV0000_CTRL_CMD_GPU_ATTACH_IDS to 702 * accomplish this. 703 * 704 * hwbcInfo 705 * This field is an array of NV0000_CTRL_SYSTEM_HWBC_INFO structures into 706 * which HWBC information is placed. There is one entry for each HWBC 707 * present in the system. Valid entries are contiguous, invalid entries 708 * have the hwbcId equal to NV0000_CTRL_SYSTEM_HWBC_INVALID_ID. If no HWBC 709 * is present in the system, all the entries would be marked invalid, but 710 * the return value would still be SUCCESS. 711 * 712 * Possible status values returned are: 713 * NV_OK 714 * NV_ERR_INVALID_ARGUMENT 715 */ 716 #define NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO (0x124U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID" */ 717 718 #define NV0000_CTRL_SYSTEM_MAX_HWBCS (0x00000080U) 719 720 #define NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID (0x24U) 721 722 typedef struct NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS { 723 NV0000_CTRL_SYSTEM_HWBC_INFO hwbcInfo[NV0000_CTRL_SYSTEM_MAX_HWBCS]; 724 } NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS; 725 726 /* 727 * NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL 728 * 729 * This command is used to control GPS functionality. It allows control of 730 * GPU Performance Scaling (GPS), changing its operational parameters and read 731 * most GPS dynamic parameters. 732 * 733 * command 734 * This parameter specifies the command to execute. Invalid commands 735 * result in the return of an NV_ERR_INVALID_ARGUMENT status. 736 * locale 737 * This parameter indicates the specific locale to which the command 738 * 'command' is to be applied. 739 * Supported range of CPU/GPU {i = 0, ..., 255} 740 * data 741 * This parameter contains a command-specific data payload. It can 742 * be used to input data as well as output data. 743 * 744 * Possible status values returned are: 745 * NV_OK 746 * NV_ERR_INVALID_COMMAND 747 * NV_ERR_INVALID_STATE 748 * NV_ERR_INVALID_DATA 749 * NV_ERR_INVALID_REQUEST 750 * NV_ERR_NOT_SUPPORTED 751 */ 752 #define NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL (0x122U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID" */ 753 754 #define NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID (0x22U) 755 756 typedef struct NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS { 757 NvU16 command; 758 NvU16 locale; 759 NvU32 data; 760 } NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS; 761 762 /* 763 * Valid command values : 764 * 765 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT 766 * Is used to check if GPS was correctly initialized. 767 * Possible return (OUT) values are: 768 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO 769 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES 770 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC 771 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC 772 * Are used to stop/start GPS functionality and to get current status. 773 * Possible IN/OUT values are: 774 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP 775 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START 776 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS 777 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS 778 * Are used to control execution of GPS actions and to get current status. 779 * Possible IN/OUT values are: 780 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF 781 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON 782 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC 783 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC 784 * Are used to switch current GPS logic and to retrieve current logic. 785 * Possible IN/OUT values are: 786 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF 787 * Will cause that all GPS actions will be NULL. 788 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY 789 * Fuzzy logic will determine GPS actions based on current ruleset. 790 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC 791 * Deterministic logic will define GPS actions based on current ruleset. 792 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE 793 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE 794 * Are used to set/retrieve system control preference. 795 * Possible IN/OUT values are: 796 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU 797 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU 798 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH 799 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT 800 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT 801 * Are used to set/retrieve GPU2CPU pstate limits. 802 * IN/OUT values are four bytes packed into a 32-bit data field. 803 * The CPU cap index for GPU pstate 0 is in the lowest byte, the CPU cap 804 * index for the GPU pstate 3 is in the highest byte, etc. One 805 * special value is to disable the override to the GPU2CPU map: 806 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE 807 * Is used to stop/start GPS PMU functionality. 808 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE 809 * Is used to get the current status of PMU GPS. 810 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE 811 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER 812 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER 813 * Are used to set/retrieve max power [mW] that system can provide. 814 * This is hardcoded GPS safety feature and logic/rules does not apply 815 * to this threshold. 816 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET 817 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET 818 * Are used to set/retrieve current system cooling budget [mW]. 819 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD 820 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD 821 * Are used to set/retrieve integration interval [sec]. 822 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET 823 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET 824 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT 825 * Are used to set/retrieve used ruleset [#]. Value is checked 826 * against MAX number of rules for currently used GPS logic. Also COUNT 827 * provides a way to find out how many rules exist for the current control 828 * system. 829 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST 830 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST 831 * Is used to set/get a delay relative to now during which to allow unbound 832 * CPU performance. Units are seconds. 833 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE 834 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE 835 * Is used to override/get the actual power supply mode (AC/Battery). 836 * Possible IN/OUT values are: 837 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL 838 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC 839 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT 840 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO 841 * Is used to get the Ventura system information for VCT tool 842 * Returned 32bit value should be treated as bitmask and decoded in 843 * following way: 844 * Encoding details are defined in objgps.h refer to 845 * NV_GPS_SYS_SUPPORT_INFO and corresponding bit defines. 846 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTION 847 * Is used to get the supported sub-functions defined in SBIOS. Returned 848 * value is a bitmask where each bit corresponds to different function: 849 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT 850 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS 851 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS 852 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC 853 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC 854 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB 855 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS 856 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER 857 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA 858 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE 859 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG 860 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL 861 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN 862 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE 863 * Are used to retrieve appropriate power measurements and their derivatives 864 * in [mW] for required locale. _BURDEN is defined only for _LOCALE_SYSTEM. 865 * _INTERMEDIATE is not defined for _LOCALE_SYSTEM, and takes an In value as 866 * index. 867 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS 868 * Is used to retrieve parameters when adjusting raw sensor power reading. 869 * The values may come from SBIOS, VBIOS, registry or driver default. 870 * Possible IN value is the index of interested parameter. 871 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP 872 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA 873 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE 874 * Are used to retrieve appropriate temperature measurements and their 875 * derivatives in [1/1000 Celsius]. 876 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE 877 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP 878 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN 879 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX 880 * Are used to retrieve CPU(x)/GPU(x) p-state or it's limits. 881 * Not applicable to _LOCALE_SYSTEM. 882 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION 883 * Is used to retrieve last GPS action for given domain. 884 * Not applicable to _LOCALE_SYSTEM. 885 * Possible return (OUT) values are: 886 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 887 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 888 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING 889 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT 890 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 891 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 892 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM 893 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM 894 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE 895 * Is used to set the power sensor simulator state. 896 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE 897 * Is used to get the power simulator sensor simulator state. 898 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA 899 * Is used to set power sensor simulator data 900 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA 901 * Is used to get power sensor simulator data 902 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK 903 * Is used to respond to the ACPI event triggered by SBIOS. RM will 904 * request value for budget and status, validate them, apply them 905 * and send ACK back to SBIOS. 906 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT 907 * Is a test cmd that should notify SBIOS to send ACPI event requesting 908 * budget and status change. 909 */ 910 #define NV0000_CTRL_CMD_SYSTEM_GPS_INVALID (0xFFFFU) 911 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT (0x0000U) 912 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC (0x0001U) 913 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC (0x0002U) 914 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS (0x0003U) 915 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS (0x0004U) 916 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC (0x0005U) 917 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC (0x0006U) 918 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE (0x0007U) 919 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE (0x0008U) 920 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT (0x0009U) 921 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT (0x000AU) 922 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE (0x000BU) 923 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE (0x000CU) 924 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER (0x0100U) 925 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER (0x0101U) 926 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET (0x0102U) 927 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET (0x0103U) 928 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD (0x0104U) 929 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD (0x0105U) 930 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET (0x0106U) 931 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET (0x0107U) 932 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT (0x0108U) 933 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST (0x0109U) 934 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST (0x010AU) 935 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE (0x010BU) 936 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE (0x010CU) 937 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO (0x010DU) 938 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTIONS (0x010EU) 939 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER (0x0200U) 940 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA (0x0201U) 941 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE (0x0202U) 942 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG (0x0203U) 943 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL (0x0204U) 944 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN (0x0205U) 945 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE (0x0206U) 946 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS (0x0210U) 947 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP (0x0220U) 948 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA (0x0221U) 949 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE (0x0222U) 950 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE (0x0240U) 951 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP (0x0241U) 952 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN (0x0242U) 953 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX (0x0243U) 954 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION (0x0244U) 955 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_SLFM_PRESENT (0x0245U) 956 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE (0x0250U) 957 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE (0x0251U) 958 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA (0x0252U) 959 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA (0x0253U) 960 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK (0x0320U) 961 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT (0x0321U) 962 963 /* valid LOCALE values */ 964 #define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_INVALID (0xFFFFU) 965 #define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_SYSTEM (0x0000U) 966 #define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_CPU(i) (0x0100+((i)%0x100)) 967 #define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_GPU(i) (0x0200+((i)%0x100)) 968 969 /* valid data values for enums */ 970 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID (0x80000000U) 971 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO (0x00000000U) 972 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES (0x00000001U) 973 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP (0x00000000U) 974 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START (0x00000001U) 975 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF (0x00000000U) 976 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON (0x00000001U) 977 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF (0x00000000U) 978 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY (0x00000001U) 979 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC (0x00000002U) 980 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU (0x00000000U) 981 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU (0x00000001U) 982 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH (0x00000002U) 983 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE (0xFFFFFFFFU) 984 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_OFF (0x00000000U) 985 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_ON (0x00000001U) 986 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL (0x00000000U) 987 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC (0x00000001U) 988 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT (0x00000002U) 989 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT (0x00000001U) 990 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS (0x00000002U) 991 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS (0x00000004U) 992 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC (0x00000008U) 993 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC (0x00000010U) 994 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB (0x00000020U) 995 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS (0x00000040U) 996 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 (0x00000000U) 997 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 (0x00000001U) 998 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING (0x00000002U) 999 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT (0x00000003U) 1000 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 (0x00000004U) 1001 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 (0x00000005U) 1002 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM (0x00000006U) 1003 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM (0x00000007U) 1004 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_NO (0x00000000U) 1005 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_YES (0x00000001U) 1006 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_OFF (0x00000000U) 1007 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_ON (0x00000001U) 1008 1009 /* 1010 * NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL 1011 * 1012 * This command allows execution of multiple GpsControl commands within one 1013 * RmControl call. For practical reasons # of commands is limited to 16. 1014 * This command shares defines with NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL. 1015 * 1016 * cmdCount 1017 * Number of commands that should be executed. 1018 * Less or equal to NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX. 1019 * 1020 * succeeded 1021 * Number of commands that were succesully executed. 1022 * Less or equal to NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX. 1023 * Failing commands return NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID 1024 * in their data field. 1025 * 1026 * cmdData 1027 * Array of commands with following structure: 1028 * command 1029 * This parameter specifies the command to execute. 1030 * Invalid commands result in the return of an 1031 * NV_ERR_INVALID_ARGUMENT status. 1032 * locale 1033 * This parameter indicates the specific locale to which 1034 * the command 'command' is to be applied. 1035 * Supported range of CPU/GPU {i = 0, ..., 255} 1036 * data 1037 * This parameter contains a command-specific data payload. 1038 * It is used both to input data as well as to output data. 1039 * 1040 * Possible status values returned are: 1041 * NV_OK 1042 * NV_ERR_INVALID_REQUEST 1043 * NV_ERR_NOT_SUPPORTED 1044 */ 1045 #define NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL (0x123U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID" */ 1046 1047 #define NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX (16U) 1048 #define NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID (0x23U) 1049 1050 typedef struct NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS { 1051 NvU32 cmdCount; 1052 NvU32 succeeded; 1053 1054 struct { 1055 NvU16 command; 1056 NvU16 locale; 1057 NvU32 data; 1058 } cmdData[NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX]; 1059 } NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS; 1060 1061 1062 /* 1063 * Deprecated. Please use NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 instead. 1064 */ 1065 #define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS (0x127U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID" */ 1066 1067 /* 1068 * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED must remain equal to the square of 1069 * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS due to Check RM parsing issues. 1070 * NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS is the maximum size of GPU groups 1071 * allowed for batched P2P caps queries provided by the RM control 1072 * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX. 1073 */ 1074 #define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS 32U 1075 #define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED 1024U 1076 #define NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS 8U 1077 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER 0xffffffffU 1078 1079 /* P2P capabilities status index values */ 1080 #define NV0000_CTRL_P2P_CAPS_INDEX_READ 0U 1081 #define NV0000_CTRL_P2P_CAPS_INDEX_WRITE 1U 1082 #define NV0000_CTRL_P2P_CAPS_INDEX_NVLINK 2U 1083 #define NV0000_CTRL_P2P_CAPS_INDEX_ATOMICS 3U 1084 #define NV0000_CTRL_P2P_CAPS_INDEX_PROP 4U 1085 #define NV0000_CTRL_P2P_CAPS_INDEX_LOOPBACK 5U 1086 #define NV0000_CTRL_P2P_CAPS_INDEX_PCI 6U 1087 #define NV0000_CTRL_P2P_CAPS_INDEX_C2C 7U 1088 #define NV0000_CTRL_P2P_CAPS_INDEX_PCI_BAR1 8U 1089 1090 #define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE 9U 1091 1092 1093 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID (0x27U) 1094 1095 typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS { 1096 NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 1097 NvU32 gpuCount; 1098 NvU32 p2pCaps; 1099 NvU32 p2pOptimalReadCEs; 1100 NvU32 p2pOptimalWriteCEs; 1101 NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; 1102 NV_DECLARE_ALIGNED(NvP64 busPeerIds, 8); 1103 NV_DECLARE_ALIGNED(NvP64 busEgmPeerIds, 8); 1104 } NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS; 1105 1106 /* valid p2pCaps values */ 1107 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED 0:0 1108 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_FALSE (0x00000000U) 1109 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_TRUE (0x00000001U) 1110 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED 1:1 1111 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_FALSE (0x00000000U) 1112 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_TRUE (0x00000001U) 1113 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED 2:2 1114 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_FALSE (0x00000000U) 1115 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_TRUE (0x00000001U) 1116 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED 3:3 1117 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_FALSE (0x00000000U) 1118 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_TRUE (0x00000001U) 1119 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED 4:4 1120 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_FALSE (0x00000000U) 1121 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_TRUE (0x00000001U) 1122 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED 5:5 1123 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_FALSE (0x00000000U) 1124 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_TRUE (0x00000001U) 1125 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED 6:6 1126 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_FALSE (0x00000000U) 1127 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_TRUE (0x00000001U) 1128 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED 7:7 1129 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_FALSE (0x00000000U) 1130 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_TRUE (0x00000001U) 1131 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED 8:8 1132 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_FALSE (0x00000000U) 1133 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_TRUE (0x00000001U) 1134 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED 9:9 1135 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_FALSE (0x00000000U) 1136 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_TRUE (0x00000001U) 1137 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED 10:10 1138 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_FALSE (0x00000000U) 1139 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_TRUE (0x00000001U) 1140 1141 1142 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED 12:12 1143 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_FALSE (0x00000000U) 1144 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_TRUE (0x00000001U) 1145 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED 13:13 1146 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_FALSE (0x00000000U) 1147 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_TRUE (0x00000001U) 1148 1149 /* P2P status codes */ 1150 #define NV0000_P2P_CAPS_STATUS_OK (0x00U) 1151 #define NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED (0x01U) 1152 #define NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED (0x02U) 1153 #define NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED (0x03U) 1154 #define NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY (0x04U) 1155 #define NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED (0x05U) 1156 1157 /* 1158 * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 1159 * 1160 * This command returns peer to peer capabilities present between GPUs. 1161 * Valid requests must present a list of GPU Ids. 1162 * 1163 * [in] gpuIds 1164 * This member contains the array of GPU IDs for which we query the P2P 1165 * capabilities. Valid entries are contiguous, beginning with the first 1166 * entry in the list. 1167 * [in] gpuCount 1168 * This member contains the number of GPU IDs stored in the gpuIds[] array. 1169 * [out] p2pCaps 1170 * This member returns the peer to peer capabilities discovered between the 1171 * GPUs. Valid p2pCaps values include: 1172 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED 1173 * When this bit is set, peer to peer writes between subdevices owned 1174 * by this device are supported. 1175 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED 1176 * When this bit is set, peer to peer reads between subdevices owned 1177 * by this device are supported. 1178 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED 1179 * When this bit is set, peer to peer PROP between subdevices owned 1180 * by this device are supported. This is enabled by default 1181 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED 1182 * When this bit is set, PCI is supported for all P2P between subdevices 1183 * owned by this device. 1184 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED 1185 * When this bit is set, NVLINK is supported for all P2P between subdevices 1186 * owned by this device. 1187 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED 1188 * When this bit is set, peer to peer atomics between subdevices owned 1189 * by this device are supported. 1190 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED 1191 * When this bit is set, peer to peer loopback is supported for subdevices 1192 * owned by this device. 1193 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED 1194 * When this bit is set, indirect peer to peer writes between subdevices 1195 * owned by this device are supported. 1196 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED 1197 * When this bit is set, indirect peer to peer reads between subdevices 1198 * owned by this device are supported. 1199 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED 1200 * When this bit is set, indirect peer to peer atomics between 1201 * subdevices owned by this device are supported. 1202 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED 1203 * When this bit is set, indirect NVLINK is supported for subdevices 1204 * owned by this device. 1205 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED 1206 * When this bit is set, C2C P2P is supported between the GPUs 1207 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_BAR1_SUPPORTED 1208 * When this bit is set, BAR1 P2P is supported between the GPUs 1209 * mentioned in @ref gpuIds 1210 * [out] p2pOptimalReadCEs 1211 * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink 1212 * [out] p2pOptimalWriteCEs 1213 * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink 1214 * [out] p2pCapsStatus 1215 * This member returns status of all supported p2p capabilities. Valid 1216 * status values include: 1217 * NV0000_P2P_CAPS_STATUS_OK 1218 * P2P capability is supported. 1219 * NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED 1220 * Chipset doesn't support p2p capability. 1221 * NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED 1222 * GPU doesn't support p2p capability. 1223 * NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED 1224 * IOH topology isn't supported. For e.g. root ports are on different 1225 * IOH. 1226 * NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY 1227 * P2P Capability is disabled by a regkey. 1228 * NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED 1229 * P2P Capability is not supported. 1230 * NV0000_P2P_CAPS_STATUS_NVLINK_SETUP_FAILED 1231 * Indicates that NvLink P2P link setup failed. 1232 * [out] busPeerIds 1233 * Peer ID matrix. It is a one-dimentional array. 1234 * busPeerIds[X * gpuCount + Y] maps from index X to index Y in 1235 * the gpuIds[] table. For invalid or non-existent peer busPeerIds[] 1236 * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. 1237 * [out] busEgmPeerIds 1238 * EGM Peer ID matrix. It is a one-dimentional array. 1239 * busEgmPeerIds[X * gpuCount + Y] maps from index X to index Y in 1240 * the gpuIds[] table. For invalid or non-existent peer busEgmPeerIds[] 1241 * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. 1242 * 1243 * Possible status values returned are: 1244 * NV_OK 1245 * NV_ERR_INVALID_ARGUMENT 1246 * NV_ERR_INVALID_PARAM_STRUCT 1247 */ 1248 1249 1250 1251 #define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 (0x12bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID" */ 1252 1253 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID (0x2BU) 1254 1255 typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS { 1256 NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 1257 NvU32 gpuCount; 1258 NvU32 p2pCaps; 1259 NvU32 p2pOptimalReadCEs; 1260 NvU32 p2pOptimalWriteCEs; 1261 NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; 1262 NvU32 busPeerIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED]; 1263 NvU32 busEgmPeerIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED]; 1264 } NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS; 1265 1266 /* 1267 * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX 1268 * 1269 * This command returns peer to peer capabilities present between all pairs of 1270 * GPU IDs {(a, b) : a in gpuIdGrpA and b in gpuIdGrpB}. This can be used to 1271 * collect all P2P capabilities in the system - see the SRT: 1272 * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX_TEST 1273 * for a demonstration. 1274 * 1275 * The call will query for all pairs between set A and set B, and returns 1276 * results in both link directions. The results are two-dimensional arrays where 1277 * the first dimension is the index within the set-A array of one GPU ID under 1278 * consideration, and the second dimension is the index within the set-B array 1279 * of the other GPU ID under consideration. 1280 * 1281 * That is, the result arrays are *ALWAYS* to be indexed first with the set-A 1282 * index, then with the set-B index. The B-to-A direction of results are put in 1283 * the b2aOptimal(Read|Write)CEs. This makes it unnecessary to call the query 1284 * twice, since the usual use case requires both directions. 1285 * 1286 * If a set is being compared against itself (by setting grpBCount to 0), then 1287 * the result matrices are symmetric - it doesn't matter which index is first. 1288 * However, the choice of indices is effectively a choice of which ID is "B" and 1289 * which is "A" for the "a2b" and "b2a" directional results. 1290 * 1291 * [in] grpACount 1292 * This member contains the number of GPU IDs stored in the gpuIdGrpA[] 1293 * array. Must be >= 0. 1294 * [in] grpBCount 1295 * This member contains the number of GPU IDs stored in the gpuIdGrpB[] 1296 * array. Can be == 0 to specify a check of group A against itself. 1297 * [in] gpuIdGrpA 1298 * This member contains the array of GPU IDs in "group A", each of which 1299 * will have its P2P capabilities returned with respect to each GPU ID in 1300 * "group B". Valid entries are contiguous, beginning with the first entry 1301 * in the list. 1302 * [in] gpuIdGrpB 1303 * This member contains the array of GPU IDs in "group B", each of which 1304 * will have its P2P capabilities returned with respect to each GPU ID in 1305 * "group A". Valid entries are contiguous, beginning with the first entry 1306 * in the list. May be equal to gpuIdGrpA, but best performance requires 1307 * that the caller specifies grpBCount = 0 in this case, and ignores this. 1308 * [out] p2pCaps 1309 * This member returns the peer to peer capabilities discovered between the 1310 * pairs of input GPUs between the groups, indexed by [A_index][B_index]. 1311 * Valid p2pCaps values include: 1312 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED 1313 * When this bit is set, peer to peer writes between subdevices owned 1314 * by this device are supported. 1315 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED 1316 * When this bit is set, peer to peer reads between subdevices owned 1317 * by this device are supported. 1318 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED 1319 * When this bit is set, peer to peer PROP between subdevices owned 1320 * by this device are supported. This is enabled by default 1321 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED 1322 * When this bit is set, PCI is supported for all P2P between subdevices 1323 * owned by this device. 1324 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED 1325 * When this bit is set, NVLINK is supported for all P2P between subdevices 1326 * owned by this device. 1327 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED 1328 * When this bit is set, peer to peer atomics between subdevices owned 1329 * by this device are supported. 1330 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED 1331 * When this bit is set, peer to peer loopback is supported for subdevices 1332 * owned by this device. 1333 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED 1334 * When this bit is set, indirect peer to peer writes between subdevices 1335 * owned by this device are supported. 1336 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED 1337 * When this bit is set, indirect peer to peer reads between subdevices 1338 * owned by this device are supported. 1339 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED 1340 * When this bit is set, indirect peer to peer atomics between 1341 * subdevices owned by this device are supported. 1342 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED 1343 * When this bit is set, indirect NVLINK is supported for subdevices 1344 * owned by this device. 1345 * [out] a2bOptimalReadCes 1346 * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink 1347 * in the A-to-B direction. 1348 * [out] a2bOptimalWriteCes 1349 * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink 1350 * in the A-to-B direction. 1351 * [out] b2aOptimalReadCes 1352 * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink 1353 * in the B-to-A direction. 1354 * [out] b2aOptimalWriteCes 1355 * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink 1356 * in the B-to-A direction. 1357 * 1358 * Possible status values returned are: 1359 * NV_OK 1360 * NV_ERR_INVALID_ARGUMENT 1361 * NV_ERR_INVALID_PARAM_STRUCT 1362 */ 1363 1364 1365 1366 #define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX (0x13aU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID" */ 1367 1368 typedef NvU32 NV0000_CTRL_P2P_CAPS_MATRIX_ROW[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1369 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID (0x3AU) 1370 1371 typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS { 1372 NvU32 grpACount; 1373 NvU32 grpBCount; 1374 NvU32 gpuIdGrpA[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1375 NvU32 gpuIdGrpB[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1376 NV0000_CTRL_P2P_CAPS_MATRIX_ROW p2pCaps[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1377 NV0000_CTRL_P2P_CAPS_MATRIX_ROW a2bOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1378 NV0000_CTRL_P2P_CAPS_MATRIX_ROW a2bOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1379 NV0000_CTRL_P2P_CAPS_MATRIX_ROW b2aOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1380 NV0000_CTRL_P2P_CAPS_MATRIX_ROW b2aOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1381 } NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS; 1382 1383 /* 1384 * NV0000_CTRL_CMD_SYSTEM_GPS_CTRL 1385 * 1386 * This command is used to execute general GPS Functions, most dealing with 1387 * calling SBIOS, or retrieving cached sensor and GPS state data. 1388 * 1389 * version 1390 * This parameter specifies the version of the interface. Legal values 1391 * for this parameter are 1. 1392 * cmd 1393 * This parameter specifies the GPS API to be invoked. 1394 * Valid values for this parameter are: 1395 * NV0000_CTRL_GPS_CMD_GET_THERM_LIMIT 1396 * This command gets the temperature limit for thermal controller. When 1397 * this command is specified the input parameter contains ???. 1398 * NV0000_CTRL_GPS_CMD_SET_THERM_LIMIT 1399 * This command set the temperature limit for thermal controller. When 1400 * this command is specified the input parameter contains ???. 1401 * input 1402 * This parameter specifies the cmd-specific input value. 1403 * result 1404 * This parameter returns the cmd-specific output value. 1405 * 1406 * Possible status values returned are: 1407 * NV_OK 1408 * NV_ERR_INVALID_PARAM_STRUCT 1409 * NV_ERR_INVALID_ARGUMENT 1410 */ 1411 1412 #define NV0000_CTRL_CMD_SYSTEM_GPS_CTRL (0x12aU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID" */ 1413 1414 #define NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID (0x2AU) 1415 1416 typedef struct NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS { 1417 NvU32 cmd; 1418 NvS32 input[2]; 1419 NvS32 result[4]; 1420 } NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS; 1421 1422 /* valid version values */ 1423 #define NV0000_CTRL_GPS_PSHARE_PARAMS_PSP_CURRENT_VERSION (0x00010000U) 1424 1425 /* valid cmd values */ 1426 #define NV0000_CTRL_GPS_CMD_TYPE_GET_THERM_LIMIT (0x00000002U) 1427 #define NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000U) 1428 #define NV0000_CTRL_GPS_RESULT_THERMAL_LIMIT (0x00000000U) 1429 #define NV0000_CTRL_GPS_RESULT_MIN_LIMIT (0x00000001U) 1430 #define NV0000_CTRL_GPS_RESULT_MAX_LIMIT (0x00000002U) 1431 #define NV0000_CTRL_GPS_RESULT_LIMIT_SOURCE (0x00000003U) 1432 1433 #define NV0000_CTRL_GPS_CMD_TYPE_SET_THERM_LIMIT (0x00000003U) 1434 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1435 #define NV0000_CTRL_GPS_INPUT_THERMAL_LIMIT (0x00000001U) 1436 1437 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA (0x00000004U) 1438 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1439 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DOWN_N_DELTA (0x00000000U) 1440 1441 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA (0x00000005U) 1442 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1443 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DOWN_N_DELTA (0x00000001U) 1444 1445 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA (0x00000006U) 1446 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1447 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_HOLD_DELTA (0x00000000U) 1448 1449 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA (0x00000007U) 1450 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1451 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_HOLD_DELTA (0x00000001U) 1452 1453 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA (0x00000008U) 1454 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1455 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_UP_DELTA (0x00000000U) 1456 1457 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA (0x00000009U) 1458 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1459 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_UP_DELTA (0x00000001U) 1460 1461 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA (0x0000000AU) 1462 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1463 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_ENGAGE_DELTA (0x00000000U) 1464 1465 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA (0x0000000BU) 1466 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1467 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_ENGAGE_DELTA (0x00000001U) 1468 1469 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000CU) 1470 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1471 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) 1472 1473 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000DU) 1474 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1475 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) 1476 1477 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_STATUS (0x00000016U) 1478 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_STATUS (0x00000000U) 1479 1480 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_STATUS (0x00000017U) 1481 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_STATUS (0x00000000U) 1482 1483 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM (0x00000018U) 1484 #define NV0000_CTRL_GPS_RESULT_CPU_SET_UTIL_AVG_NUM (0x00000000U) 1485 1486 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM (0x00000019U) 1487 #define NV0000_CTRL_GPS_INPUT_CPU_GET_UTIL_AVG_NUM (0x00000000U) 1488 1489 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PERF_SENSOR (0x0000001AU) 1490 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1491 #define NV0000_CTRL_GPS_INPUT_NEXT_EXPECTED_POLL (0x00000001U) 1492 #define NV0000_CTRL_GPS_RESULT_PERF_SENSOR_VALUE (0x00000000U) 1493 #define NV0000_CTRL_GPS_RESULT_PERF_SENSOR_AVAILABLE (0x00000001U) 1494 1495 #define NV0000_CTRL_GPS_CMD_TYPE_CALL_ACPI (0x0000001BU) 1496 #define NV0000_CTRL_GPS_INPUT_ACPI_CMD (0x00000000U) 1497 #define NV0000_CTRL_GPS_INPUT_ACPI_PARAM_IN (0x00000001U) 1498 #define NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_1 (0x00000000U) 1499 #define NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_2 (0x00000001U) 1500 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_STATUS (0x00000000U) 1501 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_VERSION (0x00000001U) 1502 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_SZ (0x00000002U) 1503 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_SZ (0x00000000U) 1504 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_COUNT (0x00000001U) 1505 1506 #define NV0000_CTRL_GPS_CMD_TYPE_SET_IGPU_TURBO (0x0000001CU) 1507 #define NV0000_CTRL_GPS_INPUT_SET_IGPU_TURBO (0x00000000U) 1508 1509 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERIOD (0x00000026U) 1510 #define NV0000_CTRL_GPS_INPUT_TEMP_PERIOD (0x00000000U) 1511 1512 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERIOD (0x00000027U) 1513 #define NV0000_CTRL_GPS_RESULT_TEMP_PERIOD (0x00000000U) 1514 1515 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_NUDGE_FACTOR (0x00000028U) 1516 #define NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_UP (0x00000000U) 1517 #define NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_DOWN (0x00000001U) 1518 1519 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_NUDGE_FACTOR (0x00000029U) 1520 #define NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_UP (0x00000000U) 1521 #define NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_DOWN (0x00000001U) 1522 1523 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES (0x0000002AU) 1524 #define NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) 1525 #define NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) 1526 1527 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES (0x0000002BU) 1528 #define NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) 1529 #define NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) 1530 1531 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERF_LIMITS (0x0000002CU) 1532 #define NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_UPPER (0x00000000U) 1533 #define NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_LOWER (0x00000001U) 1534 1535 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERF_LIMITS (0x0000002DU) 1536 #define NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_UPPER (0x00000000U) 1537 #define NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_LOWER (0x00000001U) 1538 1539 #define NV0000_CTRL_GPS_CMD_TYPE_SET_PM1_AVAILABLE (0x0000002EU) 1540 #define NV0000_CTRL_GPS_INPUT_PM1_AVAILABLE (0x00000000U) 1541 1542 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PM1_AVAILABLE (0x0000002FU) 1543 #define NV0000_CTRL_GPS_OUTPUT_PM1_AVAILABLE (0x00000000U) 1544 1545 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS (0x00000044U) 1546 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) 1547 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 (0x00000001U) 1548 1549 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS (0x00000045U) 1550 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) 1551 1552 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT (0x00000046U) 1553 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ (0000000000U) 1554 1555 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT (0x00000047U) 1556 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ (0000000000U) 1557 1558 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM (0x00000048U) 1559 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_INDEX (0000000000U) 1560 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_AVAILABLE_MASK (0000000001U) 1561 1562 #define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM (0x00000049U) 1563 #define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX (0000000000U) 1564 #define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX_MAX (2U) 1565 1566 #define NV0000_CTRL_GPS_PPM_INDEX 7:0 1567 #define NV0000_CTRL_GPS_PPM_INDEX_MAXPERF (0U) 1568 #define NV0000_CTRL_GPS_PPM_INDEX_BALANCED (1U) 1569 #define NV0000_CTRL_GPS_PPM_INDEX_QUIET (2U) 1570 #define NV0000_CTRL_GPS_PPM_INDEX_INVALID (0xFFU) 1571 #define NV0000_CTRL_GPS_PPM_MASK 15:8 1572 #define NV0000_CTRL_GPS_PPM_MASK_INVALID (0U) 1573 1574 /* valid PS_STATUS result values */ 1575 #define NV0000_CTRL_GPS_CMD_PS_STATUS_OFF (0U) 1576 #define NV0000_CTRL_GPS_CMD_PS_STATUS_ON (1U) 1577 1578 1579 /* 1580 * NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS 1581 * 1582 * This command allows privileged users to update the values of 1583 * security settings governing RM behavior. 1584 * 1585 * Possible status values returned are: 1586 * NV_OK 1587 * NV_ERR_INVALID_ARGUMENT, 1588 * NV_ERR_INVALID_OBJECT_HANDLE 1589 * NV_ERR_NOT_SUPPORTED 1590 * NV_ERR_INSUFFICIENT_PERMISSIONS 1591 * 1592 * Please note: as implied above, administrator privileges are 1593 * required to modify security settings. 1594 */ 1595 #define NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS (0x129U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID" */ 1596 1597 #define GPS_MAX_COUNTERS_PER_BLOCK 32U 1598 #define NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID (0x29U) 1599 1600 typedef struct NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS { 1601 NvU32 objHndl; 1602 NvU32 blockId; 1603 NvU32 nextExpectedSampleTimems; 1604 NvU32 countersReq; 1605 NvU32 countersReturned; 1606 NvU32 counterBlock[GPS_MAX_COUNTERS_PER_BLOCK]; 1607 } NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS; 1608 1609 #define NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS (0x12cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID" */ 1610 1611 #define NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID (0x2CU) 1612 1613 typedef NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS; 1614 1615 #define NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS (0x12eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID" */ 1616 1617 #define NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID (0x2EU) 1618 1619 typedef NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS; 1620 1621 /* 1622 * NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI 1623 * 1624 * This command allows users to call GPS ACPI commands for testing purposes. 1625 * 1626 * cmd 1627 * This parameter specifies the GPS ACPI command to execute. 1628 * 1629 * input 1630 * This parameter specified the cmd-dependent input value. 1631 * 1632 * resultSz 1633 * This parameter returns the size (in bytes) of the valid data 1634 * returned in the result parameter. 1635 * 1636 * result 1637 * This parameter returns the results of the specified cmd. 1638 * The maximum size (in bytes) of this returned data will 1639 * not exceed GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 1640 * 1641 * GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 1642 * The size of buffer (result) in unit of NvU32. 1643 * The smallest value is sizeof(PSS_ENTRY)*ACPI_PSS_ENTRY_MAX. 1644 * Since the prior one is 24 bytes, and the later one is 48, 1645 * this value cannot be smaller than 288. 1646 * 1647 * Possible status values returned are: 1648 * NV_OK 1649 * NV_ERR_INVALID_ARGUMENT, 1650 * NV_ERR_INVALID_OBJECT_HANDLE 1651 * NV_ERR_NOT_SUPPORTED 1652 * NV_ERR_INSUFFICIENT_PERMISSIONS 1653 * 1654 */ 1655 #define GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U 1656 #define NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID (0x2DU) 1657 1658 typedef struct NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS { 1659 NvU32 cmd; 1660 NvU32 input; 1661 NvU32 resultSz; 1662 NvU32 result[GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE]; 1663 } NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS; 1664 1665 #define NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI (0x12dU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID" */ 1666 1667 /* 1668 * NV0000_CTRL_SYSTEM_PARAM_* 1669 * 1670 * The following is a list of system-level parameters (often sensors) that the 1671 * driver can be made aware of. They are primarily intended to be used by system 1672 * power-balancing algorithms that require system-wide visibility in order to 1673 * function. The names and values used here are established and specified in 1674 * several different NVIDIA documents that are made externally available. Thus, 1675 * updates to this list must be made with great caution. The only permissible 1676 * change is to append new parameters. Reordering is strictly prohibited. 1677 * 1678 * Brief Parameter Summary: 1679 * TGPU - GPU temperature (NvTemp) 1680 * PDTS - CPU package temperature (NvTemp) 1681 * SFAN - System fan speed (% of maximum fan speed) 1682 * SKNT - Skin temperature (NvTemp) 1683 * CPUE - CPU energy counter (NvU32) 1684 * TMP1 - Additional temperature sensor 1 (NvTemp) 1685 * TMP2 - Additional temperature sensor 2 (NvTemp) 1686 * CTGP - Mode 2 power limit offset (NvU32) 1687 * PPMD - Power mode data (NvU32) 1688 */ 1689 #define NV0000_CTRL_SYSTEM_PARAM_TGPU (0x00000000U) 1690 #define NV0000_CTRL_SYSTEM_PARAM_PDTS (0x00000001U) 1691 #define NV0000_CTRL_SYSTEM_PARAM_SFAN (0x00000002U) 1692 #define NV0000_CTRL_SYSTEM_PARAM_SKNT (0x00000003U) 1693 #define NV0000_CTRL_SYSTEM_PARAM_CPUE (0x00000004U) 1694 #define NV0000_CTRL_SYSTEM_PARAM_TMP1 (0x00000005U) 1695 #define NV0000_CTRL_SYSTEM_PARAM_TMP2 (0x00000006U) 1696 #define NV0000_CTRL_SYSTEM_PARAM_CTGP (0x00000007U) 1697 #define NV0000_CTRL_SYSTEM_PARAM_PPMD (0x00000008U) 1698 #define NV0000_CTRL_SYSTEM_PARAM_COUNT (0x00000009U) 1699 1700 /* 1701 * NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD 1702 * 1703 * This command is used to execute general ACPI methods. 1704 * 1705 * method 1706 * This parameter identifies the MXM ACPI API to be invoked. 1707 * Valid values for this parameter are: 1708 * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS 1709 * This value specifies that the DSM NVOP subfunction OPTIMUSCAPS 1710 * API is to be invoked. 1711 * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG 1712 * This value specifies that the DSM NVOP subfunction OPTIMUSFLAG 1713 * API is to be invoked. This API will set a Flag in sbios to Indicate 1714 * that HD Audio Controller is disable/Enabled from GPU Config space. 1715 * This flag will be used by sbios to restore Audio state after resuming 1716 * from s3/s4. 1717 * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS 1718 * This value specifies that the DSM JT subfunction FUNC_CAPS is to 1719 * to be invoked to get the SBIOS capabilities 1720 * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY 1721 * This value specifies that the DSM JT subfunction FUNC_PLATPOLICY is 1722 * to be invoked to set and get the various platform policies for JT. 1723 * Refer to the JT spec in more detail on various policies. 1724 * inData 1725 * This parameter specifies the method-specific input buffer. Data is 1726 * passed to the specified API using this buffer. 1727 * inDataSize 1728 * This parameter specifies the size of the inData buffer in bytes. 1729 * outStatus 1730 * This parameter returns the status code from the associated ACPI call. 1731 * outData 1732 * This parameter specifies the method-specific output buffer. Data 1733 * is returned by the specified API using this buffer. 1734 * outDataSize 1735 * This parameter specifies the size of the outData buffer in bytes. 1736 * 1737 * Possible status values returned are: 1738 * NV_OK 1739 * NV_ERR_INVALID_PARAM_STRUCT 1740 * NV_ERR_INVALID_ARGUMENT 1741 */ 1742 1743 #define NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD (0x130U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID" */ 1744 1745 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID (0x30U) 1746 1747 typedef struct NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS { 1748 NvU32 method; 1749 NV_DECLARE_ALIGNED(NvP64 inData, 8); 1750 NvU16 inDataSize; 1751 NvU32 outStatus; 1752 NV_DECLARE_ALIGNED(NvP64 outData, 8); 1753 NvU16 outDataSize; 1754 } NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS; 1755 1756 /* valid method parameter values */ 1757 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS (0x00000000U) 1758 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG (0x00000001U) 1759 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS (0x00000002U) 1760 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY (0x00000003U) 1761 /* 1762 * NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS 1763 * 1764 * This command can be used to instruct the RM to enable/disable specific module 1765 * of ETW events. 1766 * 1767 * moduleMask 1768 * This parameter specifies the module of events we would like to 1769 * enable/disable. 1770 * 1771 * Possible status values returned are: 1772 * NV_OK 1773 */ 1774 #define NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS (0x131U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID" */ 1775 1776 #define NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID (0x31U) 1777 1778 typedef struct NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS { 1779 NvU32 moduleMask; 1780 } NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS; 1781 1782 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ALL (0x00000001U) 1783 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NOFREQ (0x00000002U) 1784 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_FLUSH (0x00000004U) 1785 1786 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PERF (0x00000010U) 1787 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ELPG (0x00000020U) 1788 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVDPS (0x00000040U) 1789 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_POWER (0x00000080U) 1790 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_DISP (0x00000100U) 1791 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RMAPI (0x00000200U) 1792 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_INTR (0x00000400U) 1793 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_LOCK (0x00000800U) 1794 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RCJOURNAL (0x00001000U) 1795 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GENERIC (0x00002000U) 1796 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_THERM (0x00004000U) 1797 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GPS (0x00008000U) 1798 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PCIE (0x00010000U) 1799 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVTELEMETRY (0x00020000U) 1800 1801 /* 1802 * NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA 1803 * 1804 * This command is used to read FRL data based on need. 1805 * 1806 * nextSampleNumber 1807 * This parameter returns the counter of next sample which is being filled. 1808 * samples 1809 * This parameter returns the frame time, render time, target time, client ID 1810 * with one reserve bit for future use. 1811 * 1812 * Possible status values returned are: 1813 * NV_OK 1814 * NV_ERR_NOT_SUPPORTED 1815 */ 1816 1817 #define NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA (0x12fU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID" */ 1818 1819 #define NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE 64U 1820 1821 typedef struct NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE { 1822 NvU16 frameTime; 1823 NvU16 renderTime; 1824 NvU16 targetTime; 1825 NvU8 sleepTime; 1826 NvU8 sampleNumber; 1827 } NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE; 1828 1829 #define NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID (0x2FU) 1830 1831 typedef struct NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS { 1832 NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE samples[NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE]; 1833 NvU8 nextSampleNumber; 1834 } NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS; 1835 1836 /* 1837 * NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA 1838 * 1839 * This command is used to write FRM data based on need. 1840 * 1841 * frameTime 1842 * This parameter contains the frame time of current frame. 1843 * renderTime 1844 * This parameter contains the render time of current frame. 1845 * targetTime 1846 * This parameter contains the target time of current frame. 1847 * sleepTime 1848 * This parameter contains the sleep duration inserted by FRL for the latest frame. 1849 * 1850 * Possible status values returned are: 1851 * NV_OK 1852 * NV_ERR_NOT_SUPPORTED 1853 */ 1854 1855 #define NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA (0x132U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID" */ 1856 1857 #define NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID (0x32U) 1858 1859 typedef struct NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS { 1860 NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE sampleData; 1861 } NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS; 1862 1863 /* 1864 * NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO 1865 * 1866 * This command returns the current host driver, host OS and 1867 * plugin information. It is only valid when VGX is setup. 1868 * szHostDriverVersionBuffer 1869 * This field returns the host driver version (NV_VERSION_STRING). 1870 * szHostVersionBuffer 1871 * This field returns the host driver version (NV_BUILD_BRANCH_VERSION). 1872 * szHostTitleBuffer 1873 * This field returns the host driver title (NV_DISPLAY_DRIVER_TITLE). 1874 * szPluginTitleBuffer 1875 * This field returns the plugin build title (NV_DISPLAY_DRIVER_TITLE). 1876 * szHostUnameBuffer 1877 * This field returns the call of 'uname' on the host OS. 1878 * iHostChangelistNumber 1879 * This field returns the changelist value of the host driver (NV_BUILD_CHANGELIST_NUM). 1880 * iPluginChangelistNumber 1881 * This field returns the changelist value of the plugin (NV_BUILD_CHANGELIST_NUM). 1882 * 1883 * Possible status values returned are: 1884 * NV_OK 1885 * NV_ERR_INVALID_PARAM_STRUCT 1886 */ 1887 1888 #define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE 256U 1889 #define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO (0x133U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID" */ 1890 1891 #define NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID (0x33U) 1892 1893 typedef struct NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS { 1894 char szHostDriverVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1895 char szHostVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1896 char szHostTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1897 char szPluginTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1898 char szHostUnameBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1899 NvU32 iHostChangelistNumber; 1900 NvU32 iPluginChangelistNumber; 1901 } NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS; 1902 1903 /* 1904 * NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS 1905 * 1906 * This command returns the power status of the GPUs in the system, successfully attached or not because of 1907 * insufficient power. It is supported on Kepler and up only. 1908 * gpuCount 1909 * This field returns the count into the following arrays. 1910 * busNumber 1911 * This field returns the busNumber of a GPU. 1912 * gpuExternalPowerStatus 1913 * This field returns the corresponding external power status: 1914 * NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED 1915 * NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED 1916 * 1917 * Possible status values returned are: 1918 * NV_OK 1919 * NV_ERR_INVALID_PARAM_STRUCT 1920 * NV_ERR_NOT_SUPPORTED 1921 */ 1922 1923 #define NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS (0x134U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID" */ 1924 1925 #define NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID (0x34U) 1926 1927 typedef struct NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS { 1928 NvU8 gpuCount; 1929 NvU8 gpuBus[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 1930 NvU8 gpuExternalPowerStatus[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 1931 } NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS; 1932 1933 /* Valid gpuExternalPowerStatus values */ 1934 #define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED 0U 1935 #define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED 1U 1936 1937 /* 1938 * NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS 1939 * 1940 * This command returns the caller's API access privileges using 1941 * this client handle. 1942 * 1943 * privStatus 1944 * This parameter returns a mask of possible access privileges: 1945 * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_PRIV_USER_FLAG 1946 * The caller is running with elevated privileges 1947 * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_ROOT_HANDLE_FLAG 1948 * Client is of NV01_ROOT class. 1949 * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG 1950 * Client has PRIV bit set. 1951 * 1952 * Possible status values returned are: 1953 * NV_OK 1954 * NV_ERR_INVALID_PARAM_STRUCT 1955 */ 1956 1957 1958 #define NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS (0x135U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID" */ 1959 1960 #define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID (0x35U) 1961 1962 typedef struct NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS { 1963 NvU8 privStatusFlags; 1964 } NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS; 1965 1966 1967 /* Valid privStatus values */ 1968 #define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_USER_FLAG (0x00000001U) 1969 #define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_KERNEL_HANDLE_FLAG (0x00000002U) 1970 #define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG (0x00000004U) 1971 1972 /* 1973 * NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS 1974 * 1975 * The fabric manager (FM) notifies RM that fabric (system) is ready for peer to 1976 * peer (P2P) use or still initializing the fabric. This command allows clients 1977 * to query fabric status to allow P2P operations. 1978 * 1979 * Note, on systems where FM isn't used, RM just returns _SKIP. 1980 * 1981 * fabricStatus 1982 * This parameter returns current fabric status: 1983 * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP 1984 * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED 1985 * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS 1986 * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED 1987 * 1988 * Possible status values returned are: 1989 * NV_OK 1990 * NV_ERR_INVALID_ARGUMENT 1991 * NV_ERR_INVALID_OBJECT_HANDLE 1992 * NV_ERR_NOT_SUPPORTED 1993 * NV_ERR_INSUFFICIENT_PERMISSIONS 1994 * NV_ERR_INVALID_PARAM_STRUCT 1995 */ 1996 1997 typedef enum NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS { 1998 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP = 1, 1999 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED = 2, 2000 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS = 3, 2001 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED = 4, 2002 } NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS; 2003 2004 #define NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS (0x136U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID" */ 2005 2006 #define NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID (0x36U) 2007 2008 typedef struct NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS { 2009 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS fabricStatus; 2010 } NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS; 2011 2012 /* 2013 * NV0000_CTRL_VGPU_GET_VGPU_VERSION_INFO 2014 * 2015 * This command is used to query the range of VGX version supported. 2016 * 2017 * host_min_supported_version 2018 * The minimum vGPU version supported by host driver 2019 * host_max_supported_version 2020 * The maximum vGPU version supported by host driver 2021 * user_min_supported_version 2022 * The minimum vGPU version set by user for vGPU support 2023 * user_max_supported_version 2024 * The maximum vGPU version set by user for vGPU support 2025 * 2026 * Possible status values returned are: 2027 * NV_OK 2028 * NV_ERR_INVALID_REQUEST 2029 */ 2030 #define NV0000_CTRL_VGPU_GET_VGPU_VERSION (0x137U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID" */ 2031 2032 /* 2033 * NV0000_CTRL_VGPU_GET_VGPU_VERSION 2034 */ 2035 #define NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID (0x37U) 2036 2037 typedef struct NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS { 2038 NvU32 host_min_supported_version; 2039 NvU32 host_max_supported_version; 2040 NvU32 user_min_supported_version; 2041 NvU32 user_max_supported_version; 2042 } NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS; 2043 2044 /* 2045 * NV0000_CTRL_VGPU_SET_VGPU_VERSION 2046 * 2047 * This command is used to query whether pGPU is live migration capable or not. 2048 * 2049 * min_version 2050 * The minimum vGPU version to be supported being set 2051 * max_version 2052 * The maximum vGPU version to be supported being set 2053 * 2054 * Possible status values returned are: 2055 * NV_OK 2056 * NV_ERR_INVALID_REQUEST 2057 */ 2058 #define NV0000_CTRL_VGPU_SET_VGPU_VERSION (0x138U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID" */ 2059 2060 /* 2061 * NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS 2062 */ 2063 #define NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID (0x38U) 2064 2065 typedef struct NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS { 2066 NvU32 min_version; 2067 NvU32 max_version; 2068 } NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS; 2069 2070 /* 2071 * NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID 2072 * 2073 * This command is used to get a unique identifier for the instance of RM. 2074 * The returned value will only change when the driver is reloaded. A previous 2075 * value will never be reused on a given machine. 2076 * 2077 * rm_instance_id; 2078 * The instance ID of the current RM instance 2079 * 2080 * Possible status values returned are: 2081 * NV_OK 2082 */ 2083 #define NV0000_CTRL_CMD_SYSTEM_GET_RM_INSTANCE_ID (0x139U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID" */ 2084 2085 /* 2086 * NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS 2087 */ 2088 #define NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID (0x39U) 2089 2090 typedef struct NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS { 2091 NV_DECLARE_ALIGNED(NvU64 rm_instance_id, 8); 2092 } NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS; 2093 2094 /* 2095 * NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO 2096 * 2097 * This API is used to get the TPP(total processing power) and 2098 * the rated TGP(total GPU power) from SBIOS. 2099 * 2100 * NVPCF is an acronym for Nvidia Platform Controllers and Framework 2101 * which implements platform level policies. NVPCF is implemented in 2102 * a kernel driver on windows. It is implemented in a user mode app 2103 * called nvidia-powerd on Linux. 2104 * 2105 * Valid subFunc ids for NVPCF 1x include : 2106 * NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED 2107 * NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS 2108 * 2109 * Valid subFunc ids for NVPCF 2x include : 2110 * NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED 2111 * NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS 2112 * NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES 2113 * 2114 * Possible status values returned are: 2115 * NV_OK 2116 * NV_ERR_INVALID_REQUEST 2117 * NV_ERR_NOT_SUPPORTED 2118 */ 2119 #define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO (0x13bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID" */ 2120 #define NVPCF_CTRL_SYSPWRLIMIT_TYPE_BASE 1U 2121 #define NV0000_CTRL_SYSTEM_POWER_INFO_INDEX_MAX_SIZE 32U 2122 2123 #define NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT_MESSAGE_ID (0x48U) 2124 2125 typedef struct NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT { 2126 2127 /* Battery state of charge threshold (percent 0-100) */ 2128 NvU8 batteryStateOfChargePercent; 2129 2130 /* Long Timescale Battery current limit (milliamps) */ 2131 NvU32 batteryCurrentLimitmA; 2132 2133 /* Rest of system reserved power (milliwatts) */ 2134 NvU32 restOfSytemReservedPowermW; 2135 2136 /* Min CPU TDP (milliwatts) */ 2137 NvU32 minCpuTdpmW; 2138 2139 /* Max CPU TDP (milliwatts) */ 2140 NvU32 maxCpuTdpmW; 2141 2142 /* Short Timescale Battery current limit (milliamps) */ 2143 NvU32 shortTimescaleBatteryCurrentLimitmA; 2144 } NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT; 2145 2146 #define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID (0x3BU) 2147 2148 typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS { 2149 /* GPU ID */ 2150 NvU32 gpuId; 2151 2152 /* Total processing power including CPU and GPU */ 2153 NvU32 tpp; 2154 2155 /* Rated total GPU Power */ 2156 NvU32 ratedTgp; 2157 2158 /* NVPCF subfunction id */ 2159 NvU32 subFunc; 2160 2161 /* Configurable TGP offset, in mW */ 2162 NvS32 ctgpOffsetmW; 2163 2164 /* TPP, as offset in mW */ 2165 NvS32 targetTppOffsetmW; 2166 2167 /* Maximum allowed output, as offset in mW */ 2168 NvS32 maxOutputOffsetmW; 2169 2170 /* Minimum allowed output, as offset in mW */ 2171 NvS32 minOutputOffsetmW; 2172 2173 /* Configurable TGP offset, on battery, in milli-Watts. */ 2174 NvS32 ctgpBattOffsetmW; 2175 2176 /* Target total processing power on battery, offset, in milli-Watts. */ 2177 NvS32 targetTppBattOffsetmW; 2178 2179 /* 2180 * If value specified is larger than the statically assigned ROS reserve in 2181 * the system power limits table, this will take affect. 2182 * 2183 * A value of zero naturally works as a clear as it will be lesser than the 2184 * statically assigned value. 2185 */ 2186 NvU32 dcRosReserveOverridemW; 2187 2188 /* 2189 * This is the active arbitrated long timescale limit provided by Qboost and 2190 * honored by JPAC/JPPC 2191 */ 2192 NvU32 dcTspLongTimescaleLimitmA; 2193 2194 /* 2195 * This is the active arbitrated short timescale limit provided by Qboost and 2196 * honored by RM/PMU 2197 */ 2198 NvU32 dcTspShortTimescaleLimitmA; 2199 2200 /* Require DB on DC to use system power limits table */ 2201 NvBool bRequireDcSysPowerLimitsTable; 2202 2203 /* Dynamic params can override ROS reserve used in DB-DC */ 2204 NvBool bAllowDcRestOfSystemReserveOverride; 2205 2206 /* Is DC-TSP supported? */ 2207 NvBool bSupportDcTsp; 2208 2209 /* Dynamic Boost AC support */ 2210 NvBool bEnableForAC; 2211 2212 /* Dynamic Boost DC support */ 2213 NvBool bEnableForDC; 2214 2215 /* The System Controller Table Version */ 2216 NvU8 version; 2217 2218 /* Base sampling period */ 2219 NvU16 samplingPeriodmS; 2220 2221 /* Sampling Multiplier */ 2222 NvU16 samplingMulti; 2223 2224 /* Fitler function type */ 2225 NvU8 filterType; 2226 2227 union { 2228 2229 /* weight */ 2230 NvU8 weight; 2231 2232 /* windowSize */ 2233 NvU8 windowSize; 2234 } filterParam; 2235 2236 /* Reserved */ 2237 NvU16 filterReserved; 2238 2239 /* Controller Type Dynamic Boost Controller */ 2240 NvBool bIsBoostController; 2241 2242 /* Increase power limit ratio */ 2243 NvU16 incRatio; 2244 2245 /* Decrease power limit ratio */ 2246 NvU16 decRatio; 2247 2248 /* Dynamic Boost Controller DC Support */ 2249 NvBool bSupportBatt; 2250 2251 /* CPU type(Intel/AMD) */ 2252 NvU8 cpuType; 2253 2254 /* GPU type(Nvidia) */ 2255 NvU8 gpuType; 2256 2257 /* System Power Table info index */ 2258 NvU32 sysPwrIndex; 2259 2260 /* System Power Table get table limits */ 2261 NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT sysPwrGetInfo[NV0000_CTRL_SYSTEM_POWER_INFO_INDEX_MAX_SIZE]; 2262 2263 /* 2264 * Does this version of the system power limits table support TSP -> table 2265 * version 2.0 and later should set this to true 2266 */ 2267 NvBool bIsTspSupported; 2268 2269 /* 2270 * Stores the System Power Limits (Battery State of Charge aka BSOC) table version implemented by the SBIOS 2271 * 2272 */ 2273 NvU8 sysPwrLimitsTableVersion; 2274 2275 /* SYSPWRLIMIT class types */ 2276 NvU32 type; 2277 2278 /* CPU TDP Limit to be set (milliwatts) */ 2279 NvU32 cpuTdpmw; 2280 } NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS; 2281 2282 /* Define the filter types */ 2283 #define CONTROLLER_FILTER_TYPE_EMWA 0U 2284 #define CONTROLLER_FILTER_TYPE_MOVING_MAX 1U 2285 2286 /* Valid NVPCF subfunction case */ 2287 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE 2U 2288 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE 3U 2289 2290 /* NVPCF subfunction to get the static data tables */ 2291 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CASE 4U 2292 2293 /* NVPCF subfunction to get the system power limits table */ 2294 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DC_SYSTEM_POWER_LIMITS_CASE 5U 2295 2296 /* NVPCF subfunction to change the CPU's TDP limit */ 2297 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_CPU_TDP_LIMIT_CONTROL_CASE 6U 2298 2299 /* Valid NVPCF subfunction ids */ 2300 #define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED (0x00000000) 2301 #define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS (0x00000002) 2302 2303 /* 2304 * Defines for get supported sub functions bit fields 2305 */ 2306 #define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED 0:0 2307 #define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES 1 2308 #define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO 0 2309 2310 /*! 2311 * Config DSM 2x version specific defines 2312 */ 2313 #define NVPCF0100_CTRL_CONFIG_DSM_2X_VERSION (0x00000200) 2314 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED (0x00000000) 2315 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES (0x00000001) 2316 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS (0x00000002) 2317 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DC_SYSTEM_POWER_LIMITS_TABLE (0x00000008) 2318 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_CPU_TDP_LIMIT_CONTROL (0x00000009) 2319 2320 /*! 2321 * Defines the max buffer size for config 2322 */ 2323 #define NVPCF0100_CTRL_CONFIG_2X_BUFF_SIZE_MAX (255) 2324 2325 /* 2326 * NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT 2327 * 2328 * This API is used to sync the external fabric management status with 2329 * GSP-RM 2330 * 2331 * bExternalFabricMgmt 2332 * Whether fabric is externally managed 2333 * 2334 * Possible status values returned are: 2335 * NV_OK 2336 */ 2337 #define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT (0x13cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID" */ 2338 2339 #define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID (0x3CU) 2340 2341 typedef struct NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS { 2342 NvBool bExternalFabricMgmt; 2343 } NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS; 2344 2345 /* 2346 * NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO 2347 * 2348 * This API is used to get information about the RM client 2349 * database. 2350 * 2351 * clientCount [OUT] 2352 * This field indicates the number of clients currently allocated. 2353 * 2354 * resourceCount [OUT] 2355 * This field indicates the number of resources currently allocated 2356 * across all clients. 2357 * 2358 */ 2359 #define NV0000_CTRL_CMD_SYSTEM_GET_CLIENT_DATABASE_INFO (0x13dU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID" */ 2360 2361 #define NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID (0x3DU) 2362 2363 typedef struct NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS { 2364 NvU32 clientCount; 2365 NV_DECLARE_ALIGNED(NvU64 resourceCount, 8); 2366 } NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS; 2367 2368 /* 2369 * NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 2370 * 2371 * This command returns the current driver information in 2372 * statically sized character arrays. 2373 * 2374 * driverVersionBuffer 2375 * This field returns the version (NV_VERSION_STRING). 2376 * versionBuffer 2377 * This field returns the version (NV_BUILD_BRANCH_VERSION). 2378 * driverBranch 2379 * This field returns the branch (NV_BUILD_BRANCH). 2380 * titleBuffer 2381 * This field returns the title (NV_DISPLAY_DRIVER_TITLE). 2382 * changelistNumber 2383 * This field returns the changelist value (NV_BUILD_CHANGELIST_NUM). 2384 * officialChangelistNumber 2385 * This field returns the last official changelist value 2386 * (NV_LAST_OFFICIAL_CHANGELIST_NUM). 2387 * 2388 * Possible status values returned are: 2389 * NV_OK 2390 */ 2391 2392 #define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE 256U 2393 #define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 (0x13eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID" */ 2394 2395 #define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID (0x3EU) 2396 2397 typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS { 2398 char driverVersionBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; 2399 char versionBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; 2400 char driverBranch[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; 2401 char titleBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; 2402 NvU32 changelistNumber; 2403 NvU32 officialChangelistNumber; 2404 } NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS; 2405 2406 /* 2407 * NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL 2408 * 2409 * This API is used to get/set RMCTRL cache mode 2410 * 2411 * cmd [IN] 2412 * GET - Gets RMCTRL cache mode 2413 * SET - Sets RMCTRL cache mode 2414 * 2415 * mode [IN/OUT] 2416 * On GET, this field is the output of current RMCTRL cache mode 2417 * On SET, this field indicates the mode to set RMCTRL cache to 2418 * Valid values for this parameter are: 2419 * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE 2420 * No get/set action to cache. 2421 * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE 2422 * Try to get from cache at the beginning of the control. 2423 * Set cache after control finished if the control has not been cached. 2424 * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY 2425 * Do not get from cache. Set cache when control call finished. 2426 * When setting the cache, verify the value in the cache is the same 2427 * with the current control value if the control is already cached. 2428 * 2429 * Possible status values returned are: 2430 * NV_OK 2431 * NV_ERR_INVALID_ARGUMENT 2432 */ 2433 #define NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL (0x13fU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID" */ 2434 2435 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID (0x3FU) 2436 2437 typedef struct NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS { 2438 NvU32 cmd; 2439 NvU32 mode; 2440 } NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS; 2441 2442 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_GET (0x00000000U) 2443 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_SET (0x00000001U) 2444 2445 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE (0x00000000U) 2446 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE (0x00000001U) 2447 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY (0x00000002U) 2448 2449 /* 2450 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL 2451 * 2452 * This command is used to control PFM_REQ_HNDLR functionality. It allows control of 2453 * GPU Performance Scaling (PFM_REQ_HNDLR), changing its operational parameters and read 2454 * most PFM_REQ_HNDLR dynamic parameters. 2455 * 2456 * command 2457 * This parameter specifies the command to execute. Invalid commands 2458 * result in the return of an NV_ERR_INVALID_ARGUMENT status. 2459 * locale 2460 * This parameter indicates the specific locale to which the command 2461 * 'command' is to be applied. 2462 * Supported range of CPU/GPU {i = 0, ..., 255} 2463 * data 2464 * This parameter contains a command-specific data payload. It can 2465 * be used to input data as well as output data. 2466 * 2467 * Possible status values returned are: 2468 * NV_OK 2469 * NV_ERR_INVALID_COMMAND 2470 * NV_ERR_INVALID_STATE 2471 * NV_ERR_INVALID_DATA 2472 * NV_ERR_INVALID_REQUEST 2473 * NV_ERR_NOT_SUPPORTED 2474 */ 2475 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL (0x140U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID" */ 2476 2477 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID (0x40U) 2478 2479 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS { 2480 NvU16 command; 2481 NvU16 locale; 2482 NvU32 data; 2483 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS; 2484 2485 /* 2486 * Valid command values : 2487 * 2488 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT 2489 * Is used to check if PFM_REQ_HNDLR was correctly initialized. 2490 * Possible return (OUT) values are: 2491 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO 2492 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES 2493 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC 2494 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC 2495 * Are used to stop/start PFM_REQ_HNDLR functionality and to get current status. 2496 * Possible IN/OUT values are: 2497 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP 2498 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START 2499 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS 2500 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS 2501 * Are used to control execution of PFM_REQ_HNDLR actions and to get current status. 2502 * Possible IN/OUT values are: 2503 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF 2504 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON 2505 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC 2506 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC 2507 * Are used to switch current PFM_REQ_HNDLR logic and to retrieve current logic. 2508 * Possible IN/OUT values are: 2509 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF 2510 * Will cause that all PFM_REQ_HNDLR actions will be NULL. 2511 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY 2512 * Fuzzy logic will determine PFM_REQ_HNDLR actions based on current ruleset. 2513 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC 2514 * Deterministic logic will define PFM_REQ_HNDLR actions based on current ruleset. 2515 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE 2516 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE 2517 * Are used to set/retrieve system control preference. 2518 * Possible IN/OUT values are: 2519 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU 2520 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU 2521 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH 2522 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT 2523 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT 2524 * Are used to set/retrieve GPU2CPU pstate limits. 2525 * IN/OUT values are four bytes packed into a 32-bit data field. 2526 * The CPU cap index for GPU pstate 0 is in the lowest byte, the CPU cap 2527 * index for the GPU pstate 3 is in the highest byte, etc. One 2528 * special value is to disable the override to the GPU2CPU map: 2529 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE 2530 * Is used to stop/start PFM_REQ_HNDLR PMU functionality. 2531 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE 2532 * Is used to get the current status of PMU PFM_REQ_HNDLR. 2533 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE 2534 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER 2535 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER 2536 * Are used to set/retrieve max power [mW] that system can provide. 2537 * This is hardcoded PFM_REQ_HNDLR safety feature and logic/rules does not apply 2538 * to this threshold. 2539 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET 2540 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET 2541 * Are used to set/retrieve current system cooling budget [mW]. 2542 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD 2543 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD 2544 * Are used to set/retrieve integration interval [sec]. 2545 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET 2546 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET 2547 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT 2548 * Are used to set/retrieve used ruleset [#]. Value is checked 2549 * against MAX number of rules for currently used PFM_REQ_HNDLR logic. Also COUNT 2550 * provides a way to find out how many rules exist for the current control 2551 * system. 2552 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST 2553 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST 2554 * Is used to set/get a delay relative to now during which to allow unbound 2555 * CPU performance. Units are seconds. 2556 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE 2557 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE 2558 * Is used to override/get the actual power supply mode (AC/Battery). 2559 * Possible IN/OUT values are: 2560 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL 2561 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC 2562 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT 2563 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO 2564 * Is used to get the Ventura system information for VCT tool 2565 * Returned 32bit value should be treated as bitmask and decoded in 2566 * following way: 2567 * Encoding details are defined in objPFM_REQ_HNDLR.h refer to 2568 * NV_PFM_REQ_HNDLR_SYS_SUPPORT_INFO and corresponding bit defines. 2569 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTION 2570 * Is used to get the supported sub-functions defined in SBIOS. Returned 2571 * value is a bitmask where each bit corresponds to different function: 2572 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT 2573 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS 2574 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS 2575 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC 2576 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC 2577 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB 2578 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS 2579 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER 2580 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA 2581 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE 2582 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG 2583 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL 2584 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN 2585 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE 2586 * Are used to retrieve appropriate power measurements and their derivatives 2587 * in [mW] for required locale. _BURDEN is defined only for _LOCALE_SYSTEM. 2588 * _INTERMEDIATE is not defined for _LOCALE_SYSTEM, and takes an In value as 2589 * index. 2590 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS 2591 * Is used to retrieve parameters when adjusting raw sensor power reading. 2592 * The values may come from SBIOS, VBIOS, registry or driver default. 2593 * Possible IN value is the index of interested parameter. 2594 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP 2595 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA 2596 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE 2597 * Are used to retrieve appropriate temperature measurements and their 2598 * derivatives in [1/1000 Celsius]. 2599 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE 2600 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP 2601 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN 2602 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX 2603 * Are used to retrieve CPU(x)/GPU(x) p-state or it's limits. 2604 * Not applicable to _LOCALE_SYSTEM. 2605 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION 2606 * Is used to retrieve last PFM_REQ_HNDLR action for given domain. 2607 * Not applicable to _LOCALE_SYSTEM. 2608 * Possible return (OUT) values are: 2609 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 2610 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 2611 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING 2612 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT 2613 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 2614 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 2615 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM 2616 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM 2617 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE 2618 * Is used to set the power sensor simulator state. 2619 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE 2620 * Is used to get the power simulator sensor simulator state. 2621 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA 2622 * Is used to set power sensor simulator data 2623 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA 2624 * Is used to get power sensor simulator data 2625 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK 2626 * Is used to respond to the ACPI event triggered by SBIOS. RM will 2627 * request value for budget and status, validate them, apply them 2628 * and send ACK back to SBIOS. 2629 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT 2630 * Is a test cmd that should notify SBIOS to send ACPI event requesting 2631 * budget and status change. 2632 */ 2633 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_INVALID (0xFFFFU) 2634 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT (0x0000U) 2635 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC (0x0001U) 2636 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC (0x0002U) 2637 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS (0x0003U) 2638 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS (0x0004U) 2639 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC (0x0005U) 2640 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC (0x0006U) 2641 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE (0x0007U) 2642 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE (0x0008U) 2643 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT (0x0009U) 2644 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT (0x000AU) 2645 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE (0x000BU) 2646 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE (0x000CU) 2647 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER (0x0100U) 2648 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER (0x0101U) 2649 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET (0x0102U) 2650 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET (0x0103U) 2651 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD (0x0104U) 2652 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD (0x0105U) 2653 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET (0x0106U) 2654 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET (0x0107U) 2655 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT (0x0108U) 2656 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST (0x0109U) 2657 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST (0x010AU) 2658 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE (0x010BU) 2659 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE (0x010CU) 2660 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO (0x010DU) 2661 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTIONS (0x010EU) 2662 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER (0x0200U) 2663 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA (0x0201U) 2664 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE (0x0202U) 2665 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG (0x0203U) 2666 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL (0x0204U) 2667 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN (0x0205U) 2668 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE (0x0206U) 2669 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS (0x0210U) 2670 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP (0x0220U) 2671 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA (0x0221U) 2672 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE (0x0222U) 2673 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE (0x0240U) 2674 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP (0x0241U) 2675 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN (0x0242U) 2676 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX (0x0243U) 2677 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION (0x0244U) 2678 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_SLFM_PRESENT (0x0245U) 2679 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE (0x0250U) 2680 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE (0x0251U) 2681 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA (0x0252U) 2682 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA (0x0253U) 2683 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK (0x0320U) 2684 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT (0x0321U) 2685 2686 /* valid LOCALE values */ 2687 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_INVALID (0xFFFFU) 2688 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_SYSTEM (0x0000U) 2689 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_CPU(i) (0x0100+((i)%0x100)) 2690 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_GPU(i) (0x0200+((i)%0x100)) 2691 2692 /* valid data values for enums */ 2693 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID (0x80000000U) 2694 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO (0x00000000U) 2695 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES (0x00000001U) 2696 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP (0x00000000U) 2697 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START (0x00000001U) 2698 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF (0x00000000U) 2699 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON (0x00000001U) 2700 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF (0x00000000U) 2701 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY (0x00000001U) 2702 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC (0x00000002U) 2703 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU (0x00000000U) 2704 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU (0x00000001U) 2705 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH (0x00000002U) 2706 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE (0xFFFFFFFFU) 2707 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_OFF (0x00000000U) 2708 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_ON (0x00000001U) 2709 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL (0x00000000U) 2710 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC (0x00000001U) 2711 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT (0x00000002U) 2712 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT (0x00000001U) 2713 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS (0x00000002U) 2714 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS (0x00000004U) 2715 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC (0x00000008U) 2716 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC (0x00000010U) 2717 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB (0x00000020U) 2718 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS (0x00000040U) 2719 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 (0x00000000U) 2720 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 (0x00000001U) 2721 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING (0x00000002U) 2722 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT (0x00000003U) 2723 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 (0x00000004U) 2724 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 (0x00000005U) 2725 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM (0x00000006U) 2726 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM (0x00000007U) 2727 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_NO (0x00000000U) 2728 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_YES (0x00000001U) 2729 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_OFF (0x00000000U) 2730 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_ON (0x00000001U) 2731 2732 /* 2733 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL 2734 * 2735 * This command allows execution of multiple PFM_REQ_HNDLRControl commands within one 2736 * RmControl call. For practical reasons # of commands is limited to 16. 2737 * This command shares defines with NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL. 2738 * 2739 * cmdCount 2740 * Number of commands that should be executed. 2741 * Less or equal to NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX. 2742 * 2743 * succeeded 2744 * Number of commands that were succesully executed. 2745 * Less or equal to NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX. 2746 * Failing commands return NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID 2747 * in their data field. 2748 * 2749 * cmdData 2750 * Array of commands with following structure: 2751 * command 2752 * This parameter specifies the command to execute. 2753 * Invalid commands result in the return of an 2754 * NV_ERR_INVALID_ARGUMENT status. 2755 * locale 2756 * This parameter indicates the specific locale to which 2757 * the command 'command' is to be applied. 2758 * Supported range of CPU/GPU {i = 0, ..., 255} 2759 * data 2760 * This parameter contains a command-specific data payload. 2761 * It is used both to input data as well as to output data. 2762 * 2763 * Possible status values returned are: 2764 * NV_OK 2765 * NV_ERR_INVALID_REQUEST 2766 * NV_ERR_NOT_SUPPORTED 2767 */ 2768 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL (0x141U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID" */ 2769 2770 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX (16U) 2771 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID (0x41U) 2772 2773 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS { 2774 NvU32 cmdCount; 2775 NvU32 succeeded; 2776 2777 struct { 2778 NvU16 command; 2779 NvU16 locale; 2780 NvU32 data; 2781 } cmdData[NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX]; 2782 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS; 2783 2784 /* 2785 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL 2786 * 2787 * This command is used to execute general PFM_REQ_HNDLR Functions, most dealing with 2788 * calling SBIOS, or retrieving cached sensor and PFM_REQ_HNDLR state data. 2789 * 2790 * version 2791 * This parameter specifies the version of the interface. Legal values 2792 * for this parameter are 1. 2793 * cmd 2794 * This parameter specifies the PFM_REQ_HNDLR API to be invoked. 2795 * Valid values for this parameter are: 2796 * NV0000_CTRL_PFM_REQ_HNDLR_CMD_GET_THERM_LIMIT 2797 * This command gets the temperature limit for thermal controller. When 2798 * this command is specified the input parameter contains ???. 2799 * NV0000_CTRL_PFM_REQ_HNDLR_CMD_SET_THERM_LIMIT 2800 * This command set the temperature limit for thermal controller. When 2801 * this command is specified the input parameter contains ???. 2802 * input 2803 * This parameter specifies the cmd-specific input value. 2804 * result 2805 * This parameter returns the cmd-specific output value. 2806 * 2807 * Possible status values returned are: 2808 * NV_OK 2809 * NV_ERR_INVALID_PARAM_STRUCT 2810 * NV_ERR_INVALID_ARGUMENT 2811 */ 2812 2813 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL (0x142U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID" */ 2814 2815 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID (0x42U) 2816 2817 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS { 2818 NvU32 cmd; 2819 NvS32 input[2]; 2820 NvS32 result[4]; 2821 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS; 2822 2823 /* valid version values */ 2824 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_PSP_CURRENT_VERSION (0x00010000U) 2825 2826 /* valid cmd values */ 2827 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_THERM_LIMIT (0x00000002U) 2828 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000U) 2829 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_THERMAL_LIMIT (0x00000000U) 2830 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MIN_LIMIT (0x00000001U) 2831 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MAX_LIMIT (0x00000002U) 2832 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE (0x00000003U) 2833 2834 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_THERM_LIMIT (0x00000003U) 2835 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2836 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_THERMAL_LIMIT (0x00000001U) 2837 2838 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA (0x00000004U) 2839 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2840 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DOWN_N_DELTA (0x00000000U) 2841 2842 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA (0x00000005U) 2843 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2844 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DOWN_N_DELTA (0x00000001U) 2845 2846 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA (0x00000006U) 2847 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2848 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_HOLD_DELTA (0x00000000U) 2849 2850 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA (0x00000007U) 2851 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2852 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_HOLD_DELTA (0x00000001U) 2853 2854 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA (0x00000008U) 2855 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2856 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_UP_DELTA (0x00000000U) 2857 2858 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA (0x00000009U) 2859 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2860 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_UP_DELTA (0x00000001U) 2861 2862 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA (0x0000000AU) 2863 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2864 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_ENGAGE_DELTA (0x00000000U) 2865 2866 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA (0x0000000BU) 2867 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2868 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_ENGAGE_DELTA (0x00000001U) 2869 2870 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000CU) 2871 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2872 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) 2873 2874 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000DU) 2875 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2876 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) 2877 2878 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_STATUS (0x00000016U) 2879 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_STATUS (0x00000000U) 2880 2881 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_STATUS (0x00000017U) 2882 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_STATUS (0x00000000U) 2883 2884 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM (0x00000018U) 2885 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_CPU_SET_UTIL_AVG_NUM (0x00000000U) 2886 2887 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM (0x00000019U) 2888 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_CPU_GET_UTIL_AVG_NUM (0x00000000U) 2889 2890 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PERF_SENSOR (0x0000001AU) 2891 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2892 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_NEXT_EXPECTED_POLL (0x00000001U) 2893 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_VALUE (0x00000000U) 2894 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_AVAILABLE (0x00000001U) 2895 2896 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_CALL_ACPI (0x0000001BU) 2897 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_CMD (0x00000000U) 2898 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_PARAM_IN (0x00000001U) 2899 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_1 (0x00000000U) 2900 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_2 (0x00000001U) 2901 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_STATUS (0x00000000U) 2902 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_VERSION (0x00000001U) 2903 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_SZ (0x00000002U) 2904 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_SZ (0x00000000U) 2905 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_COUNT (0x00000001U) 2906 2907 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_IGPU_TURBO (0x0000001CU) 2908 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SET_IGPU_TURBO (0x00000000U) 2909 2910 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERIOD (0x00000026U) 2911 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERIOD (0x00000000U) 2912 2913 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERIOD (0x00000027U) 2914 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERIOD (0x00000000U) 2915 2916 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_NUDGE_FACTOR (0x00000028U) 2917 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_UP (0x00000000U) 2918 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_DOWN (0x00000001U) 2919 2920 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_NUDGE_FACTOR (0x00000029U) 2921 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_UP (0x00000000U) 2922 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_DOWN (0x00000001U) 2923 2924 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES (0x0000002AU) 2925 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) 2926 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) 2927 2928 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES (0x0000002BU) 2929 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) 2930 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) 2931 2932 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERF_LIMITS (0x0000002CU) 2933 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_UPPER (0x00000000U) 2934 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_LOWER (0x00000001U) 2935 2936 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERF_LIMITS (0x0000002DU) 2937 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_UPPER (0x00000000U) 2938 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_LOWER (0x00000001U) 2939 2940 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PM1_AVAILABLE (0x0000002EU) 2941 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_PM1_AVAILABLE (0x00000000U) 2942 2943 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PM1_AVAILABLE (0x0000002FU) 2944 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE (0x00000000U) 2945 2946 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS (0x00000044U) 2947 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) 2948 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 (0x00000001U) 2949 2950 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS (0x00000045U) 2951 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) 2952 2953 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT (0x00000046U) 2954 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ (0000000000U) 2955 2956 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT (0x00000047U) 2957 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ (0000000000U) 2958 2959 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM (0x00000048U) 2960 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_INDEX (0000000000U) 2961 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_AVAILABLE_MASK (0000000001U) 2962 2963 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM (0x00000049U) 2964 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX (0000000000U) 2965 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX_MAX (2U) 2966 2967 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX 7:0 2968 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_MAXPERF (0U) 2969 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_BALANCED (1U) 2970 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_QUIET (2U) 2971 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID (0xFFU) 2972 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK 15:8 2973 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK_INVALID (0U) 2974 2975 /* valid PS_STATUS result values */ 2976 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_OFF (0U) 2977 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_ON (1U) 2978 2979 #define PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK 32U 2980 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS { 2981 NvU32 objHndl; 2982 NvU32 blockId; 2983 NvU32 nextExpectedSampleTimems; 2984 NvU32 countersReq; 2985 NvU32 countersReturned; 2986 NvU32 counterBlock[PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK]; 2987 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS; 2988 2989 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS (0x146U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID" */ 2990 2991 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID (0x46U) 2992 2993 typedef NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS; 2994 2995 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS (0x147U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID" */ 2996 2997 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID (0x47U) 2998 2999 typedef NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS; 3000 3001 /* 3002 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI 3003 * 3004 * This command allows users to call PFM_REQ_HNDLR ACPI commands for testing purposes. 3005 * 3006 * cmd 3007 * This parameter specifies the PFM_REQ_HNDLR ACPI command to execute. 3008 * 3009 * input 3010 * This parameter specified the cmd-dependent input value. 3011 * 3012 * resultSz 3013 * This parameter returns the size (in bytes) of the valid data 3014 * returned in the result parameter. 3015 * 3016 * result 3017 * This parameter returns the results of the specified cmd. 3018 * The maximum size (in bytes) of this returned data will 3019 * not exceed PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 3020 * 3021 * PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 3022 * The size of buffer (result) in unit of NvU32. 3023 * The smallest value is sizeof(PSS_ENTRY)*ACPI_PSS_ENTRY_MAX. 3024 * Since the prior one is 24 bytes, and the later one is 48, 3025 * this value cannot be smaller than 288. 3026 * 3027 * Possible status values returned are: 3028 * NV_OK 3029 * NV_ERR_INVALID_ARGUMENT, 3030 * NV_ERR_INVALID_OBJECT_HANDLE 3031 * NV_ERR_NOT_SUPPORTED 3032 * NV_ERR_INSUFFICIENT_PERMISSIONS 3033 * 3034 */ 3035 #define PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U 3036 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID (0x43U) 3037 3038 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS { 3039 NvU32 cmd; 3040 NvU32 input; 3041 NvU32 resultSz; 3042 NvU32 result[PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE]; 3043 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS; 3044 3045 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI (0x143U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID" */ 3046 3047 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PFM_REQ_HNDLR (0x00008000U) 3048 3049 /* 3050 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA 3051 * 3052 * This command is used to read FRL data based on need. 3053 * 3054 * nextSampleNumber 3055 * This parameter returns the counter of next sample which is being filled. 3056 * samples 3057 * This parameter returns the frame time, render time, target time, client ID 3058 * with one reserve bit for future use. 3059 * 3060 * Possible status values returned are: 3061 * NV_OK 3062 * NV_ERR_NOT_SUPPORTED 3063 */ 3064 3065 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA (0x144U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID" */ 3066 3067 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE 64U 3068 3069 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE { 3070 NvU16 frameTime; 3071 NvU16 renderTime; 3072 NvU16 targetTime; 3073 NvU8 sleepTime; 3074 NvU8 sampleNumber; 3075 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE; 3076 3077 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID (0x44U) 3078 3079 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS { 3080 NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE samples[NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE]; 3081 NvU8 nextSampleNumber; 3082 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS; 3083 3084 /* 3085 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA 3086 * 3087 * This command is used to write FRM data based on need. 3088 * 3089 * frameTime 3090 * This parameter contains the frame time of current frame. 3091 * renderTime 3092 * This parameter contains the render time of current frame. 3093 * targetTime 3094 * This parameter contains the target time of current frame. 3095 * sleepTime 3096 * This parameter contains the sleep duration inserted by FRL for the latest frame. 3097 * 3098 * Possible status values returned are: 3099 * NV_OK 3100 * NV_ERR_NOT_SUPPORTED 3101 */ 3102 3103 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA (0x145U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID" */ 3104 3105 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID (0x45U) 3106 3107 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS { 3108 NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE sampleData; 3109 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS; 3110 3111 /* _ctrl0000system_h_ */ 3112