1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2004-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #pragma once 25 26 #include <nvtypes.h> 27 28 // 29 // This file was generated with FINN, an NVIDIA coding tool. 30 // Source file: ctrl/ctrl0080/ctrl0080fb.finn 31 // 32 33 #include "ctrl/ctrl0080/ctrl0080base.h" 34 35 /* NV01_DEVICE_XX/NV03_DEVICE fb control commands and parameters */ 36 37 /** 38 * NV0080_CTRL_CMD_FB_GET_CAPS 39 * 40 * This command returns the set of framebuffer capabilities for the device 41 * in the form of an array of unsigned bytes. Framebuffer capabilities 42 * include supported features and required workarounds for the framebuffer 43 * engine(s) within the device, each represented by a byte offset into the 44 * table and a bit position within that byte. 45 * 46 * capsTblSize 47 * This parameter specifies the size in bytes of the caps table. 48 * This value should be set to NV0080_CTRL_FB_CAPS_TBL_SIZE. 49 * capsTbl 50 * This parameter specifies a pointer to the client's caps table buffer 51 * into which the framebuffer caps bits will be transferred by the RM. 52 * The caps table is an array of unsigned bytes. 53 * 54 * Possible status values returned are: 55 * NV_OK 56 * NV_ERR_INVALID_PARAM_STRUCT 57 * NV_ERR_INVALID_ARGUMENT 58 * NV_ERR_INVALID_POINTER 59 */ 60 #define NV0080_CTRL_CMD_FB_GET_CAPS (0x801301) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_GET_CAPS_PARAMS_MESSAGE_ID" */ 61 62 #define NV0080_CTRL_FB_GET_CAPS_PARAMS_MESSAGE_ID (0x1U) 63 64 typedef struct NV0080_CTRL_FB_GET_CAPS_PARAMS { 65 NvU32 capsTblSize; 66 NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); 67 } NV0080_CTRL_FB_GET_CAPS_PARAMS; 68 69 /* extract cap bit setting from tbl */ 70 #define NV0080_CTRL_FB_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) 71 72 /* caps format is byte_index:bit_mask */ 73 #define NV0080_CTRL_FB_CAPS_SUPPORT_RENDER_TO_SYSMEM 0:0x01 74 #define NV0080_CTRL_FB_CAPS_BLOCKLINEAR 0:0x02 75 #define NV0080_CTRL_FB_CAPS_SUPPORT_SCANOUT_FROM_SYSMEM 0:0x04 76 #define NV0080_CTRL_FB_CAPS_SUPPORT_CACHED_SYSMEM 0:0x08 77 #define NV0080_CTRL_FB_CAPS_SUPPORT_C24_COMPRESSION 0:0x10 // Deprecated 78 #define NV0080_CTRL_FB_CAPS_SUPPORT_SYSMEM_COMPRESSION 0:0x20 79 #define NV0080_CTRL_FB_CAPS_NISO_CFG0_BUG_534680 0:0x40 // Deprecated 80 #define NV0080_CTRL_FB_CAPS_ISO_FETCH_ALIGN_BUG_561630 0:0x80 // Deprecated 81 82 #define NV0080_CTRL_FB_CAPS_BLOCKLINEAR_GOBS_512 1:0x01 83 #define NV0080_CTRL_FB_CAPS_L2_TAG_BUG_632241 1:0x02 84 #define NV0080_CTRL_FB_CAPS_SINGLE_FB_UNIT 1:0x04 // Deprecated 85 #define NV0080_CTRL_FB_CAPS_CE_RMW_DISABLE_BUG_897745 1:0x08 // Deprecated 86 #define NV0080_CTRL_FB_CAPS_OS_OWNS_HEAP_NEED_ECC_SCRUB 1:0x10 87 #define NV0080_CTRL_FB_CAPS_ASYNC_CE_L2_BYPASS_SET 1:0x20 // Deprecated 88 #define NV0080_CTRL_FB_CAPS_DISABLE_TILED_CACHING_INVALIDATES_WITH_ECC_BUG_1521641 1:0x40 89 #define NV0080_CTRL_FB_CAPS_GENERIC_PAGE_KIND 1:0x80 90 91 #define NV0080_CTRL_FB_CAPS_DISABLE_MSCG_WITH_VR_BUG_1681803 2:0x01 92 #define NV0080_CTRL_FB_CAPS_VIDMEM_ALLOCS_ARE_CLEARED 2:0x02 93 #define NV0080_CTRL_FB_CAPS_DISABLE_PLC_GLOBALLY 2:0x04 94 #define NV0080_CTRL_FB_CAPS_PLC_BUG_3046774 2:0x08 95 #define NV0080_CTRL_FB_CAPS_PARTIAL_UNMAP 2:0x10 96 97 98 /* size in bytes of fb caps table */ 99 #define NV0080_CTRL_FB_CAPS_TBL_SIZE 3 100 101 102 103 /*! 104 * NV0080_CTRL_CMD_FB_COMPBIT_STORE_GET_INFO 105 * 106 * This command returns compbit backing store-related information. 107 * 108 * size 109 * [out] Size of compbit store, in bytes 110 * address 111 * [out] Address of compbit store 112 * addressSpace 113 * [out] Address space of compbit store (corresponds to type NV_ADDRESS_SPACE in nvrm.h) 114 * maxCompbitLine 115 * [out] Maximum compbitline possible, determined based on size 116 * comptagsPerCacheLine 117 * [out] Number of compression tags per compression cache line, across all 118 * L2 slices. 119 * cacheLineSize 120 * [out] Size of compression cache line, across all L2 slices. (bytes) 121 * cacheLineSizePerSlice 122 * [out] Size of the compression cache line per slice (bytes) 123 * cacheLineFetchAlignment 124 * [out] Alignment used while fetching the compression cacheline range in FB. 125 * If start offset of compcacheline in FB is S and end offset is E, then 126 * the range to fetch to ensure entire compcacheline data is extracted is: 127 * (align_down(S) , align_up(E)) 128 * This is needed in GM20X+ because of interleaving of data in Linear FB space. 129 * Example - In GM204 every other 1K FB chunk of data is offset by 16K. 130 * backingStoreBase 131 * [out] Address of start of Backing Store in linear FB Physical Addr space. 132 * This is the actual offset in FB which HW starts using as the Backing Store and 133 * in general will be different from the start of the region that driver allocates 134 * as the backing store. This address is expected to be 2K aligned. 135 * gobsPerComptagPerSlice 136 * [out] (Only on Pascal) Number of GOBS(512 bytes of surface PA) that correspond to one 64KB comptgaline, per slice. 137 * One GOB stores 1 byte of compression bits. 138 * 0 value means this field is not applicable for the current architecture. 139 * backingStoreCbcBase 140 * [out] 2KB aligned base address of CBC (post divide address) 141 * comptaglineAllocationPolicy 142 * [out] Policy used to allocate comptagline from CBC for the device 143 * privRegionStartOffset 144 * [out] Starting offset for any priv region allocated by clients. only used by MODS 145 * Possible status values returned are: 146 * NV_OK 147 */ 148 #define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO (0x801306) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID" */ 149 150 #define NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID (0x6U) 151 152 typedef struct NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS { 153 NV_DECLARE_ALIGNED(NvU64 Size, 8); 154 NV_DECLARE_ALIGNED(NvU64 Address, 8); 155 NvU32 AddressSpace; 156 NvU32 MaxCompbitLine; 157 NvU32 comptagsPerCacheLine; 158 NvU32 cacheLineSize; 159 NvU32 cacheLineSizePerSlice; 160 NvU32 cacheLineFetchAlignment; 161 NV_DECLARE_ALIGNED(NvU64 backingStoreBase, 8); 162 NvU32 gobsPerComptagPerSlice; 163 NvU32 backingStoreCbcBase; 164 NvU32 comptaglineAllocationPolicy; 165 NV_DECLARE_ALIGNED(NvU64 privRegionStartOffset, 8); 166 NvU32 cbcCoveragePerSlice; 167 } NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS; 168 169 #define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_UNKNOWN 0 // ADDR_UNKNOWN 170 #define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_SYSMEM 1 // ADDR_SYSMEM 171 #define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_FBMEM 2 // ADDR_FBMEM 172 173 // Policy used to allocate comptaglines 174 /** 175 * Legacy mode allocates a comptagline for 64kb page. This mode will always allocate 176 * contiguous comptaglines from a ctag heap. 177 */ 178 #define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_LEGACY 0 179 /** 180 * 1TO1 mode allocates a comptagline for 64kb page. This mode will calculate 181 * comptagline offset based on physical address. This mode will allocate 182 * contiguous comptaglines if the surface is contiguous and non-contiguous 183 * comptaglines for non-contiguous surfaces. 184 */ 185 #define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO1 1 186 /** 187 * 1TO4_Heap mode allocates a comptagline for 256kb page granularity. This mode 188 * will allocate comptagline from a heap. This mode will align the surface allocations 189 * to 256kb before allocating comptaglines. The comptaglines allocated will always be 190 * contiguous here. 191 * TODO: For GA10x, this mode will support < 256kb surface allocations, by sharing 192 * a comptagline with at most 3 different 64Kb allocations. This will result in 193 * miixed-contiguity config where comptaglines will be allocated contiguously as well 194 * as non-contiguous when shared with other allocations. 195 */ 196 #define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO4 2 197 /** 198 * Rawmode will transfer allocation of comptaglines to HW, where HW manages 199 * comptaglines based on physical offset. The comptaglines are cleared when SW 200 * issues physical/virtual scrub to the surface before reuse. 201 */ 202 #define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_RAWMODE 3 203 204 /** 205 * NV0080_CTRL_CMD_FB_GET_CAPS_V2 206 * 207 * This command returns the same set of framebuffer capabilities for the 208 * device as @ref NV0080_CTRL_CMD_FB_GET_CAPS. The difference is in the structure 209 * NV0080_CTRL_FB_GET_CAPS_V2_PARAMS, which contains a statically sized array, 210 * rather than a caps table pointer and a caps table size in 211 * NV0080_CTRL_FB_GET_CAPS_PARAMS. 212 * 213 * capsTbl 214 * This parameter specifies a pointer to the client's caps table buffer 215 * into which the framebuffer caps bits will be written by the RM. 216 * The caps table is an array of unsigned bytes. 217 * 218 * Possible status values returned are: 219 * NV_OK 220 * NV_ERR_INVALID_PARAM_STRUCT 221 * NV_ERR_INVALID_ARGUMENT 222 * NV_ERR_INVALID_POINTER 223 */ 224 #define NV0080_CTRL_CMD_FB_GET_CAPS_V2 (0x801307) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ 225 226 #define NV0080_CTRL_FB_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x7U) 227 228 typedef struct NV0080_CTRL_FB_GET_CAPS_V2_PARAMS { 229 NvU8 capsTbl[NV0080_CTRL_FB_CAPS_TBL_SIZE]; 230 } NV0080_CTRL_FB_GET_CAPS_V2_PARAMS; 231 232 /** 233 * NV0080_CTRL_CMD_FB_SET_DEFAULT_VIDMEM_PHYSICALITY 234 * 235 * When clients allocate video memory specifying _DEFAULT (0) for 236 * NVOS32_ATTR_PHYSICALITY, RM will usually allocate contiguous memory. 237 * Clients can change that behavior with this command so that _DEFAULT maps to 238 * another value. 239 * 240 * The expectation is that clients currently implicitly rely on the default, 241 * but can be incrementally updated to explicitly specify _CONTIGUOUS where 242 * necessary and change the default for their allocations to _NONCONTIGUOUS or 243 * _ALLOW_NONCONTIGUOUS. 244 * 245 * In the future RM may be updated to globally default to _NONCONTIGUOUS or 246 * _ALLOW_NONCONTIGUOUS, and at that point this can be removed. 247 */ 248 #define NV0080_CTRL_CMD_FB_SET_DEFAULT_VIDMEM_PHYSICALITY (0x801308) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS_MESSAGE_ID" */ 249 250 #define NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS_MESSAGE_ID (0x8U) 251 252 typedef struct NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS { 253 NvU32 value; 254 } NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS; 255 256 typedef enum NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY { 257 NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT = 0, 258 NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS = 1, 259 NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS = 2, 260 NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS = 3, 261 } NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY; 262 263 264 /* _ctrl0080fb_h_ */ 265