1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #pragma once 25 26 #include <nvtypes.h> 27 28 // 29 // This file was generated with FINN, an NVIDIA coding tool. 30 // Source file: ctrl/ctrla081.finn 31 // 32 33 #include "ctrl/ctrlxxxx.h" 34 #include "ctrl/ctrl2080/ctrl2080gpu.h" 35 #include "nv_vgpu_types.h" 36 /* NVA081_VGPU_CONFIG control commands and parameters */ 37 38 #define NVA081_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA081, NVA081_CTRL_##cat, idx) 39 40 /* Command categories (6bits) */ 41 #define NVA081_CTRL_RESERVED (0x00) 42 #define NVA081_CTRL_VGPU_CONFIG (0x01) 43 44 #define NVA081_CTRL_VGPU_CONFIG_INVALID_TYPE 0x00 45 #define NVA081_MAX_VGPU_TYPES_PER_PGPU 0x40 46 #define NVA081_MAX_VGPU_PER_PGPU 32 47 #define NVA081_VM_UUID_SIZE 16 48 #define NVA081_VGPU_STRING_BUFFER_SIZE 32 49 #define NVA081_VGPU_SIGNATURE_SIZE 128 50 #define NVA081_VM_NAME_SIZE 128 51 #define NVA081_PCI_CONFIG_SPACE_SIZE 0x100 52 #define NVA081_PGPU_METADATA_STRING_SIZE 256 53 #define NVA081_EXTRA_PARAMETERS_SIZE 1024 54 #define NVA081_PLACEMENT_ID_INVALID 0xFFFFU 55 #define NVA081_CONFIG_PARAMS_MAX_LENGTH 1024 56 57 #define NVA081_MAX_BAR_REGION_COUNT 4 58 #define NVA081_MAX_SPARSE_REGION_COUNT 5 59 60 /* 61 * NVA081_CTRL_CMD_VGPU_CONFIG_SET_INFO 62 * 63 * This command sets the vGPU config information in RM 64 * 65 * Parameters: 66 * 67 * discardVgpuTypes [IN] 68 * This parameter specifies if existing vGPU configuration should be 69 * discarded for given pGPU 70 * 71 * vgpuInfo [IN] 72 * This parameter specifies virtual GPU type information 73 * 74 * Possible status values returned are: 75 * NV_OK 76 * NV_ERR_NOT_SUPPORTED 77 */ 78 #define NVA081_CTRL_CMD_VGPU_CONFIG_SET_INFO (0xa0810101) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS_MESSAGE_ID" */ 79 80 /* 81 * NVA081_CTRL_VGPU_CONFIG_INFO 82 * 83 * This structure represents the per vGPU information 84 * 85 */ 86 typedef struct NVA081_CTRL_VGPU_INFO { 87 // This structure should be in sync with NVA082_CTRL_CMD_HOST_VGPU_DEVICE_GET_VGPU_TYPE_INFO_PARAMS 88 NvU32 vgpuType; 89 NvU8 vgpuName[NVA081_VGPU_STRING_BUFFER_SIZE]; 90 NvU8 vgpuClass[NVA081_VGPU_STRING_BUFFER_SIZE]; 91 NvU8 vgpuSignature[NVA081_VGPU_SIGNATURE_SIZE]; 92 NvU8 license[NV_GRID_LICENSE_INFO_MAX_LENGTH]; 93 NvU32 maxInstance; 94 NvU32 numHeads; 95 NvU32 maxResolutionX; 96 NvU32 maxResolutionY; 97 NvU32 maxPixels; 98 NvU32 frlConfig; 99 NvU32 cudaEnabled; 100 NvU32 eccSupported; 101 NvU32 gpuInstanceSize; 102 NvU32 multiVgpuSupported; 103 NV_DECLARE_ALIGNED(NvU64 vdevId, 8); 104 NV_DECLARE_ALIGNED(NvU64 pdevId, 8); 105 NV_DECLARE_ALIGNED(NvU64 profileSize, 8); 106 NV_DECLARE_ALIGNED(NvU64 fbLength, 8); 107 NV_DECLARE_ALIGNED(NvU64 gspHeapSize, 8); 108 NV_DECLARE_ALIGNED(NvU64 fbReservation, 8); 109 NV_DECLARE_ALIGNED(NvU64 mappableVideoSize, 8); 110 NvU32 encoderCapacity; 111 NV_DECLARE_ALIGNED(NvU64 bar1Length, 8); 112 NvU32 frlEnable; 113 NvU8 adapterName[NV2080_GPU_MAX_NAME_STRING_LENGTH]; 114 NvU16 adapterName_Unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH]; 115 NvU8 shortGpuNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH]; 116 NvU8 licensedProductName[NV_GRID_LICENSE_INFO_MAX_LENGTH]; 117 NvU32 vgpuExtraParams[NVA081_EXTRA_PARAMETERS_SIZE]; 118 NvU32 ftraceEnable; 119 NvU32 gpuDirectSupported; 120 NvU32 nvlinkP2PSupported; 121 NvU32 multiVgpuExclusive; 122 NvU32 exclusiveType; 123 NvU32 exclusiveSize; 124 // used only by NVML 125 NvU32 gpuInstanceProfileId; 126 NvU32 placementSize; 127 NvU32 placementCount; 128 NvU32 placementIds[NVA081_MAX_VGPU_PER_PGPU]; 129 } NVA081_CTRL_VGPU_INFO; 130 131 /* 132 * NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS 133 * 134 * This structure represents the vGPU configuration information 135 * 136 */ 137 #define NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS_MESSAGE_ID (0x1U) 138 139 typedef struct NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS { 140 NvBool discardVgpuTypes; 141 NV_DECLARE_ALIGNED(NVA081_CTRL_VGPU_INFO vgpuInfo, 8); 142 NvU32 vgpuConfigState; 143 } NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS; 144 145 /* VGPU Config state values */ 146 #define NVA081_CTRL_VGPU_CONFIG_STATE_UNINITIALIZED 0 147 #define NVA081_CTRL_VGPU_CONFIG_STATE_IN_PROGRESS 1 148 #define NVA081_CTRL_VGPU_CONFIG_STATE_READY 2 149 150 /* 151 * NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU 152 * 153 * This command enumerates list of vGPU guest instances per pGpu 154 * 155 * Parameters: 156 * 157 * vgpuType [OUT] 158 * This parameter specifies the virtual GPU type for this physical GPU 159 * 160 * numVgpu [OUT] 161 * This parameter specifies the number of virtual GPUs created on this physical GPU 162 * 163 * guestInstanceInfo [OUT] 164 * This parameter specifies an array containing guest instance's information for 165 * all instances created on this physical GPU 166 * 167 * guestVgpuInfo [OUT] 168 * This parameter specifies an array containing guest vgpu's information for 169 * all vGPUs created on this physical GPU 170 * 171 * Possible status values returned are: 172 * NV_OK 173 * NV_ERR_OBJECT_NOT_FOUND 174 */ 175 #define NVA081_CTRL_CMD_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU (0xa0810102) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID" */ 176 177 /* 178 * NVA081_GUEST_VM_INFO 179 * 180 * This structure represents vGPU guest's (VM's) information 181 * 182 * vmPid [OUT] 183 * This param specifies the vGPU plugin process ID 184 * vmIdType [OUT] 185 * This param specifies the VM ID type, i.e. DOMAIN_ID or UUID 186 * guestOs [OUT] 187 * This param specifies the vGPU guest OS type 188 * migrationProhibited [OUT] 189 * This flag indicates whether migration is prohibited for VM or not 190 * guestNegotiatedVgpuVersion [OUT] 191 * This param specifies the vGPU version of guest driver after negotiation 192 * frameRateLimit [OUT] 193 * This param specifies the current value of FRL set for guest 194 * licensed [OUT] 195 * This param specifies whether the VM is Unlicensed/Licensed 196 * licenseState [OUT] 197 * This param specifies the current state of the GRID license state machine 198 * licenseExpiryTimestamp [OUT] 199 * License expiry time in seconds since UNIX epoch 200 * licenseExpiryStatus [OUT] 201 * License expiry status 202 * guestDriverVersion [OUT] 203 * This param specifies the driver version of the driver installed on the VM 204 * guestDriverBranch [OUT] 205 * This param specifies the driver branch of the driver installed on the VM 206 * vmName [OUT] 207 * This param stores the name assigned to VM (KVM only) 208 * guestVmInfoState [OUT] 209 * This param stores the current state of guest dependent fields 210 * 211 */ 212 typedef struct NVA081_GUEST_VM_INFO { 213 NvU32 vmPid; 214 VM_ID_TYPE vmIdType; 215 NvU32 guestOs; 216 NvU32 migrationProhibited; 217 NvU32 guestNegotiatedVgpuVersion; 218 NvU32 frameRateLimit; 219 NvBool licensed; 220 NvU32 licenseState; 221 NvU32 licenseExpiryTimestamp; 222 NvU8 licenseExpiryStatus; 223 NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); 224 NvU8 guestDriverVersion[NVA081_VGPU_STRING_BUFFER_SIZE]; 225 NvU8 guestDriverBranch[NVA081_VGPU_STRING_BUFFER_SIZE]; 226 NvU8 vmName[NVA081_VM_NAME_SIZE]; 227 GUEST_VM_INFO_STATE guestVmInfoState; 228 } NVA081_GUEST_VM_INFO; 229 230 /* 231 * NVA081_GUEST_VGPU_DEVICE 232 * 233 * This structure represents host vgpu device's (assigned to VM) information 234 * 235 * eccState [OUT] 236 * This parameter specifies the ECC state of the virtual GPU. 237 * One of NVA081_CTRL_ECC_STATE_xxx values. 238 * bDriverLoaded [OUT] 239 * This parameter specifies whether driver is loaded on this particular vGPU. 240 * swizzId [OUT] 241 * This param specifies the GPU Instance ID or Swizz ID 242 * placementId [OUT] 243 * This param specifies the placement ID of heterogeneous timesliced vGPU instance. 244 * Otherwise it is NVA081_PLACEMENT_ID_INVALID. 245 * 246 */ 247 typedef struct NVA081_HOST_VGPU_DEVICE { 248 NvU32 vgpuType; 249 NvU32 vgpuDeviceInstanceId; 250 NV_DECLARE_ALIGNED(NvU64 vgpuPciId, 8); 251 NvU8 vgpuUuid[VM_UUID_SIZE]; 252 NvU8 mdevUuid[VM_UUID_SIZE]; 253 NvU32 encoderCapacity; 254 NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); 255 NvU32 eccState; 256 NvBool bDriverLoaded; 257 NvU32 swizzId; 258 NvU32 placementId; 259 } NVA081_HOST_VGPU_DEVICE; 260 261 /* ECC state values */ 262 #define NVA081_CTRL_ECC_STATE_UNKNOWN 0 263 #define NVA081_CTRL_ECC_STATE_NOT_SUPPORTED 1 264 #define NVA081_CTRL_ECC_STATE_DISABLED 2 265 #define NVA081_CTRL_ECC_STATE_ENABLED 3 266 267 /* 268 * NVA081_VGPU_GUEST 269 * 270 * This structure represents a vGPU guest 271 * 272 */ 273 typedef struct NVA081_VGPU_GUEST { 274 NV_DECLARE_ALIGNED(NVA081_GUEST_VM_INFO guestVmInfo, 8); 275 NV_DECLARE_ALIGNED(NVA081_HOST_VGPU_DEVICE vgpuDevice, 8); 276 } NVA081_VGPU_GUEST; 277 278 /* 279 * NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS 280 * 281 * This structure represents the information of vGPU guest instances per pGpu 282 * 283 */ 284 #define NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID (0x2U) 285 286 typedef struct NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS { 287 NvU32 vgpuType; 288 NvU32 numVgpu; 289 NV_DECLARE_ALIGNED(NVA081_VGPU_GUEST vgpuGuest[NVA081_MAX_VGPU_PER_PGPU], 8); 290 } NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS; 291 292 /* 293 * NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_TYPE_INFO 294 * 295 * This command fetches vGPU type info from RM. 296 * 297 * Parameters: 298 * 299 * vgpuType [IN] 300 * This parameter specifies the virtual GPU type for which vGPU info should be returned. 301 * 302 * vgpuTypeInfo [OUT] 303 * This parameter returns NVA081_CTRL_VGPU_INFO data for the vGPU type specified by vgpuType. 304 * 305 * Possible status values returned are: 306 * NV_OK 307 * NV_ERR_OBJECT_NOT_FOUND 308 */ 309 310 #define NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_TYPE_INFO (0xa0810103) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS_MESSAGE_ID" */ 311 312 /* 313 * NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS 314 * 315 */ 316 #define NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS_MESSAGE_ID (0x3U) 317 318 typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS { 319 NvU32 vgpuType; 320 NV_DECLARE_ALIGNED(NVA081_CTRL_VGPU_INFO vgpuTypeInfo, 8); 321 } NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS; 322 323 /* 324 * NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS 325 * This structure represents supported/creatable vGPU types on a pGPU 326 */ 327 typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS { 328 /* 329 * [OUT] vGPU config state on a pGPU 330 */ 331 NvU32 vgpuConfigState; 332 333 /* 334 * [OUT] Count of supported/creatable vGPU types on a pGPU 335 */ 336 NvU32 numVgpuTypes; 337 338 /* 339 * [OUT] - Array of vGPU type ids supported/creatable on a pGPU 340 */ 341 NvU32 vgpuTypes[NVA081_MAX_VGPU_TYPES_PER_PGPU]; 342 } NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS; 343 344 345 /* 346 * NVA081_CTRL_CMD_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES 347 * 348 * This command fetches count and list of vGPU types supported on a pGpu from RM 349 * 350 * Parameters: 351 * 352 * numVgpuTypes [OUT] 353 * This parameter returns the number of vGPU types supported on this pGPU 354 * 355 * vgpuTypes [OUT] 356 * This parameter returns list of supported vGPUs types on this pGPU 357 * 358 * Possible status values returned are: 359 * NV_OK 360 * NV_ERR_OBJECT_NOT_FOUND 361 * NV_ERR_NOT_SUPPORTED 362 */ 363 364 #define NVA081_CTRL_CMD_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES (0xa0810104) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES_PARAMS_MESSAGE_ID" */ 365 366 #define NVA081_CTRL_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES_PARAMS_MESSAGE_ID (0x4U) 367 368 typedef NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS NVA081_CTRL_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES_PARAMS; 369 370 /* 371 * NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES 372 * 373 * This command fetches count and list of vGPU types creatable on a pGpu from RM 374 * 375 * Parameters: 376 * 377 * numVgpuTypes [OUT] 378 * This parameter returns the number of vGPU types creatable on this pGPU 379 * 380 * vgpuTypes [OUT] 381 * This parameter returns list of creatable vGPUs types on this pGPU 382 * 383 * Possible status values returned are: 384 * NV_OK 385 * NV_ERR_OBJECT_NOT_FOUND 386 * NV_ERR_NOT_SUPPORTED 387 */ 388 389 #define NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES (0xa0810105) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES_PARAMS_MESSAGE_ID" */ 390 391 #define NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES_PARAMS_MESSAGE_ID (0x5U) 392 393 typedef NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES_PARAMS; 394 395 /* 396 * NVA081_CTRL_CMD_VGPU_CONFIG_EVENT_SET_NOTIFICATION 397 * 398 * This command sets event notification state for the associated subdevice/pGPU. 399 * This command requires that an instance of NV01_EVENT has been previously 400 * bound to the associated subdevice object. 401 * 402 * event 403 * This parameter specifies the type of event to which the specified 404 * action is to be applied. This parameter must specify a valid 405 * NVA081_NOTIFIERS value (see cla081.h for more details) and should 406 * not exceed one less NVA081_NOTIFIERS_MAXCOUNT. 407 * action 408 * This parameter specifies the desired event notification action. 409 * Valid notification actions include: 410 * NVA081_CTRL_SET_EVENT_NOTIFICATION_DISABLE 411 * This action disables event notification for the specified 412 * event for the associated subdevice object. 413 * NVA081_CTRL_SET_EVENT_NOTIFICATION_SINGLE 414 * This action enables single-shot event notification for the 415 * specified event for the associated subdevice object. 416 * NVA081_CTRL_SET_EVENT_NOTIFICATION_REPEAT 417 * This action enables repeated event notification for the specified 418 * event for the associated system controller object. 419 * 420 * Possible status values returned are: 421 * NV_OK 422 * NV_ERR_INVALID_PARAM_STRUCT 423 * NV_ERR_INVALID_ARGUMENT 424 * NV_ERR_INVALID_STATE 425 */ 426 #define NVA081_CTRL_CMD_VGPU_CONFIG_EVENT_SET_NOTIFICATION (0xa0810106) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ 427 428 #define NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x6U) 429 430 typedef struct NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS { 431 NvU32 event; 432 NvU32 action; 433 } NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS; 434 435 436 /* valid event action values */ 437 #define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) 438 #define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) 439 #define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) 440 441 /* 442 * NVA081_CTRL_CMD_VGPU_CONFIG_UPDATE_PGPU_INFO 443 * 444 * This command register the GPU to Linux kernel's mdev module for vGPU on KVM. 445 */ 446 #define NVA081_CTRL_CMD_VGPU_CONFIG_UPDATE_PGPU_INFO (0xa0810109) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x9" */ 447 448 /* 449 * NVA081_CTRL_CMD_VGPU_CONFIG_SET_VGPU_INSTANCE_ENCODER_CAPACITY 450 * 451 * This command is used to set vGPU instance's (represented by vgpuUuid) encoder Capacity. 452 * 453 * vgpuUuid 454 * This parameter specifies the uuid of vGPU assigned to VM. 455 * encoderCapacity 456 * Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance 457 * may be minimal for this GPU and software should fall back to CPU-based encode. 458 * 459 * Possible status values returned are: 460 * NV_OK 461 * NV_ERR_INVALID_ARGUMENT 462 */ 463 464 #define NVA081_CTRL_CMD_VGPU_CONFIG_SET_VGPU_INSTANCE_ENCODER_CAPACITY (0xa0810110) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS_MESSAGE_ID" */ 465 466 /* 467 * NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS 468 * 469 * This structure represents encoder capacity for vgpu instance. 470 */ 471 #define NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x10U) 472 473 typedef struct NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS { 474 NvU8 vgpuUuid[VM_UUID_SIZE]; 475 NvU32 encoderCapacity; 476 } NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS; 477 478 /* 479 * NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_FB_USAGE 480 * 481 * This command is used to get the FB usage of all vGPU instances running on a GPU. 482 * 483 * vgpuCount 484 * This field specifies the number of vGPU devices for which FB usage is returned. 485 * vgpuFbUsage 486 * This is an array of type NVA081_VGPU_FB_USAGE, which contains a list of vGPUs 487 * and their corresponding FB usage in bytes; 488 * 489 * Possible status values returned are: 490 * NV_OK 491 * NV_ERR_INVALID_ARGUMENT 492 */ 493 #define NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_FB_USAGE (0xa0810111) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID" */ 494 495 typedef struct NVA081_VGPU_FB_USAGE { 496 NvU8 vgpuUuid[VM_UUID_SIZE]; 497 NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); 498 } NVA081_VGPU_FB_USAGE; 499 500 /* 501 * NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS 502 * 503 * This structure represents the FB usage information of vGPU instances running on a GPU. 504 */ 505 #define NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID (0x11U) 506 507 typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS { 508 NvU32 vgpuCount; 509 NV_DECLARE_ALIGNED(NVA081_VGPU_FB_USAGE vgpuFbUsage[NVA081_MAX_VGPU_PER_PGPU], 8); 510 } NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS; 511 512 /* 513 * NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP 514 * 515 * This command is used to query whether pGPU is live migration capable or not. 516 * 517 * bMigrationCap 518 * Set to NV_TRUE if pGPU is migration capable. 519 * 520 * Possible status values returned are: 521 * NV_OK 522 * NV_ERR_INVALID_STATE 523 * NV_ERR_INVALID_REQUEST 524 */ 525 #define NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP (0xa0810112) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS_MESSAGE_ID" */ 526 527 /* 528 * NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS 529 */ 530 #define NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS_MESSAGE_ID (0x12U) 531 532 typedef struct NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS { 533 NvBool bMigrationCap; 534 } NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS; 535 536 /* 537 * NVA081_CTRL_CMD_VGPU_CONFIG_GET_HOST_FB_RESERVATION 538 * 539 * This command is used to get the host FB requirements 540 * 541 * hostReservedFb [OUT] 542 * Amount of FB reserved for the host 543 * eccAndPrReservedFb [OUT] 544 * Amount of FB reserved for the ecc and page retirement 545 * totalReservedFb [OUT] 546 * Total FB reservation 547 * vgpuTypeId [IN] 548 * The Type ID for VGPU profile 549 * 550 * Possible status values returned are: 551 * NV_OK 552 * NV_ERR_INVALID_ARGUMENT 553 */ 554 #define NVA081_CTRL_CMD_VGPU_CONFIG_GET_HOST_FB_RESERVATION (0xa0810113) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS_MESSAGE_ID" */ 555 556 #define NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS_MESSAGE_ID (0x13U) 557 558 typedef struct NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS { 559 NV_DECLARE_ALIGNED(NvU64 hostReservedFb, 8); 560 NV_DECLARE_ALIGNED(NvU64 eccAndPrReservedFb, 8); 561 NV_DECLARE_ALIGNED(NvU64 totalReservedFb, 8); 562 NvU32 vgpuTypeId; 563 } NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS; 564 565 /* 566 * NVA081_CTRL_CMD_VGPU_CONFIG_GET_PGPU_METADATA_STRING 567 * 568 * This command is used to get the pGpu metadata string. 569 * 570 * pGpuString 571 * String holding pGpu Metadata 572 * 573 * Possible status values returned are: 574 * NV_OK 575 * NV_ERR_INVALID_REQUEST 576 * NV_ERR_INVALID_STATE 577 * NV_ERR_INSUFFICIENT_RESOURCES 578 */ 579 #define NVA081_CTRL_CMD_VGPU_CONFIG_GET_PGPU_METADATA_STRING (0xa0810114) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS_MESSAGE_ID" */ 580 581 #define NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS_MESSAGE_ID (0x14U) 582 583 typedef struct NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS { 584 NvU8 pGpuString[NVA081_PGPU_METADATA_STRING_SIZE]; 585 } NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS; 586 587 #define NVA081_CTRL_CMD_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT (0xa0810115) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS_MESSAGE_ID" */ 588 589 #define NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS_MESSAGE_ID (0x15U) 590 591 typedef struct NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS { 592 NvBool doorbellEmulationEnabled; 593 } NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS; 594 595 /* 596 * NVA081_CTRL_CMD_VGPU_CONFIG_GET_FREE_SWIZZID 597 * 598 * This command is used to get free swizzid from RM 599 * 600 * gpuPciId [IN] 601 * This param specifies the PCI device ID of VF on which VM is running 602 * 603 * vgpuTypeId [IN] 604 * This param specifies the Type ID for VGPU profile 605 * 606 * swizzId [OUT] 607 * This param specifies the GPU Instance ID or Swizz ID 608 * 609 * Possible status values returned are: 610 * NV_OK 611 * NV_ERR_INVALID_REQUEST 612 * NV_ERR_INVALID_STATE 613 * NV_ERR_INVALID_ARGUMENT 614 */ 615 #define NVA081_CTRL_CMD_VGPU_CONFIG_GET_FREE_SWIZZID (0xa0810116) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS_MESSAGE_ID" */ 616 617 #define NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS_MESSAGE_ID (0x16U) 618 619 typedef struct NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS { 620 NvU32 gpuPciId; 621 NvU32 vgpuTypeId; 622 NvU32 swizzId; 623 } NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS; 624 625 /* 626 * NVA081_CTRL_CMD_PGPU_GET_MULTI_VGPU_SUPPORT_INFO 627 * 628 * This command is used to get multi vGPU related info for the physical GPU. 629 * 630 * fractionalmultiVgpuSupported [OUT] 631 * This param specifies whether fractional multi-vGPU is supported 632 * 633 * heterogeneousTimesliceProfilesSupported [OUT] 634 * This param specifies whether concurrent execution of timesliced vGPU profiles of differing types is supported 635 * 636 * heterogeneousTimesliceSizesSupported [OUT] 637 * This param specifies whether concurrent execution of timesliced vGPU profiles of differing framebuffer sizes is supported 638 * 639 * Possible status values returned are: 640 * NV_OK 641 * NV_ERR_INVALID_REQUEST 642 * NV_ERR_INVALID_STATE 643 * NV_ERR_INVALID_ARGUMENT 644 */ 645 646 #define NVA081_CTRL_CMD_PGPU_GET_MULTI_VGPU_SUPPORT_INFO (0xa0810117) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS_MESSAGE_ID" */ 647 648 #define NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS_MESSAGE_ID (0x17U) 649 650 typedef struct NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS { 651 NvU32 fractionalmultiVgpuSupported; 652 NvU32 heterogeneousTimesliceProfilesSupported; 653 NvU32 heterogeneousTimesliceSizesSupported; 654 } NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS; 655 656 /* 657 * NVA081_CTRL_CMD_GET_VGPU_DRIVER_CAPS 658 * 659 * This command is used to get vGPU driver capabilities. 660 * 661 * heterogeneousMultiVgpuSupported [OUT] 662 * This param specifies whether heterogeneous multi-vGPU is supported 663 * 664 * Possible status values returned are: 665 * NV_OK 666 * NV_ERR_INVALID_REQUEST 667 * NV_ERR_INVALID_STATE 668 * NV_ERR_INVALID_ARGUMENT 669 */ 670 671 #define NVA081_CTRL_CMD_GET_VGPU_DRIVER_CAPS (0xa0810118) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS_MESSAGE_ID" */ 672 673 #define NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS_MESSAGE_ID (0x18U) 674 675 typedef struct NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS { 676 NvU32 heterogeneousMultiVgpuSupported; 677 } NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS; 678 679 /* 680 * NVA081_CTRL_CMD_VGPU_CONFIG_SET_PGPU_INFO 681 * 682 * This command is to set pgpu info 683 * 684 * fractionalMultiVgpu [IN] 685 * This param specifies the fractional multivgpu is enabled or disabled on GPU 686 * 687 * Possible status values returned are: 688 * NV_OK 689 * NV_ERR_OBJECT_NOT_FOUND 690 */ 691 692 #define NVA081_CTRL_CMD_VGPU_CONFIG_SET_PGPU_INFO (0xa0810119) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS_MESSAGE_ID" */ 693 694 #define NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS_MESSAGE_ID (0x19U) 695 696 typedef struct NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS { 697 NvU32 fractionalMultiVgpu; 698 } NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS; 699 700 /* 701 * NVA081_CTRL_CMD_VGPU_CONFIG_VALIDATE_SWIZZID 702 * 703 * This command is used to vallidate input swizzid from RM 704 * 705 * vgpuTypeId [IN] 706 * This param specifies the Type ID for VGPU profile 707 * 708 * swizzId [IN] 709 * This param specifies the GPU Instance ID or Swizz ID 710 * 711 * Possible status values returned are: 712 * NV_OK 713 * NV_ERR_INVALID_REQUEST 714 * NV_ERR_INVALID_STATE 715 * NV_ERR_INVALID_ARGUMENT 716 */ 717 #define NVA081_CTRL_CMD_VGPU_CONFIG_VALIDATE_SWIZZID (0xa081011a) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS_MESSAGE_ID" */ 718 719 #define NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS_MESSAGE_ID (0x1aU) 720 721 typedef struct NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS { 722 NvU32 vgpuTypeId; 723 NvU32 swizzId; 724 } NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS; 725 726 /* 727 * NVA081_CTRL_CMD_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO 728 * 729 * This command is used to get a placement Id from RM for timesliced 730 * heterogeneous vGPUs. 731 * 732 * isHeterogeneousEnabled [OUT] 733 * This param specific whether timesliced heterogeneous vGPU is enabled 734 * for different FB sized profiles. 735 * 736 * vgpuTypeId [IN] 737 * This param specifies the Type ID for VGPU profile 738 * 739 * placementId [IN / OUT] 740 * This param specifies the input placement ID provided by hypervisor 741 * or output placement ID reserved by RM for vGPU type ID. 742 * 743 * TODO : This same RmCtrl will be also be used to provide GSP heap offset 744 * to CPU plugin when vGPU-GSP is enabled. 745 * (As guest fb and gsp heap is allocated before A084 object) 746 * 747 * Possible status values returned are: 748 * NV_OK 749 * NV_ERR_INVALID_REQUEST 750 * NV_ERR_INVALID_STATE 751 * NV_ERR_INVALID_ARGUMENT 752 */ 753 #define NVA081_CTRL_CMD_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO (0xa081011b) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS_MESSAGE_ID" */ 754 755 #define NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS_MESSAGE_ID (0x1bU) 756 757 typedef struct NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS { 758 NvBool isHeterogeneousEnabled; 759 NvU16 placementId; 760 NvU32 vgpuTypeId; 761 NV_DECLARE_ALIGNED(NvU64 guestFbLength, 8); 762 NV_DECLARE_ALIGNED(NvU64 guestFbOffset, 8); 763 NV_DECLARE_ALIGNED(NvU64 gspHeapOffset, 8); 764 } NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS; 765 766 /* 767 * NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS 768 * 769 * This command fetches count and list of creatable vGPU placements 770 * 771 * Parameters: 772 * 773 * vgpuTypeId [IN] 774 * The client provided vGPU type ID 775 * 776 * placementSize [OUT] 777 * The number of placement slots occupied by the vGPU type 778 * 779 * count [OUT] 780 * This parameter returns the number of placements supported for the vGPU 781 * 782 * placementIds [OUT] 783 * Array of creatable placement IDs 784 * 785 * Possible status values returned are: 786 * NV_OK 787 * NV_ERR_OBJECT_NOT_FOUND 788 * NV_ERR_NOT_SUPPORTED 789 */ 790 791 #define NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS (0xa081011c) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS_MESSAGE_ID" */ 792 793 #define NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS_MESSAGE_ID (0x1cU) 794 795 typedef struct NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS { 796 NvU32 vgpuTypeId; 797 NvU32 placementSize; 798 NvU32 count; 799 NvU32 placementIds[NVA081_MAX_VGPU_PER_PGPU]; 800 } NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS; 801 802 /* 803 * NVA081_CTRL_CMD_PGPU_GET_VGPU_STREAMING_CAPABILITY 804 * 805 * This command is used to get streaming capability for the physical GPU. 806 * 807 * streamingCapability [OUT] 808 * This param specifies whether vGPU profiles on the GPU supports migration data streaming 809 * 810 * Possible status values returned are: 811 * NV_OK 812 * NV_ERR_INVALID_REQUEST 813 * NV_ERR_INVALID_ARGUMENT 814 */ 815 #define NVA081_CTRL_CMD_PGPU_GET_VGPU_STREAMING_CAPABILITY (0xa081011d) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS_MESSAGE_ID" */ 816 817 #define NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS_MESSAGE_ID (0x1dU) 818 819 typedef struct NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS { 820 NvBool streamingCapability; 821 } NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS; 822 823 /* vGPU capabilities */ 824 #define NVA081_CTRL_VGPU_CAPABILITY_MINI_QUARTER_GPU 0 825 #define NVA081_CTRL_VGPU_CAPABILITY_COMPUTE_MEDIA_ENGINE_GPU 1 826 827 /* 828 * NVA081_CTRL_CMD_VGPU_SET_CAPABILITY 829 * 830 * This command is used to set vGPU capability for the physical GPU. 831 * 832 * capability [IN] 833 * This param specifies the requested capabiity of the device that is to be set 834 * One of NVA081_CTRL_VGPU_CAPABILITY* values 835 * 836 * state [IN] 837 * This param specifies the state of the capability 838 * 839 * Possible status values returned are: 840 * NV_OK 841 * NV_ERR_OBJECT_NOT_FOUND 842 * NV_ERR_INVALID_ARGUMENT 843 */ 844 #define NVA081_CTRL_CMD_VGPU_SET_CAPABILITY (0xa081011e) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS_MESSAGE_ID" */ 845 846 #define NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS_MESSAGE_ID (0x1eU) 847 848 typedef struct NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS { 849 NvU32 capability; 850 NvBool state; 851 } NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS; 852 853 /* 854 * NVA081_CTRL_CMD_VGPU_GET_CAPABILITY 855 * 856 * This command is to get state of vGPU capability for the physical GPU. 857 * 858 * capability [IN] 859 * This param specifies the requested capabiity of the device that is to be set 860 * One of NVA081_CTRL_VGPU_CAPABILITY* values 861 * 862 * state [OUT] 863 * This param specifies the state of the capability 864 * 865 * Possible status values returned are: 866 * NV_OK 867 * NV_ERR_OBJECT_NOT_FOUND 868 * NV_ERR_INVALID_ARGUMENT 869 */ 870 #define NVA081_CTRL_CMD_VGPU_GET_CAPABILITY (0xa081011f) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_GET_CAPABILITY_PARAMS_MESSAGE_ID" */ 871 872 #define NVA081_CTRL_VGPU_GET_CAPABILITY_PARAMS_MESSAGE_ID (0x1fU) 873 874 typedef struct NVA081_CTRL_VGPU_GET_CAPABILITY_PARAMS { 875 NvU32 capability; 876 NvBool state; 877 } NVA081_CTRL_VGPU_GET_CAPABILITY_PARAMS; 878 879 /* 880 * NVA081_CTRL_CMD_VGPU_SET_VM_NAME 881 * 882 * This command is to set VM name for KVM. 883 * 884 * vgpuName [IN] 885 * This param provides the vGPU device name to RM. 886 * 887 * vmName [IN] 888 * This param provides the VM name of the vGPU device attached. 889 * 890 * Possible status values returned are: 891 * NV_OK 892 * NV_ERR_OBJECT_NOT_FOUND 893 * NV_ERR_INVALID_ARGUMENT 894 */ 895 896 #define NVA081_CTRL_CMD_VGPU_SET_VM_NAME (0xa0810120) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_SET_VM_NAME_PARAMS_MESSAGE_ID" */ 897 898 #define NVA081_CTRL_VGPU_SET_VM_NAME_PARAMS_MESSAGE_ID (0x20U) 899 900 typedef struct NVA081_CTRL_VGPU_SET_VM_NAME_PARAMS { 901 NvU8 vgpuName[VM_UUID_SIZE]; 902 NvU8 vmName[NVA081_VM_NAME_SIZE]; 903 } NVA081_CTRL_VGPU_SET_VM_NAME_PARAMS; 904 905 /* 906 * NVA081_CTRL_CMD_VGPU_GET_BAR_INFO 907 * 908 * This command is to get the bar info for a vGPU. 909 * 910 * gpuPciId [IN] 911 * This param specifies the PCI device ID of VF on which VM is running 912 * 913 * vgpuName [IN] 914 * This param provides the vGPU device name to RM. 915 * 916 * configParams [IN] 917 * This param provides the vGPU config params to RM 918 * 919 * barSizes [OUT] 920 * This param provides the BAR size for each region index of the device 921 * 922 * sparseOffsets [OUT] 923 * This param provides the offset of each sparse mmap region in BAR0 924 * 925 * sparseSizes [OUT] 926 * This param provides the size of each sparse mmap region in BAR0 927 * 928 * sparseCount [OUT] 929 * This param provides the number of sparse mmap regions in BAR0 930 * 931 * isBar064bit [OUT] 932 * This param provides whether the BAR0 is 64bit of the vGPU device 933 * 934 * Possible status values returned are: 935 * NV_OK 936 * NV_ERR_OBJECT_NOT_FOUND 937 * NV_ERR_INVALID_ARGUMENT 938 */ 939 940 #define NVA081_CTRL_CMD_VGPU_GET_BAR_INFO (0xa0810121) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_GET_BAR_INFO_PARAMS_MESSAGE_ID" */ 941 942 #define NVA081_CTRL_VGPU_GET_BAR_INFO_PARAMS_MESSAGE_ID (0x21U) 943 944 typedef struct NVA081_CTRL_VGPU_GET_BAR_INFO_PARAMS { 945 NvU32 gpuPciId; 946 NvU8 vgpuName[VM_UUID_SIZE]; 947 NvU8 configParams[NVA081_CONFIG_PARAMS_MAX_LENGTH]; 948 NV_DECLARE_ALIGNED(NvU64 barSizes[NVA081_MAX_BAR_REGION_COUNT], 8); 949 NV_DECLARE_ALIGNED(NvU64 sparseOffsets[NVA081_MAX_SPARSE_REGION_COUNT], 8); 950 NV_DECLARE_ALIGNED(NvU64 sparseSizes[NVA081_MAX_SPARSE_REGION_COUNT], 8); 951 NvU32 sparseCount; 952 NvBool isBar064bit; 953 } NVA081_CTRL_VGPU_GET_BAR_INFO_PARAMS; 954 955 /* 956 * NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH 957 * 958 * This command is to get the migration bandwidth of the physical GPU. 959 * 960 * migrationBandwidth [OUT] 961 * This param specifies the migration bandwidth of GPU 962 * 963 * Possible status values returned are: 964 * NV_OK 965 * NV_ERR_INVALID_REQUEST 966 * NV_ERR_INVALID_STATE 967 * NV_ERR_INVALID_ARGUMENT 968 */ 969 #define NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH (0xa0810122) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS_MESSAGE_ID" */ 970 971 #define NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS_MESSAGE_ID (0x22U) 972 973 typedef struct NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS { 974 NvU32 migrationBandwidth; 975 } NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS; 976 977 /* _ctrlA081vgpuconfig_h_ */ 978