1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef DEV_P2060_H 25 #define DEV_P2060_H 26 27 #define NV_P2060_STATUS 0x00 /* R--1R */ 28 #define NV_P2060_STATUS_VAL 7:0 /* R-XVF */ 29 #define NV_P2060_STATUS_VCXO 1:0 /* R-XVF */ 30 #define NV_P2060_STATUS_VCXO_NOLOCK_TOO_FAST 0x00 /* R---V */ 31 #define NV_P2060_STATUS_VCXO_NOLOCK_TOO_SLOW 0x01 /* R---V */ 32 #define NV_P2060_STATUS_VCXO_LOCK 0x02 /* R---V */ 33 #define NV_P2060_STATUS_VCXO_NOT_SERVO 0x03 /* R---V */ 34 #define NV_P2060_STATUS_SYNC_LOSS 2:2 /* R-XVF */ 35 #define NV_P2060_STATUS_SYNC_LOSS_FALSE 0x00 /* R---V */ 36 #define NV_P2060_STATUS_SYNC_LOSS_TRUE 0x01 /* R---V */ 37 #define NV_P2060_STATUS_RESERVED1 3:3 /* RWXVF */ 38 #define NV_P2060_STATUS_GPU_STEREO 4:4 /* R-XVF */ 39 #define NV_P2060_STATUS_GPU_STEREO_NOT_ACTIVE 0x00 /* R---V */ 40 #define NV_P2060_STATUS_GPU_STEREO_ACTIVE 0x01 /* R---V */ 41 #define NV_P2060_STATUS_MSTR_STEREO 5:5 /* R-XVF */ 42 #define NV_P2060_STATUS_MSTR_STEREO_NOT_ACTIVE 0x00 /* R---V */ 43 #define NV_P2060_STATUS_MSTR_STEREO_ACTIVE 0x01 /* R---V */ 44 #define NV_P2060_STATUS_STEREO 6:6 /* R-XVF */ 45 #define NV_P2060_STATUS_STEREO_NOLOCK 0x00 /* R---V */ 46 #define NV_P2060_STATUS_STEREO_LOCK 0x01 /* R---V */ 47 #define NV_P2060_STATUS_RESERVED2 7:7 /* RWXVF */ 48 49 #define NV_P2060_STATUS2 0x01 /* RW-1R */ 50 #define NV_P2060_STATUS2_VAL 7:0 /* R-XVF */ 51 #define NV_P2060_STATUS2_PORT0 0:0 /* RWIVF */ 52 #define NV_P2060_STATUS2_PORT0_INPUT 0x00 /* RWI-V */ 53 #define NV_P2060_STATUS2_PORT0_OUTPUT 0x01 /* RW--V */ 54 #define NV_P2060_STATUS2_PORT1 1:1 /* RWIVF */ 55 #define NV_P2060_STATUS2_PORT1_INPUT 0x00 /* RWI-V */ 56 #define NV_P2060_STATUS2_PORT1_OUTPUT 0x01 /* RW--V */ 57 #define NV_P2060_STATUS2_ETHER0_DETECTED 2:2 /* RWIVF */ 58 #define NV_P2060_STATUS2_ETHER0_DETECTED_FALSE 0x00 /* RWI-V */ 59 #define NV_P2060_STATUS2_ETHER0_DETECTED_TRUE 0x01 /* R---V */ 60 #define NV_P2060_STATUS2_ETHER1_DETECTED 3:3 /* RWIVF */ 61 #define NV_P2060_STATUS2_ETHER1_DETECTED_FALSE 0x00 /* RWI-V */ 62 #define NV_P2060_STATUS2_ETHER1_DETECTED_TRUE 0x01 /* R---V */ 63 #define NV_P2060_STATUS2_HS_DETECT 5:4 /* RWXVF */ 64 #define NV_P2060_STATUS2_HS_DETECT_NONE 0x00 /* R---V */ 65 #define NV_P2060_STATUS2_HS_DETECT_TTL 0x01 /* R---V */ 66 #define NV_P2060_STATUS2_HS_DETECT_COMPOSITE 0x02 /* R---V */ 67 #define NV_P2060_STATUS2_HS_DETECT_NOT_IN_USE 0x03 /* R---V */ 68 #define NV_P2060_STATUS2_GPU_PORT 7:6 /* R-XVF */ 69 #define NV_P2060_STATUS2_GPU_PORT_CONN0 0x00 /* R---V */ 70 #define NV_P2060_STATUS2_GPU_PORT_CONN1 0x01 /* R---V */ 71 #define NV_P2060_STATUS2_GPU_PORT_CONN2 0x02 /* R---V */ 72 #define NV_P2060_STATUS2_GPU_PORT_CONN3 0x03 /* R---V */ 73 74 #define NV_P2060_STATUS3 0x02 /* RW-1R */ 75 #define NV_P2060_STATUS3_VAL 7:0 /* R-XVF */ 76 #define NV_P2060_STATUS3_RESERVED 0:0 /* R-XVF */ 77 #define NV_P2060_STATUS3_LB_INT_FAIL 1:1 /* R-XVF */ 78 #define NV_P2060_STATUS3_LB_INT_FAIL_FALSE 0x00 /* RW--V */ 79 #define NV_P2060_STATUS3_LB_INT_FAIL_TRUE 0x01 /* RW--V */ 80 #define NV_P2060_STATUS3_LB_VTGRST_FAIL 2:2 /* R-XVF */ 81 #define NV_P2060_STATUS3_LB_VTGRST_FAIL_FALSE 0x00 /* RW--V */ 82 #define NV_P2060_STATUS3_LB_VTGRST_FAIL_TRUE 0x01 /* RW--V */ 83 #define NV_P2060_STATUS3_LB_GSWPRDY_FAIL 3:3 /* R-XVF */ 84 #define NV_P2060_STATUS3_LB_GSWPRDY_FAIL_FALSE 0x00 /* RW--V */ 85 #define NV_P2060_STATUS3_LB_GSWPRDY_FAIL_TRUE 0x01 /* RW--V */ 86 #define NV_P2060_STATUS3_LB_SYNC_FAIL 4:4 /* RWXVF */ 87 #define NV_P2060_STATUS3_LB_SYNC_FAIL_FALSE 0x00 /* RW--V */ 88 #define NV_P2060_STATUS3_LB_SYNC_FAIL_TRUE 0x01 /* RW--V */ 89 #define NV_P2060_STATUS3_LB_STEREO_FAIL 5:5 /* RWXVF */ 90 #define NV_P2060_STATUS3_LB_STEREO_FAIL_FALSE 0x00 /* RW--V */ 91 #define NV_P2060_STATUS3_LB_STEREO_FAIL_TRUE 0x01 /* RW--V */ 92 #define NV_P2060_STATUS3_LB_SWPRDY_FAIL 6:6 /* RWXVF */ 93 #define NV_P2060_STATUS3_LB_SWPRDY_FAIL_FALSE 0x00 /* RW--V */ 94 #define NV_P2060_STATUS3_LB_SWPRDY_FAIL_TRUE 0x01 /* RW--V */ 95 #define NV_P2060_STATUS3_GENLOCKED 7:7 /* RWXVF */ 96 #define NV_P2060_STATUS3_GENLOCKED_FALSE 0x00 /* RW--V */ 97 #define NV_P2060_STATUS3_GENLOCKED_TRUE 0x01 /* RW--V */ 98 99 #define NV_P2060_STATUS4 0x13 /* RW-1R */ 100 #define NV_P2060_STATUS4_VAL 7:0 /* R-XVF */ 101 #define NV_P2060_STATUS4_INT_GROUP 7:6 /* R-XVF */ 102 #define NV_P2060_STATUS4_INT_GROUP_LOSS 0x00 /* R-XVF */ 103 #define NV_P2060_STATUS4_INT_GROUP_GAIN 0x01 /* R-XVF */ 104 #define NV_P2060_STATUS4_INT_GROUP_MISC 0x02 /* R-XVF */ 105 #define NV_P2060_STATUS4_SYNC 0:0 /* R---V */ 106 #define NV_P2060_STATUS4_STEREO 1:1 /* R---V */ 107 #define NV_P2060_STATUS4_HS 2:2 /* R---V */ 108 #define NV_P2060_STATUS4_RJ45 3:3 /* R---V */ 109 #define NV_P2060_STATUS4_RESERVED_GRP01 5:4 /* R---V */ 110 //Value 1 in bits 0-5 indicate loss and gain depending on interrupt group 00/01 (bit 6-7) 111 #define NV_P2060_STATUS4_FRM_CNT_MATCH_INT 0:0 /* R-XVF */ 112 #define NV_P2060_STATUS4_FRM_CNT_MATCH_INT_CLEAR 0x00 /* R---V */ 113 #define NV_P2060_STATUS4_FRM_CNT_MATCH_INT_PENDING 0x01 /* R---V */ 114 #define NV_P2060_STATUS4_SWAPRDY_INT 1:1 /* R-XVF */ 115 #define NV_P2060_STATUS4_SWAPRDY_INT_CLEAR 0x00 /* R---V */ 116 #define NV_P2060_STATUS4_SWAPRDY_INT_PENDING 0x01 /* R---V */ 117 #define NV_P2060_STATUS4_ERROR_INT 2:2 /* R-XVF */ 118 #define NV_P2060_STATUS4_ERROR_INT_CLEAR 0x00 /* R---V */ 119 #define NV_P2060_STATUS4_ERROR_INT_PENDING 0x01 /* R---V */ 120 #define NV_P2060_STATUS4_FRM_CNT_ROLLOVER_INT 3:3 /* R-XVF */ 121 #define NV_P2060_STATUS4_FRM_CNT_ROLLOVER_INT_CLEAR 0x00 /* R---V */ 122 #define NV_P2060_STATUS4_FRM_CNT_ROLLOVER_INT_PENDING 0x01 /* R---V */ 123 #define NV_P2060_STATUS4_RESERVED_GRP10 5:4 /* R---V */ 124 //Value 1 in bits 0-5 indicate interrupt pending depending on interrupt group 10 (bit 6-7) 125 126 #define NV_P2060_CONTROL 0x03 /* RW-1R */ 127 #define NV_P2060_CONTROL_I_AM 0:0 /* RWXVF */ 128 #define NV_P2060_CONTROL_I_AM_SLAVE 0x00 /* RWI-V */ 129 #define NV_P2060_CONTROL_I_AM_MASTER 0x01 /* RWI-V */ 130 #define NV_P2060_CONTROL_SYNC_POLARITY 2:1 /* RWXVF */ 131 #define NV_P2060_CONTROL_SYNC_POLARITY_RISING_EDGE 0x00 /* RW--V */ 132 #define NV_P2060_CONTROL_SYNC_POLARITY_FALLING_EDGE 0x01 /* RW--V */ 133 #define NV_P2060_CONTROL_SYNC_POLARITY_BOTH 0x02 /* RW--V */ 134 #define NV_P2060_CONTROL_TEST_MODE 3:3 /* RWXVF */ 135 #define NV_P2060_CONTROL_TEST_MODE_OFF 0x00 /* RW--V */ 136 #define NV_P2060_CONTROL_TEST_MODE_ON 0x01 /* RW--V */ 137 #define NV_P2060_CONTROL_SYNC_SRC 5:4 /* RWXVF */ 138 #define NV_P2060_CONTROL_SYNC_SRC_CONN0 0x00 /* RW--V */ 139 #define NV_P2060_CONTROL_SYNC_SRC_CONN1 0x01 /* RW--V */ 140 #define NV_P2060_CONTROL_SYNC_SRC_CONN2 0x02 /* RW--V */ 141 #define NV_P2060_CONTROL_SYNC_SRC_CONN3 0x03 /* RW--V */ 142 #define NV_P2060_CONTROL_INTERLACE_MODE 6:6 /* RWXVF */ 143 #define NV_P2060_CONTROL_INTERLACE_MODE_FALSE 0x00 /* RW--V */ 144 #define NV_P2060_CONTROL_INTERLACE_MODE_TRUE 0x01 /* RW--V */ 145 #define NV_P2060_CONTROL_SYNC_SELECT 7:7 /* RWXVF */ 146 #define NV_P2060_CONTROL_SYNC_SELECT_INTERNAL 0x00 /* RW--V */ 147 #define NV_P2060_CONTROL_SYNC_SELECT_HOUSE 0x01 /* RW--V */ 148 149 #define NV_P2060_CONTROL2 0x04 /* RW-1R */ 150 #define NV_P2060_CONTROL2_LAMUX 1:0 /* RWXVF */ 151 #define NV_P2060_CONTROL2_LAMUX_0 0x00 /* RWI-V */ 152 #define NV_P2060_CONTROL2_FRAMERATE_RPT 3:2 /* RWXVF */ 153 #define NV_P2060_CONTROL2_FRAMERATE_RPT_LIVE 0x00 /* RW--V */ 154 #define NV_P2060_CONTROL2_FRAMERATE_RPT_MIN 0x02 /* RW--V */ 155 #define NV_P2060_CONTROL2_FRAMERATE_RPT_MAX 0x03 /* RW--V */ 156 #define NV_P2060_CONTROL2_RESET 4:4 /* RWXVF */ 157 #define NV_P2060_CONTROL2_RESET_FALSE 0x00 /* RW--V */ 158 #define NV_P2060_CONTROL2_RESET_TRUE 0x01 /* RW--V */ 159 #define NV_P2060_CONTROL2_SWAP_READY 5:5 /* RWXVF */ 160 #define NV_P2060_CONTROL2_SWAP_READY_DISABLE 0x00 /* RW--V */ 161 #define NV_P2060_CONTROL2_SWAP_READY_ENABLE 0x01 /* RW--V */ 162 #define NV_P2060_CONTROL2_RESERVED 6:6 /* RWXVF */ 163 #define NV_P2060_CONTROL2_LOOPBACK_MODE 7:7 /* RWXVF */ 164 #define NV_P2060_CONTROL2_LOOPBACK_MODE_OFF 0x00 /* RW--V */ 165 #define NV_P2060_CONTROL2_LOOPBACK_MODE_ON 0x01 /* RW--V */ 166 167 #define NV_P2060_CONTROL3 0x05 /* RW-1R */ 168 #define NV_P2060_CONTROL3_INTERRUPT 6:0 /* RWXVF */ 169 #define NV_P2060_CONTROL3_INTERRUPT_DISABLE 0x00 /* RW--V */ 170 #define NV_P2060_CONTROL3_INTERRUPT_ON_STEREO_CHG 0x01 /* RW--V */ 171 #define NV_P2060_CONTROL3_INTERRUPT_ON_ERROR 0x02 /* RW--V */ 172 #define NV_P2060_CONTROL3_INTERRUPT_ON_FRAME_MATCH 0x04 /* RW--V */ 173 #define NV_P2060_CONTROL3_INTERRUPT_ON_HS_CHG 0x08 /* RW--V */ 174 #define NV_P2060_CONTROL3_INTERRUPT_ON_SYNC_CHG 0x10 /* RW--V */ 175 #define NV_P2060_CONTROL3_INTERRUPT_ON_RJ45_CHG 0x20 /* RW--V */ 176 #define NV_P2060_CONTROL3_INTERRUPT_ON_ALL 0x7f /* RW--V */ 177 #define NV_P2060_CONTROL3_RESYNC 7:7 /* RWXVF */ 178 #define NV_P2060_CONTROL3_RESYNC_OFF 0x00 /* RW--V */ 179 #define NV_P2060_CONTROL3_RESYNC_ON 0x01 /* RW--V */ 180 181 #define NV_P2060_CONTROL4 0x06 /* RW-1R */ 182 #define NV_P2060_CONTROL4_SWPRDYINT_DELAY 2:0 /* RWXVF */ 183 #define NV_P2060_CONTROL4_STEREO_LOCK_MODE 3:3 /* RWXVF */ 184 #define NV_P2060_CONTROL4_STEREO_LOCK_MODE_OFF 0x00 /* RW--V */ 185 #define NV_P2060_CONTROL4_STEREO_LOCK_MODE_ON 0x01 /* RW--V */ 186 #define NV_P2060_CONTROL4_EXT_STEREO_SYNC 4:4 /* RWXVF */ 187 #define NV_P2060_CONTROL4_EXT_STEREO_SYNC_OFF 0x00 /* RW--V */ 188 #define NV_P2060_CONTROL4_EXT_STEREO_SYNC_ON 0x01 /* RW--V */ 189 #define NV_P2060_CONTROL4_EXT_STEREO_SYNC_POL 5:5 /* RWXVF */ 190 #define NV_P2060_CONTROL4_EXT_STEREO_SYNC_POL_LOW 0x00 /* RW--V */ 191 #define NV_P2060_CONTROL4_EXT_STEREO_SYNC_POL_HI 0x01 /* RW--V */ 192 #define NV_P2060_CONTROL4_RESERVED2 7:6 /* RWXVF */ 193 194 #define NV_P2060_FPGA 0x07 /* R--1R */ 195 #define NV_P2060_FPGA_REV 3:0 /* R-XVF */ 196 197 #define NV_P2060_FPGA_ID 7:4 /* R-XVF */ 198 #define NV_P2060_FPGA_ID_0 0x00 /* R---V */ 199 #define NV_P2060_FPGA_ID_5 0x05 /* R---V */ 200 201 #define NV_P2061_FPGA_ID 7:4 /* R-XVF */ 202 #define NV_P2061_FPGA_ID_4 0x04 /* R---V */ 203 204 #define NV_P2060_SYNC_SKEW_LOW 0x08 /* RW-1R */ 205 #define NV_P2060_SYNC_SKEW_LOW_VAL 7:0 /* RWIVF */ 206 #define NV_P2060_SYNC_SKEW_LOW_VAL_0 0x00 /* RWI-V */ 207 208 #define NV_P2060_SYNC_SKEW_HIGH 0x09 /* RW-1R */ 209 #define NV_P2060_SYNC_SKEW_HIGH_VAL 7:0 /* RWIVF */ 210 #define NV_P2060_SYNC_SKEW_HIGH_VAL_0 0x00 /* RWI-V */ 211 212 #define NV_P2060_SYNC_SKEW_UPPER 0x35 /* RW-1R */ 213 #define NV_P2060_SYNC_SKEW_UPPER_VAL 7:0 /* RWIVF */ 214 #define NV_P2060_SYNC_SKEW_UPPER_VAL_0 0x00 /* RWI-V */ 215 216 #define NV_P2060_START_DELAY_LOW 0x0A /* RW-1R */ 217 #define NV_P2060_START_DELAY_LOW_VAL 7:0 /* RWIVF */ 218 #define NV_P2060_START_DELAY_LOW_VAL_0 0x00 /* RWI-V */ 219 220 #define NV_P2060_START_DELAY_HIGH 0x0B /* RW-1R */ 221 #define NV_P2060_START_DELAY_HIGH_VAL 7:0 /* RWIVF */ 222 #define NV_P2060_START_DELAY_HIGH_VAL_0 0x00 /* RWI-V */ 223 224 #define NV_P2060_NSYNC 0x0C /* RW-1R */ 225 #define NV_P2060_NSYNC_FL 2:0 /* RWIVF */ 226 #define NV_P2060_NSYNC_GPU 6:4 /* RWIVF */ 227 #define NV_P2060_NSYNC_ALL 7:0 /* RWIVF */ 228 229 #define NV_P2060_FRAMECNTR_LOW 0x0D /* R--1R */ 230 #define NV_P2060_FRAMECNTR_LOW_VAL 7:0 /* RWIVF */ 231 #define NV_P2060_FRAMECNTR_LOW_VAL_0 0x00 /* RWI-V */ 232 233 #define NV_P2060_FRAMECNTR_MID 0x0E /* R--1R */ 234 #define NV_P2060_FRAMECNTR_MID_VAL 7:0 /* RWIVF */ 235 #define NV_P2060_FRAMECNTR_MID_VAL_0 0x00 /* RWI-V */ 236 237 #define NV_P2060_FRAMECNTR_HIGH 0x0F /* R--1R */ 238 #define NV_P2060_FRAMECNTR_HIGH_VAL 7:0 /* RWIVF */ 239 #define NV_P2060_FRAMECNTR_HIGH_VAL_0 0x00 /* RWI-V */ 240 241 #define NV_P2060_FRAMERATE_LOW 0x10 /* R--1R */ 242 #define NV_P2060_FRAMERATE_LOW_VAL 7:0 /* RWIVF */ 243 #define NV_P2060_FRAMERATE_LOW_VAL_0 0x00 /* RWI-V */ 244 245 #define NV_P2060_FRAMERATE_MID 0x11 /* R--1R */ 246 #define NV_P2060_FRAMERATE_MID_VAL 7:0 /* RWIVF */ 247 #define NV_P2060_FRAMERATE_MID_VAL_0 0x00 /* RWI-V */ 248 249 #define NV_P2060_FRAMERATE_HIGH 0x12 /* R--1R */ 250 #define NV_P2060_FRAMERATE_HIGH_VAL 7:0 /* RWIVF */ 251 #define NV_P2060_FRAMERATE_HIGH_VAL_0 0x00 /* RWI-V */ 252 253 #define NV_P2060_FPGA_EXREV 0x17 /* R--1R */ 254 #define NV_P2060_FPGA_EXREV_VAL 7:0 /* RWIVF */ 255 #define NV_P2060_FPGA_EXREV_VAL_0 0x00 /* RWI-V */ 256 257 #define NV_P2060_FPGA_ASGN_ID_0 0x18 /* R--1R */ 258 #define NV_P2060_FPGA_ASGN_ID_0_VAL 7:0 /* RWIVF */ 259 #define NV_P2060_FPGA_ASGN_ID_1 0x19 /* R--1R */ 260 #define NV_P2060_FPGA_ASGN_ID_1_VAL 7:0 /* RWIVF */ 261 #define NV_P2060_FPGA_ASGN_ID_2 0x1A /* R--1R */ 262 #define NV_P2060_FPGA_ASGN_ID_2_VAL 7:0 /* RWIVF */ 263 #define NV_P2060_FPGA_ASGN_ID_3 0x1B /* R--1R */ 264 #define NV_P2060_FPGA_ASGN_ID_3_VAL 7:0 /* RWIVF */ 265 266 #define NV_P2060_FPGA_ASGN_ID(i) (0x18 + i) 267 268 #define NV_P2060_FRAME_CMPR_LOW 0x1D /* R--1R */ 269 #define NV_P2060_FRAME_CMPR_LOW_VAL 7:0 /* RWIVF */ 270 #define NV_P2060_FRAME_CMPR_LOW_VAL_0 0x00 /* RWI-V */ 271 272 #define NV_P2060_FRAME_CMPR_MID 0x1E /* R--1R */ 273 #define NV_P2060_FRAME_CMPR_MID_VAL 7:0 /* RWIVF */ 274 #define NV_P2060_FRAME_CMPR_MID_VAL_0 0x00 /* RWI-V */ 275 276 #define NV_P2060_FRAME_CMPR_HIGH 0x1F /* R--1R */ 277 #define NV_P2060_FRAME_CMPR_HIGH_VAL 7:0 /* RWIVF */ 278 #define NV_P2060_FRAME_CMPR_HIGH_VAL_0 0x00 /* RWI-V */ 279 280 #define NV_P2060_HS_FRAMERATE_LOW 0x20 /* R--1R */ 281 #define NV_P2060_HS_FRAMERATE_LOW_VAL 7:0 /* RWIVF */ 282 #define NV_P2060_HS_FRAMERATE_LOW_VAL_0 0x00 /* RWI-V */ 283 284 #define NV_P2060_HS_FRAMERATE_MID 0x21 /* R--1R */ 285 #define NV_P2060_HS_FRAMERATE_MID_VAL 7:0 /* RWIVF */ 286 #define NV_P2060_HS_FRAMERATE_MID_VAL_0 0x00 /* RWI-V */ 287 288 #define NV_P2060_HS_FRAMERATE_HIGH 0x22 /* R--1R */ 289 #define NV_P2060_HS_FRAMERATE_HIGH_VAL 7:0 /* RWIVF */ 290 #define NV_P2060_HS_FRAMERATE_HIGH_VAL_0 0x00 /* RWI-V */ 291 292 #define NV_P2060_MOSAIC_MODE 0x23 /* RW-1R */ 293 #define NV_P2060_MOSAIC_MODE_TS 1:0 /* RWIVF */ 294 #define NV_P2060_MOSAIC_MODE_TS_CONN0 0x00 /* R---V */ 295 #define NV_P2060_MOSAIC_MODE_TS_CONN1 0x01 /* RW--V */ 296 #define NV_P2060_MOSAIC_MODE_TS_CONN2 0x02 /* RW--V */ 297 #define NV_P2060_MOSAIC_MODE_TS_CONN3 0x03 /* RW--V */ 298 #define NV_P2060_MOSAIC_MODE_GROUP 2:2 /* RWIVF */ 299 #define NV_P2060_MOSAIC_MODE_GROUP_ZERO 0x00 /* RW--V */ 300 #define NV_P2060_MOSAIC_MODE_GROUP_ONE 0x01 /* RW--V */ 301 #define NV_P2060_MOSAIC_MODE_ENABLE 3:3 /* RWIVF */ 302 #define NV_P2060_MOSAIC_MODE_ENABLE_FALSE 0x00 /* RW--V */ 303 #define NV_P2060_MOSAIC_MODE_ENABLE_TRUE 0x01 /* RW--V */ 304 #define NV_P2060_MOSAIC_MODE_RESERVED 7:4 /* RWIVF */ 305 306 #define NV_P2060_MULTIPLIER_DIVIDER 0x2F /* RW-1R */ 307 #define NV_P2060_MULTIPLIER_DIVIDER_VALUE_MINUS_ONE 2:0 /* RWIVF */ 308 #define NV_P2060_MULTIPLIER_DIVIDER_VALUE_MINUS_ONE_MAX 0x7 309 #define NV_P2060_MULTIPLIER_DIVIDER_MODE 7:7 /* RWIVF */ 310 #define NV_P2060_MULTIPLIER_DIVIDER_MODE_MULTIPLY 0x0 /* RWIVF */ 311 #define NV_P2060_MULTIPLIER_DIVIDER_MODE_DIVIDE 0x1 /* RWIVF */ 312 313 #endif //DEV_P2060_H 314 315