1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef __tu102_dev_boot_h__ 25 #define __tu102_dev_boot_h__ 26 #define NV_PMC_INTR(i) (0x00000100+(i)*4) /* RW-4A */ 27 #define NV_PMC_INTR_EN(i) (0x00000140+(i)*4) /* R--4A */ 28 #define NV_PMC_INTR_EN__SIZE_1 2 /* */ 29 #define NV_PMC_INTR_EN_DEVICE(i) (i):(i) /* */ 30 #define NV_PMC_INTR_EN_DEVICE__SIZE_1 32 /* */ 31 #define NV_PMC_INTR_EN_DEVICE_DISABLED 0x00000000 /* */ 32 #define NV_PMC_INTR_EN_DEVICE_ENABLED 0x00000001 /* */ 33 #define NV_PMC_INTR_EN_VALUE 31:0 /* R-IVF */ 34 #define NV_PMC_INTR_EN_VALUE_INIT 0x00000000 /* R-I-V */ 35 #define NV_PMC_INTR_EN_SET(i) (0x00000160+(i)*4) /* -W-4A */ 36 #define NV_PMC_INTR_EN_SET__SIZE_1 2 /* */ 37 #define NV_PMC_INTR_EN_SET_DEVICE(i) (i):(i) /* */ 38 #define NV_PMC_INTR_EN_SET_DEVICE__SIZE_1 32 /* */ 39 #define NV_PMC_INTR_EN_SET_DEVICE_SET 0x00000001 /* */ 40 #define NV_PMC_INTR_EN_SET_VALUE 31:0 /* -W-VF */ 41 #define NV_PMC_INTR_EN_CLEAR(i) (0x00000180+(i)*4) /* -W-4A */ 42 #define NV_PMC_INTR_EN_CLEAR__SIZE_1 2 /* */ 43 #define NV_PMC_INTR_EN_CLEAR_DEVICE(i) (i):(i) /* */ 44 #define NV_PMC_INTR_EN_CLEAR_DEVICE__SIZE_1 32 /* */ 45 #define NV_PMC_INTR_EN_CLEAR_DEVICE_SET 0x00000001 /* */ 46 #define NV_PMC_INTR_EN_CLEAR_VALUE 31:0 /* -W-VF */ 47 #define NV_PMC_ENABLE 0x00000200 /* RW-4R */ 48 #define NV_PMC_ENABLE_DEVICE(i) (i):(i) /* */ 49 #define NV_PMC_ENABLE_DEVICE__SIZE_1 32 /* */ 50 #define NV_PMC_ENABLE_DEVICE_DISABLE 0x00000000 /* */ 51 #define NV_PMC_ENABLE_DEVICE_ENABLE 0x00000001 /* */ 52 #define NV_PMC_ENABLE_PMEDIA 4:4 /* */ 53 #define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */ 54 #define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */ 55 #define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */ 56 #define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */ 57 #define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */ 58 #define NV_PMC_ENABLE_PWR 13:13 /* */ 59 #define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */ 60 #define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */ 61 #define NV_PMC_ENABLE_CE0 6:6 /* */ 62 #define NV_PMC_ENABLE_CE0_DISABLED 0x00000000 /* */ 63 #define NV_PMC_ENABLE_CE0_ENABLED 0x00000001 /* */ 64 #define NV_PMC_ENABLE_CE1 7:7 /* */ 65 #define NV_PMC_ENABLE_CE1_DISABLED 0x00000000 /* */ 66 #define NV_PMC_ENABLE_CE1_ENABLED 0x00000001 /* */ 67 #define NV_PMC_ENABLE_CE2 21:21 /* */ 68 #define NV_PMC_ENABLE_CE2_DISABLED 0x00000000 /* */ 69 #define NV_PMC_ENABLE_CE2_ENABLED 0x00000001 /* */ 70 #define NV_PMC_ENABLE_CE3 22:22 /* */ 71 #define NV_PMC_ENABLE_CE3_DISABLED 0x00000000 /* */ 72 #define NV_PMC_ENABLE_CE3_ENABLED 0x00000001 /* */ 73 #define NV_PMC_ENABLE_CE4 23:23 /* */ 74 #define NV_PMC_ENABLE_CE4_DISABLED 0x00000000 /* */ 75 #define NV_PMC_ENABLE_CE4_ENABLED 0x00000001 /* */ 76 #define NV_PMC_ENABLE_CE5 24:24 /* */ 77 #define NV_PMC_ENABLE_CE5_DISABLED 0x00000000 /* */ 78 #define NV_PMC_ENABLE_CE5_ENABLED 0x00000001 /* */ 79 #define NV_PMC_ENABLE_CE6 9:9 /* */ 80 #define NV_PMC_ENABLE_CE6_DISABLED 0x00000000 /* */ 81 #define NV_PMC_ENABLE_CE6_ENABLED 0x00000001 /* */ 82 #define NV_PMC_ENABLE_CE7 10:10 /* */ 83 #define NV_PMC_ENABLE_CE7_DISABLED 0x00000000 /* */ 84 #define NV_PMC_ENABLE_CE7_ENABLED 0x00000001 /* */ 85 #define NV_PMC_ENABLE_CE8 11:11 /* */ 86 #define NV_PMC_ENABLE_CE8_DISABLED 0x00000000 /* */ 87 #define NV_PMC_ENABLE_CE8_ENABLED 0x00000001 /* */ 88 #define NV_PMC_ENABLE_PGRAPH 12:12 /* */ 89 #define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* */ 90 #define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* */ 91 #define NV_PMC_ENABLE_SEC 14:14 /* */ 92 #define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */ 93 #define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */ 94 #define NV_PMC_ENABLE_NVDEC 15:15 /* */ 95 #define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */ 96 #define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */ 97 #define NV_PMC_ENABLE_NVDEC0 15:15 /* */ 98 #define NV_PMC_ENABLE_NVDEC0_DISABLED 0x00000000 /* */ 99 #define NV_PMC_ENABLE_NVDEC0_ENABLED 0x00000001 /* */ 100 #define NV_PMC_ENABLE_NVDEC1 16:16 /* */ 101 #define NV_PMC_ENABLE_NVDEC1_DISABLED 0x00000000 /* */ 102 #define NV_PMC_ENABLE_NVDEC1_ENABLED 0x00000001 /* */ 103 #define NV_PMC_ENABLE_NVDEC2 20:20 /* */ 104 #define NV_PMC_ENABLE_NVENC0 18:18 /* */ 105 #define NV_PMC_ENABLE_NVENC0_DISABLED 0x00000000 /* */ 106 #define NV_PMC_ENABLE_NVENC0_ENABLED 0x00000001 /* */ 107 #define NV_PMC_ENABLE_NVENC1 19:19 /* */ 108 #define NV_PMC_ENABLE_NVENC1_DISABLED 0x00000000 /* */ 109 #define NV_PMC_ENABLE_NVENC1_ENABLED 0x00000001 /* */ 110 #define NV_PMC_ENABLE_NVDEC2 20:20 /* */ 111 #define NV_PMC_ENABLE_NVDEC2_DISABLED 0x00000000 /* */ 112 #define NV_PMC_ENABLE_NVDEC2_ENABLED 0x00000001 /* */ 113 #define NV_PMC_ENABLE_PERFMON 28:28 /* RWIVF */ 114 #define NV_PMC_ENABLE_PERFMON_DISABLED 0x00000000 /* RWI-V */ 115 #define NV_PMC_ENABLE_PERFMON_ENABLED 0x00000001 /* RW--V */ 116 #define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */ 117 #define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */ 118 #define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */ 119 #define NV_PMC_ENABLE_NVJPG0 31:31 /* */ 120 #define NV_PMC_ENABLE_NVJPG0_DISABLED 0x00000000 /* */ 121 #define NV_PMC_ENABLE_NVJPG0_ENABLED 0x00000001 /* */ 122 #endif // __tu102_dev_boot_h__ 123