1
2 #ifndef _G_OS_NVOC_H_
3 #define _G_OS_NVOC_H_
4 #include "nvoc/runtime.h"
5
6 // Version of generated metadata structures
7 #ifdef NVOC_METADATA_VERSION
8 #undef NVOC_METADATA_VERSION
9 #endif
10 #define NVOC_METADATA_VERSION 0
11
12 #ifdef __cplusplus
13 extern "C" {
14 #endif
15
16 /*
17 * SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
18 * SPDX-License-Identifier: MIT
19 *
20 * Permission is hereby granted, free of charge, to any person obtaining a
21 * copy of this software and associated documentation files (the "Software"),
22 * to deal in the Software without restriction, including without limitation
23 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
24 * and/or sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following conditions:
26 *
27 * The above copyright notice and this permission notice shall be included in
28 * all copies or substantial portions of the Software.
29 *
30 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
31 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
32 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
33 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
34 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
35 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
36 * DEALINGS IN THE SOFTWARE.
37 */
38
39 #pragma once
40 #include "g_os_nvoc.h"
41
42
43 #ifndef _OS_H_
44 #define _OS_H_
45
46 /*!
47 * @file os.h
48 * @brief Interface for Operating System module
49 */
50
51 /* ------------------------ Core & Library Includes ------------------------- */
52 #include "core/core.h"
53 #include "containers/btree.h"
54 #include "ctrl/ctrl0073/ctrl0073dfp.h"
55
56 /* ------------------------ SDK & Interface Includes ------------------------ */
57 #include "nvsecurityinfo.h"
58 #include "nvacpitypes.h"
59 #include "nvimpshared.h" // TODO - should move from sdk to resman/interface
60 #include "nvi2c.h" // TODO - should move from sdk to resman/interface
61
62 /* ------------------------ OS Includes ------------------------------------- */
63 #include "os/nv_memory_type.h"
64 #include "os/capability.h"
65
66 /* ------------------------ Forward Declarations ---------------------------- */
67
68 struct OBJOS;
69
70 #ifndef __NVOC_CLASS_OBJOS_TYPEDEF__
71 #define __NVOC_CLASS_OBJOS_TYPEDEF__
72 typedef struct OBJOS OBJOS;
73 #endif /* __NVOC_CLASS_OBJOS_TYPEDEF__ */
74
75 #ifndef __nvoc_class_id_OBJOS
76 #define __nvoc_class_id_OBJOS 0xaa1d70
77 #endif /* __nvoc_class_id_OBJOS */
78
79
80
81 //
82 // The OS module should NOT depend on RM modules. The only exception is
83 // core/core.h.
84 //
85 // DO NOT ADD INCLUDES TO RM MODULE HEADERS FROM THIS FILE. OS module should be
86 // a leaf module. Dependencies on RM headers in this files results in circular
87 // dependencies as most modules depend on the OS module.
88 //
89 // Ideally, all types used by the OS module's interface are from the SDK,
90 // resman/interface or self-contained within the OS module header. For now,
91 // since the OS module depends on a few RM internal types we forward declare to
92 // avoid the need to pull in headers from across RM.
93 //
94 typedef struct SYS_STATIC_CONFIG SYS_STATIC_CONFIG;
95 typedef struct MEMORY_DESCRIPTOR MEMORY_DESCRIPTOR;
96 typedef struct IOVAMAPPING *PIOVAMAPPING;
97 typedef struct OBJGPUMGR OBJGPUMGR;
98 typedef struct EVENTNOTIFICATION EVENTNOTIFICATION, *PEVENTNOTIFICATION;
99 typedef struct DEVICE_MAPPING DEVICE_MAPPING;
100 typedef void *PUID_TOKEN;
101 typedef struct OBJTMR OBJTMR;
102 typedef struct OBJCL OBJCL;
103 typedef struct _GUID *LPGUID;
104
105 //
106 // Forward declare OS_GPU_INFO type
107 //
108 // TODO - We shouldn't need a special definition per-OS. OS implementations
109 // should use a consistent type
110 //
111 typedef struct nv_state_t OS_GPU_INFO;
112
113 /* ------------------------ OS Interface ------------------------------------ */
114
115 typedef struct os_wait_queue OS_WAIT_QUEUE;
116
117 //
118 // Defines and Typedefs used by the OS
119 //
120 typedef NvU64 OS_THREAD_HANDLE;
121
122 //
123 // Forward references for OS1HZTIMERENTRY symbols
124 //
125 typedef struct OS1HZTIMERENTRY *POS1HZTIMERENTRY;
126 typedef struct OS1HZTIMERENTRY OS1HZTIMERENTRY;
127
128 //
129 // Simple 1 second callback facility. Schedules the given routine to be called with the supplied data
130 // in approximately 1 second. Might be called from an elevated IRQL.
131 // Unlike the tmr facilities (tmrScheduleCallbackXXX), this does not rely on the hardware.
132 //
133 typedef void (*OS1HZPROC)(OBJGPU *, void *);
134
135 #define NV_OS_1HZ_ONESHOT 0x00000000
136 #define NV_OS_1HZ_REPEAT 0x00000001
137
138 struct OS1HZTIMERENTRY
139 {
140 OS1HZPROC callback;
141 void* data;
142 NvU32 flags;
143 POS1HZTIMERENTRY next;
144 };
145
146 typedef struct RM_PAGEABLE_SECTION {
147 void *osHandle; // handle returned from OS API
148 void *pDataSection; // pointer to a date inside the target data/bss/const segment
149 } RM_PAGEABLE_SECTION;
150
151
152 // OSPollHotkeyState return values
153 #define NV_OS_HOTKEY_STATE_DISPLAY_CHANGE 0:0
154 #define NV_OS_HOTKEY_STATE_DISPLAY_CHANGE_NOT_FOUND 0x00000000
155 #define NV_OS_HOTKEY_STATE_DISPLAY_CHANGE_FOUND 0x00000001
156 #define NV_OS_HOTKEY_STATE_SCALE_EVENT 1:1
157 #define NV_OS_HOTKEY_STATE_SCALE_EVENT_NOT_FOUND 0x00000000
158 #define NV_OS_HOTKEY_STATE_SCALE_EVENT_FOUND 0x00000001
159 #define NV_OS_HOTKEY_STATE_LID_EVENT 2:2
160 #define NV_OS_HOTKEY_STATE_LID_EVENT_NOT_FOUND 0x00000000
161 #define NV_OS_HOTKEY_STATE_LID_EVENT_FOUND 0x00000001
162 #define NV_OS_HOTKEY_STATE_POWER_EVENT 3:3
163 #define NV_OS_HOTKEY_STATE_POWER_EVENT_NOT_FOUND 0x00000000
164 #define NV_OS_HOTKEY_STATE_POWER_EVENT_FOUND 0x00000001
165 #define NV_OS_HOTKEY_STATE_DOCK_EVENT 4:4
166 #define NV_OS_HOTKEY_STATE_DOCK_EVENT_NOT_FOUND 0x00000000
167 #define NV_OS_HOTKEY_STATE_DOCK_EVENT_FOUND 0x00000001
168
169 #define MAX_BRIGHTNESS_BCL_ELEMENTS 103
170
171 // ACPI _DOD Bit defines
172 // These bits are defined in the Hybrid SAS
173 #define NV_ACPI_DOD_DISPLAY_OWNER 20:18
174 #define NV_ACPI_DOD_DISPLAY_OWNER_ALL 0x00000000
175 #define NV_ACPI_DOD_DISPLAY_OWNER_MGPU 0x00000001
176 #define NV_ACPI_DOD_DISPLAY_OWNER_DGPU1 0x00000002
177
178 // ACPI 3.0a definitions for requested data length
179 #define NV_ACPI_DDC_REQUESTED_DATA_LENGTH_128B 0x00000001
180 #define NV_ACPI_DDC_REQUESTED_DATA_LENGTH_256B 0x00000002
181 #define NV_ACPI_DDC_REQUESTED_DATA_LENGTH_384B 0x00000003
182 #define NV_ACPI_DDC_REQUESTED_DATA_LENGTH_512B 0x00000004
183 #define NV_ACPI_DDC_REQUESTED_DATA_LENGTH_DEFAULT 0x00000001
184
185 // osBugCheck bugcode defines
186 #define OS_BUG_CHECK_BUGCODE_UNKNOWN (0)
187 #define OS_BUG_CHECK_BUGCODE_INTERNAL_TEST (1)
188 #define OS_BUG_CHECK_BUGCODE_BUS (2)
189 #define OS_BUG_CHECK_BUGCODE_ECC_DBE (3)
190 #define OS_BUG_CHECK_BUGCODE_NVLINK_TL_ERR (4)
191 #define OS_BUG_CHECK_BUGCODE_PAGED_SEGMENT (5)
192 #define OS_BUG_CHECK_BUGCODE_BSOD_ON_ASSERT (6)
193 #define OS_BUG_CHECK_BUGCODE_DISPLAY_UNDERFLOW (7)
194 #define OS_BUG_CHECK_BUGCODE_LAST OS_BUG_CHECK_BUGCODE_DISPLAY_UNDERFLOW
195
196 #define OS_BUG_CHECK_BUGCODE_STR \
197 { \
198 "Unknown Error", \
199 "Nv Internal Testing", \
200 "Bus Error", \
201 "Double Bit Error", \
202 "NVLink TL Error", \
203 "Invalid Bindata Access", \
204 "BSOD on Assert or Breakpoint", \
205 "Display Underflow" \
206 }
207
208 // Flags needed by OSAllocPagesNode
209 #define OS_ALLOC_PAGES_NODE_NONE 0x0
210 #define OS_ALLOC_PAGES_NODE_SKIP_RECLAIM 0x1
211
212 //
213 // Structures for osPackageRegistry and osUnpackageRegistry
214 //
215 typedef struct PACKED_REGISTRY_ENTRY
216 {
217 NvU32 nameOffset;
218 NvU8 type;
219 NvU32 data;
220 NvU32 length;
221 } PACKED_REGISTRY_ENTRY;
222
223 typedef struct PACKED_REGISTRY_TABLE
224 {
225 NvU32 size;
226 NvU32 numEntries;
227 PACKED_REGISTRY_ENTRY entries[0];
228 } PACKED_REGISTRY_TABLE;
229
230 // TODO: Merge with NV_REGISTRY_ENTRY_TYPE
231 //
232 // Values for PACKED_REGISTRY_ENTRY::type
233 //
234 #define REGISTRY_TABLE_ENTRY_TYPE_UNKNOWN 0
235 #define REGISTRY_TABLE_ENTRY_TYPE_DWORD 1
236 #define REGISTRY_TABLE_ENTRY_TYPE_BINARY 2
237 #define REGISTRY_TABLE_ENTRY_TYPE_STRING 3
238
239 typedef enum
240 {
241 NV_REGISTRY_ENTRY_TYPE_UNKNOWN = 0,
242 NV_REGISTRY_ENTRY_TYPE_DWORD,
243 NV_REGISTRY_ENTRY_TYPE_BINARY,
244 NV_REGISTRY_ENTRY_TYPE_STRING
245 } nv_reg_type_t;
246
247 /*
248 * nv_reg_entry_t
249 *
250 * regParmStr/regName
251 * Name of key
252 * type
253 * One of nv_reg_type_t enum
254 * data
255 * Integer data of key. Only used with DWORD type
256 * pdata
257 * Pointer to data of key. Only used with BINARY or STRING type
258 * len
259 * Length of pdata buffer. Only used with BINARY or STRING type
260 * next
261 * Next entry in linked list
262 */
263 typedef struct nv_reg_entry_s
264 {
265 char *regParmStr;
266 NvU32 type;
267 NvU32 data;
268 NvU8 *pdata;
269 NvU32 len;
270 struct nv_reg_entry_s *next;
271 } nv_reg_entry_t;
272
273 /*
274 * OS_DRIVER_BLOCK
275 *
276 * driverStart
277 * CPU VA of where the driver is loaded
278 * unique_id
279 * Debug GUID of the Driver. Used to match with Pdb
280 * age
281 * Additional GUID information
282 * offset
283 * Offset from VA to start of text
284 */
285 typedef struct {
286 NvP64 driverStart NV_ALIGN_BYTES(8);
287 NvU8 unique_id[16];
288 NvU32 age;
289 NvU32 offset;
290 } OS_DRIVER_BLOCK;
291
292 // Basic OS interface functions
293 typedef NvU32 OSSetEvent(OBJGPU *, NvP64);
294 typedef NV_STATUS OSEventNotification(OBJGPU *, PEVENTNOTIFICATION, NvU32, void *, NvU32);
295 typedef NV_STATUS OSEventNotificationWithInfo(OBJGPU *, PEVENTNOTIFICATION, NvU32, NvU32, NvU16, void *, NvU32);
296 typedef NV_STATUS OSObjectEventNotification(NvHandle, NvHandle, NvU32, PEVENTNOTIFICATION, NvU32, void *, NvU32);
297 typedef NV_STATUS NV_FORCERESULTCHECK OSAllocPages(MEMORY_DESCRIPTOR *);
298 typedef NV_STATUS NV_FORCERESULTCHECK OSAllocPagesInternal(MEMORY_DESCRIPTOR *);
299 typedef void OSFreePages(MEMORY_DESCRIPTOR *);
300 typedef void OSFreePagesInternal(MEMORY_DESCRIPTOR *);
301 typedef NV_STATUS NV_FORCERESULTCHECK OSLockMem(MEMORY_DESCRIPTOR *);
302 typedef NV_STATUS OSUnlockMem(MEMORY_DESCRIPTOR *);
303 typedef NV_STATUS NV_FORCERESULTCHECK OSMapGPU(OBJGPU *, RS_PRIV_LEVEL, NvU64, NvU64, NvU32, NvP64 *, NvP64 *);
304 typedef void OSUnmapGPU(OS_GPU_INFO *, RS_PRIV_LEVEL, NvP64, NvU64, NvP64);
305 typedef NV_STATUS NV_FORCERESULTCHECK OSNotifyEvent(OBJGPU *, PEVENTNOTIFICATION, NvU32, NvU32, NV_STATUS);
306 typedef NV_STATUS OSReadRegistryString(OBJGPU *, const char *, NvU8 *, NvU32 *);
307 typedef NV_STATUS OSWriteRegistryBinary(OBJGPU *, const char *, NvU8 *, NvU32);
308 typedef NV_STATUS OSWriteRegistryVolatile(OBJGPU *, const char *, NvU8 *, NvU32);
309 typedef NV_STATUS OSReadRegistryVolatile(OBJGPU *, const char *, NvU8 *, NvU32);
310 typedef NV_STATUS OSReadRegistryVolatileSize(OBJGPU *, const char *, NvU32 *);
311 typedef NV_STATUS OSReadRegistryBinary(OBJGPU *, const char *, NvU8 *, NvU32 *);
312 typedef NV_STATUS OSWriteRegistryDword(OBJGPU *, const char *, NvU32);
313 typedef NV_STATUS OSReadRegistryDword(OBJGPU *, const char *, NvU32 *);
314 typedef NV_STATUS OSReadRegistryDwordBase(OBJGPU *, const char *, NvU32 *);
315 typedef NV_STATUS OSReadRegistryStringBase(OBJGPU *, const char *, NvU8 *, NvU32 *);
316 typedef NV_STATUS OSPackageRegistry(OBJGPU *, PACKED_REGISTRY_TABLE *, NvU32 *);
317 typedef NV_STATUS OSUnpackageRegistry(PACKED_REGISTRY_TABLE *);
318 typedef NvBool OSQueueDpc(OBJGPU *);
319 typedef void OSFlushCpuWriteCombineBuffer(void);
320 typedef NV_STATUS OSNumaMemblockSize(NvU64 *);
321 typedef NvBool OSNumaOnliningEnabled(OS_GPU_INFO *);
322 typedef NV_STATUS OSAllocPagesNode(NvS32, NvLength, NvU32, NvU64 *);
323 typedef void OSAllocAcquirePage(NvU64, NvU32);
324 typedef void OSAllocReleasePage(NvU64, NvU32);
325 typedef NvU32 OSGetPageRefcount(NvU64);
326 typedef NvU32 OSCountTailPages(NvU64);
327 typedef NvU64 OSGetPageSize(void);
328 typedef NvU8 OSGetPageShift(void);
329
330 typedef NV_STATUS NV_FORCERESULTCHECK OSAcquireRmSema(void *);
331 typedef NvBool NV_FORCERESULTCHECK OSIsRmSemaOwner(void *);
332 typedef NV_STATUS NV_FORCERESULTCHECK OSCondAcquireRmSema(void *);
333 typedef NvU32 OSReleaseRmSema(void *, OBJGPU *);
334
335 #define DPC_RELEASE_ALL_GPU_LOCKS (1)
336 #define DPC_RELEASE_SINGLE_GPU_LOCK (2)
337
338 typedef NV_STATUS OSGpuLocksQueueRelease(OBJGPU *pGpu, NvU32 dpcGpuLockRelease);
339 typedef NvU32 OSApiLockAcquireConfigureFlags(NvU32 flags);
340
341 typedef NvU32 OSGetCpuCount(void);
342 typedef NvU32 OSGetMaximumCoreCount(void);
343 typedef NvU32 OSGetCurrentProcessorNumber(void);
344 typedef NV_STATUS OSDelay(NvU32);
345 typedef NV_STATUS OSDelayUs(NvU32);
346 typedef NV_STATUS OSDelayNs(NvU32);
347 typedef void OSSpinLoop(void);
348 typedef NvU64 OSGetMaxUserVa(void);
349 typedef NvU32 OSGetCpuVaAddrShift(void);
350 typedef NvU32 OSGetCurrentProcess(void);
351 typedef void OSGetCurrentProcessName(char *, NvU32);
352 typedef NvU32 OSGetCurrentPasid(void);
353 typedef NV_STATUS OSGetCurrentThread(OS_THREAD_HANDLE *);
354 typedef NV_STATUS OSAttachToProcess(void **, NvU32);
355 typedef void OSDetachFromProcess(void*);
356 typedef NV_STATUS OSVirtualToPhysicalAddr(MEMORY_DESCRIPTOR *, NvP64, RmPhysAddr *);
357 typedef NV_STATUS NV_FORCERESULTCHECK OSMapPciMemoryUser(OS_GPU_INFO *, RmPhysAddr, NvU64, NvU32, NvP64 *, NvP64 *, NvU32);
358 typedef void OSUnmapPciMemoryUser(OS_GPU_INFO *, NvP64, NvU64, NvP64);
359 typedef NV_STATUS NV_FORCERESULTCHECK OSMapPciMemoryKernelOld(OBJGPU *, RmPhysAddr, NvU64, NvU32, void **, NvU32);
360 typedef void OSUnmapPciMemoryKernelOld(OBJGPU *, void *);
361 typedef NV_STATUS NV_FORCERESULTCHECK OSMapPciMemoryKernel64(OBJGPU *, RmPhysAddr, NvU64, NvU32, NvP64 *, NvU32);
362 typedef void OSUnmapPciMemoryKernel64(OBJGPU *, NvP64);
363 typedef NV_STATUS NV_FORCERESULTCHECK OSMapSystemMemory(MEMORY_DESCRIPTOR *, NvU64, NvU64, NvBool, NvU32, NvP64*, NvP64*);
364 typedef void OSUnmapSystemMemory(MEMORY_DESCRIPTOR *, NvBool, NvU32, NvP64, NvP64);
365 typedef NvBool OSLockShouldToggleInterrupts(OBJGPU *);
366 typedef NV_STATUS OSGetPerformanceCounter(NvU64 *);
367 NvBool osDbgBreakpointEnabled(void);
368 typedef NV_STATUS OSAttachGpu(OBJGPU *, void *);
369 typedef NV_STATUS OSDpcAttachGpu(OBJGPU *, void *);
370 typedef void OSDpcDetachGpu(OBJGPU *);
371 typedef NV_STATUS OSHandleGpuLost(OBJGPU *);
372 typedef void OSHandleGpuSurpriseRemoval(OBJGPU *);
373 typedef void OSInitScalabilityOptions(OBJGPU *, void *);
374 typedef void OSHandleDeferredRecovery(OBJGPU *);
375 typedef NvBool OSIsSwPreInitOnly(OS_GPU_INFO *);
376
377 typedef void OSGetTimeoutParams(OBJGPU *, NvU32 *, NvU32 *, NvU32 *);
378 typedef NvBool OSIsRaisedIRQL(void);
379 typedef NvBool OSIsISR(void);
380 typedef NV_STATUS OSGetDriverBlock(OS_GPU_INFO *, OS_DRIVER_BLOCK *);
381 typedef NvBool OSIsEqualGUID(void *, void *);
382
383 #define OS_QUEUE_WORKITEM_FLAGS_NONE 0x00000000
384 #define OS_QUEUE_WORKITEM_FLAGS_DONT_FREE_PARAMS NVBIT(0)
385 #define OS_QUEUE_WORKITEM_FLAGS_FALLBACK_TO_DPC NVBIT(1)
386 //
387 // Lock flags:
388 // Only one of the LOCK_GPU flags should be provided. If multiple are,
389 // the priority ordering should be GPUS > GROUP_DEVICE > GROUP_SUBDEVICE
390 //
391 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_SEMA NVBIT(8)
392 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_API_RW NVBIT(9)
393 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_API_RO NVBIT(10)
394 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_GPUS NVBIT(11)
395 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_DEVICE NVBIT(12)
396 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE NVBIT(13)
397 //
398 // Perform a GPU full power sanity after getting GPU locks.
399 // One of the above LOCK_GPU flags must be provided when using this flag.
400 //
401 #define OS_QUEUE_WORKITEM_FLAGS_FULL_GPU_SANITY NVBIT(14)
402 #define OS_QUEUE_WORKITEM_FLAGS_FOR_PM_RESUME NVBIT(15)
403 typedef void OSWorkItemFunction(NvU32 gpuInstance, void *);
404 typedef void OSSystemWorkItemFunction(void *);
405 NV_STATUS osQueueWorkItemWithFlags(OBJGPU *, OSWorkItemFunction, void *, NvU32);
406
osQueueWorkItem(OBJGPU * pGpu,OSWorkItemFunction pFunction,void * pParams)407 static NV_INLINE NV_STATUS osQueueWorkItem(OBJGPU *pGpu, OSWorkItemFunction pFunction, void *pParams)
408 {
409 return osQueueWorkItemWithFlags(pGpu, pFunction, pParams, OS_QUEUE_WORKITEM_FLAGS_NONE);
410 }
411
412 NV_STATUS osQueueSystemWorkItem(OSSystemWorkItemFunction, void *);
413
414 // MXM ACPI calls
415 NV_STATUS osCallACPI_MXMX(OBJGPU *, NvU32, NvU8 *);
416 NV_STATUS osCallACPI_DDC(OBJGPU *, NvU32, NvU8*,NvU32*, NvBool);
417 NV_STATUS osCallACPI_BCL(OBJGPU *, NvU32, NvU32 *, NvU16 *);
418
419 // Display MUX ACPI calls
420 NV_STATUS osCallACPI_MXDS(OBJGPU *, NvU32, NvU32 *);
421 NV_STATUS osCallACPI_MXDM(OBJGPU *, NvU32, NvU32 *);
422 NV_STATUS osCallACPI_MXID(OBJGPU *, NvU32, NvU32 *);
423 NV_STATUS osCallACPI_LRST(OBJGPU *, NvU32, NvU32 *);
424
425 // Hybrid GPU ACPI calls
426 NV_STATUS osCallACPI_NVHG_GPUON(OBJGPU *, NvU32 *);
427 NV_STATUS osCallACPI_NVHG_GPUOFF(OBJGPU *, NvU32 *);
428 NV_STATUS osCallACPI_NVHG_GPUSTA(OBJGPU *, NvU32 *);
429 NV_STATUS osCallACPI_NVHG_MXDS(OBJGPU *, NvU32, NvU32 *);
430 NV_STATUS osCallACPI_NVHG_MXMX(OBJGPU *, NvU32, NvU32 *);
431 NV_STATUS osCallACPI_NVHG_DOS(OBJGPU *, NvU32, NvU32 *);
432 NV_STATUS osCallACPI_NVHG_ROM(OBJGPU *, NvU32 *, NvU32 *);
433 NV_STATUS osCallACPI_NVHG_DCS(OBJGPU *, NvU32, NvU32 *);
434 NV_STATUS osCallACPI_DOD(OBJGPU *, NvU32 *, NvU32 *);
435
436 // Optimus WMI ACPI calls
437 NV_STATUS osCallACPI_OPTM_GPUON(OBJGPU *);
438
439 // Generic ACPI _DSM call
440 NV_STATUS osCallACPI_DSM(OBJGPU *pGpu, ACPI_DSM_FUNCTION acpiDSMFunction,
441 NvU32 NVHGDSMSubfunction, NvU32 *pInOut, NvU16 *size);
442
443 // UEFI variable calls
444 NV_STATUS osGetUefiVariable(const char *, LPGUID, NvU8 *, NvU32 *);
445
446 // The following functions are also implemented in WinNT
447 void osQADbgRegistryInit(void);
448 typedef NV_STATUS OSGetVersionDump(void *);
449 // End of WinNT
450
451 NvU32 osNv_rdcr4(void);
452 NvU64 osNv_rdxcr0(void);
453 int osNv_cpuid(int, int, NvU32 *, NvU32 *, NvU32 *, NvU32 *);
454
455 // NOTE: The following functions are also implemented in MODS
456 NV_STATUS osSimEscapeWrite(OBJGPU *, const char *path, NvU32 Index, NvU32 Size, NvU32 Value);
457 NV_STATUS osSimEscapeWriteBuffer(OBJGPU *, const char *path, NvU32 Index, NvU32 Size, void* pBuffer);
458 NV_STATUS osSimEscapeRead(OBJGPU *, const char *path, NvU32 Index, NvU32 Size, NvU32 *Value);
459 NV_STATUS osSimEscapeReadBuffer(OBJGPU *, const char *path, NvU32 Index, NvU32 Size, void* pBuffer);
460 NvU32 osGetSimulationMode(void);
461 typedef void OSLogString(const char*, ...);
462 typedef void OSFlushLog(void);
463 typedef void OSSetSurfaceName(void *pDescriptor, char *name);
464
465 // End of MODS functions
466
467 //Vista Specific Functions
468
469 NV_STATUS osSetupVBlank(OBJGPU *pGpu, void * pProc,
470 void * pParm1, void * pParm2, NvU32 Head, void * pParm3);
471
472 // Heap reserve tracking functions
473 void osInternalReserveAllocCallback(NvU64 offset, NvU64 size, NvU32 gpuId);
474 void osInternalReserveFreeCallback(NvU64 offset, NvU32 gpuId);
475
476
477 //
478 // Function pointer typedef for use as callback prototype when filtering
479 // address ranges in os memory access routines
480 //
481 typedef NV_STATUS (OSMemFilterCb)(void *pPriv, NvU64 addr, void *pData, NvU64 size, NvBool bRead);
482
483 // Structure typedef for storing the callback pointer and priv data
484 typedef struct
485 {
486 NODE node;
487 OSMemFilterCb *pFilterCb;
488 void *pPriv;
489 } OSMEMFILTERDATA, *POSMEMFILTERDATA;
490
491 //
492 // OS Functions typically only implemented for MODS
493 // Note: See comments above for other functions that
494 // are also implemented on MODS as well as other
495 // OS's.
496 //
497
498 NV_STATUS osRmInitRm(void);
499 typedef NvU32 OSPollHotkeyState(OBJGPU *);
500
501 typedef void OSSyncWithRmDestroy(void);
502 typedef void OSSyncWithGpuDestroy(NvBool);
503
504 typedef void OSModifyGpuSwStatePersistence(OS_GPU_INFO *, NvBool);
505
506 typedef NV_STATUS OSMemAddFilter(NvU64, NvU64, OSMemFilterCb*, void *);
507 typedef NV_STATUS OSMemRemoveFilter(NvU64);
508 typedef POSMEMFILTERDATA OSMemGetFilter(NvUPtr);
509
510 typedef NV_STATUS OSGetCarveoutInfo(NvU64*, NvU64*);
511 typedef NV_STATUS OSGetVPRInfo(NvU64*, NvU64*);
512 typedef NV_STATUS OSAllocInVPR(MEMORY_DESCRIPTOR*);
513 typedef NV_STATUS OSGetGenCarveout(NvU64*, NvU64 *, NvU32, NvU64);
514 typedef NV_STATUS OSGetSysmemInfo(OBJGPU *, NvU64*, NvU64*);
515
516 typedef NV_STATUS OSI2CClosePorts(OS_GPU_INFO *, NvU32);
517 typedef NV_STATUS OSWriteI2CBufferDirect(OBJGPU *, NvU32, NvU8, void *, NvU32, void *, NvU32);
518 typedef NV_STATUS OSReadI2CBufferDirect(OBJGPU *, NvU32, NvU8, void *, NvU32, void *, NvU32);
519 typedef NV_STATUS OSI2CTransfer(OBJGPU *, NvU32, NvU8, nv_i2c_msg_t *, NvU32);
520 typedef NV_STATUS OSSetGpuRailVoltage(OBJGPU *, NvU32, NvU32*);
521 typedef NV_STATUS OSGetGpuRailVoltage(OBJGPU *, NvU32*);
522 typedef NV_STATUS OSGetGpuRailVoltageInfo(OBJGPU *, NvU32 *, NvU32 *, NvU32 *);
523
524 typedef NV_STATUS OSGC6PowerControl(OBJGPU *, NvU32, NvU32 *);
525
526 RmPhysAddr osPageArrayGetPhysAddr(OS_GPU_INFO *pOsGpuInfo, void* pPageData, NvU32 pageIndex);
527 typedef NV_STATUS OSGetChipInfo(OBJGPU *, NvU32*, NvU32*, NvU32*, NvU32*);
528
529 typedef enum
530 {
531 RC_CALLBACK_IGNORE,
532 RC_CALLBACK_ISOLATE,
533 RC_CALLBACK_ISOLATE_NO_RESET,
534 } RC_CALLBACK_STATUS;
535 RC_CALLBACK_STATUS osRCCallback(OBJGPU *, NvHandle, NvHandle, NvHandle, NvHandle, NvU32, NvU32, NvU32 *, void *);
536 NvBool osCheckCallback(OBJGPU *);
537 RC_CALLBACK_STATUS osRCCallback_v2(OBJGPU *, NvHandle, NvHandle, NvHandle, NvHandle, NvU32, NvU32, NvBool, NvU32 *, void *);
538 NvBool osCheckCallback_v2(OBJGPU *);
539 typedef NV_STATUS OSReadPFPciConfigInVF(NvU32, NvU32*);
540
541 // Actual definition of the OBJOS structure
542
543 // Private field names are wrapped in PRIVATE_FIELD, which does nothing for
544 // the matching C source file, but causes diagnostics to be issued if another
545 // source file references the field.
546 #ifdef NVOC_OS_H_PRIVATE_ACCESS_ALLOWED
547 #define PRIVATE_FIELD(x) x
548 #else
549 #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x)
550 #endif
551
552
553 struct OBJOS {
554
555 // Metadata
556 const struct NVOC_RTTI *__nvoc_rtti;
557
558 // Parent (i.e. superclass or base class) object pointers
559 struct Object __nvoc_base_Object;
560
561 // Ancestor object pointers for `staticCast` feature
562 struct Object *__nvoc_pbase_Object; // obj super
563 struct OBJOS *__nvoc_pbase_OBJOS; // os
564
565 // 13 PDB properties
566 NvBool PDB_PROP_OS_PAT_UNSUPPORTED;
567 NvBool PDB_PROP_OS_SLI_ALLOWED;
568 NvBool PDB_PROP_OS_SYSTEM_EVENTS_SUPPORTED;
569 NvBool PDB_PROP_OS_ONDEMAND_VBLANK_CONTROL_ENABLE_DEFAULT;
570 NvBool PDB_PROP_OS_WAIT_FOR_ACPI_SUBSYSTEM;
571 NvBool PDB_PROP_OS_UNCACHED_MEMORY_MAPPINGS_NOT_SUPPORTED;
572 NvBool PDB_PROP_OS_CACHED_MEMORY_MAPPINGS_FOR_ACPI_TABLE;
573 NvBool PDB_PROP_OS_LIMIT_GPU_RESET;
574 NvBool PDB_PROP_OS_SUPPORTS_TDR;
575 NvBool PDB_PROP_OS_GET_ACPI_TABLE_FROM_UEFI;
576 NvBool PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER;
577 NvBool PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS;
578 NvBool PDB_PROP_OS_NO_PAGED_SEGMENT_ACCESS;
579
580 // Data members
581 NvU32 dynamicPowerSupportGpuMask;
582 NvBool bIsSimMods;
583 };
584
585 #ifndef __NVOC_CLASS_OBJOS_TYPEDEF__
586 #define __NVOC_CLASS_OBJOS_TYPEDEF__
587 typedef struct OBJOS OBJOS;
588 #endif /* __NVOC_CLASS_OBJOS_TYPEDEF__ */
589
590 #ifndef __nvoc_class_id_OBJOS
591 #define __nvoc_class_id_OBJOS 0xaa1d70
592 #endif /* __nvoc_class_id_OBJOS */
593
594 // Casting support
595 extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJOS;
596
597 #define __staticCast_OBJOS(pThis) \
598 ((pThis)->__nvoc_pbase_OBJOS)
599
600 #ifdef __nvoc_os_h_disabled
601 #define __dynamicCast_OBJOS(pThis) ((OBJOS*)NULL)
602 #else //__nvoc_os_h_disabled
603 #define __dynamicCast_OBJOS(pThis) \
604 ((OBJOS*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(OBJOS)))
605 #endif //__nvoc_os_h_disabled
606
607 // Property macros
608 #define PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER_BASE_CAST
609 #define PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER_BASE_NAME PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER
610 #define PDB_PROP_OS_NO_PAGED_SEGMENT_ACCESS_BASE_CAST
611 #define PDB_PROP_OS_NO_PAGED_SEGMENT_ACCESS_BASE_NAME PDB_PROP_OS_NO_PAGED_SEGMENT_ACCESS
612 #define PDB_PROP_OS_WAIT_FOR_ACPI_SUBSYSTEM_BASE_CAST
613 #define PDB_PROP_OS_WAIT_FOR_ACPI_SUBSYSTEM_BASE_NAME PDB_PROP_OS_WAIT_FOR_ACPI_SUBSYSTEM
614 #define PDB_PROP_OS_UNCACHED_MEMORY_MAPPINGS_NOT_SUPPORTED_BASE_CAST
615 #define PDB_PROP_OS_UNCACHED_MEMORY_MAPPINGS_NOT_SUPPORTED_BASE_NAME PDB_PROP_OS_UNCACHED_MEMORY_MAPPINGS_NOT_SUPPORTED
616 #define PDB_PROP_OS_LIMIT_GPU_RESET_BASE_CAST
617 #define PDB_PROP_OS_LIMIT_GPU_RESET_BASE_NAME PDB_PROP_OS_LIMIT_GPU_RESET
618 #define PDB_PROP_OS_ONDEMAND_VBLANK_CONTROL_ENABLE_DEFAULT_BASE_CAST
619 #define PDB_PROP_OS_ONDEMAND_VBLANK_CONTROL_ENABLE_DEFAULT_BASE_NAME PDB_PROP_OS_ONDEMAND_VBLANK_CONTROL_ENABLE_DEFAULT
620 #define PDB_PROP_OS_PAT_UNSUPPORTED_BASE_CAST
621 #define PDB_PROP_OS_PAT_UNSUPPORTED_BASE_NAME PDB_PROP_OS_PAT_UNSUPPORTED
622 #define PDB_PROP_OS_SLI_ALLOWED_BASE_CAST
623 #define PDB_PROP_OS_SLI_ALLOWED_BASE_NAME PDB_PROP_OS_SLI_ALLOWED
624 #define PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS_BASE_CAST
625 #define PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS_BASE_NAME PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS
626 #define PDB_PROP_OS_CACHED_MEMORY_MAPPINGS_FOR_ACPI_TABLE_BASE_CAST
627 #define PDB_PROP_OS_CACHED_MEMORY_MAPPINGS_FOR_ACPI_TABLE_BASE_NAME PDB_PROP_OS_CACHED_MEMORY_MAPPINGS_FOR_ACPI_TABLE
628 #define PDB_PROP_OS_SUPPORTS_TDR_BASE_CAST
629 #define PDB_PROP_OS_SUPPORTS_TDR_BASE_NAME PDB_PROP_OS_SUPPORTS_TDR
630 #define PDB_PROP_OS_GET_ACPI_TABLE_FROM_UEFI_BASE_CAST
631 #define PDB_PROP_OS_GET_ACPI_TABLE_FROM_UEFI_BASE_NAME PDB_PROP_OS_GET_ACPI_TABLE_FROM_UEFI
632 #define PDB_PROP_OS_SYSTEM_EVENTS_SUPPORTED_BASE_CAST
633 #define PDB_PROP_OS_SYSTEM_EVENTS_SUPPORTED_BASE_NAME PDB_PROP_OS_SYSTEM_EVENTS_SUPPORTED
634
635 NV_STATUS __nvoc_objCreateDynamic_OBJOS(OBJOS**, Dynamic*, NvU32, va_list);
636
637 NV_STATUS __nvoc_objCreate_OBJOS(OBJOS**, Dynamic*, NvU32);
638 #define __objCreate_OBJOS(ppNewObj, pParent, createFlags) \
639 __nvoc_objCreate_OBJOS((ppNewObj), staticCast((pParent), Dynamic), (createFlags))
640
641
642 // Wrapper macros
643
644 // Dispatch functions
645 #undef PRIVATE_FIELD
646
647
648 NV_STATUS addProbe(OBJGPU *, NvU32);
649
650
651 typedef NV_STATUS OSFlushCpuCache(void);
652 typedef void OSAddRecordForCrashLog(void *, NvU32);
653 typedef void OSDeleteRecordForCrashLog(void *);
654
655 OSFlushCpuCache osFlushCpuCache;
656 OSAddRecordForCrashLog osAddRecordForCrashLog;
657 OSDeleteRecordForCrashLog osDeleteRecordForCrashLog;
658
659 NV_STATUS osTegraSocPowerManagement(OS_GPU_INFO *pOsGpuInfo,
660 NvBool bInPMTransition,
661 NvU32 newPMLevel);
662
663 //
664 // This file should only contain the most common OS functions that provide
665 // direct call. Ex. osDelay, osIsAdministrator
666 //
667 NV_STATUS osTegraSocPmPowergate(OS_GPU_INFO *pOsGpuInfo);
668 NV_STATUS osTegraSocPmUnpowergate(OS_GPU_INFO *pOsGpuInfo);
669 NV_STATUS osTegraSocDeviceReset(OS_GPU_INFO *pOsGpuInfo);
670 NV_STATUS osTegraSocBpmpSendMrq(OS_GPU_INFO *pOsGpuInfo,
671 NvU32 mrq,
672 const void *pRequestData,
673 NvU32 requestDataSize,
674 void *pResponseData,
675 NvU32 responseDataSize,
676 NvS32 *pRet,
677 NvS32 *pApiRet);
678 NV_STATUS osTegraSocGetImpImportData(TEGRA_IMP_IMPORT_DATA *pTegraImpImportData);
679 NV_STATUS osTegraSocEnableDisableRfl(OS_GPU_INFO *pOsGpuInfo, NvBool bEnable);
680 NV_STATUS osTegraAllocateDisplayBandwidth(OS_GPU_INFO *pOsGpuInfo,
681 NvU32 averageBandwidthKBPS,
682 NvU32 floorBandwidthKBPS);
683
684 NV_STATUS osGetCurrentProcessGfid(NvU32 *pGfid);
685 NvBool osIsAdministrator(void);
686 NvBool osAllowPriorityOverride(void);
687 NV_STATUS osGetCurrentTime(NvU32 *pSec,NvU32 *puSec);
688 NV_STATUS osGetCurrentTick(NvU64 *pTimeInNs);
689 NvU64 osGetTickResolution(void);
690 NvU64 osGetTimestamp(void);
691 NvU64 osGetTimestampFreq(void);
692
693 NV_STATUS osDeferredIsr(OBJGPU *pGpu);
694
695 void osEnableInterrupts(OBJGPU *pGpu);
696
697 void osDisableInterrupts(OBJGPU *pGpu,
698 NvBool bIsr);
699
700 void osBugCheck(NvU32 bugCode);
701 void osAssertFailed(void);
702
703 // OS PCI R/W functions
704 void *osPciInitHandle(NvU32 domain, NvU8 bus, NvU8 slot, NvU8 function,
705 NvU16 *pVendor, NvU16 *pDevice);
706 NvU32 osPciReadDword(void *pHandle, NvU32 offset);
707 NvU16 osPciReadWord(void *pHandle, NvU32 offset);
708 NvU8 osPciReadByte(void *pHandle, NvU32 offset);
709 void osPciWriteDword(void *pHandle, NvU32 offset, NvU32 value);
710 void osPciWriteWord(void *pHandle, NvU32 offset, NvU16 value);
711 void osPciWriteByte(void *pHandle, NvU32 offset, NvU8 value);
712
713 // OS RM capabilities calls
714
715 void osRmCapInitDescriptor(NvU64 *pCapDescriptor);
716 NV_STATUS osRmCapAcquire(OS_RM_CAPS *pOsRmCaps, NvU32 rmCap,
717 NvU64 capDescriptor,
718 NvU64 *dupedCapDescriptor);
719 void osRmCapRelease(NvU64 dupedCapDescriptor);
720 NV_STATUS osRmCapRegisterGpu(OS_GPU_INFO *pOsGpuInfo, OS_RM_CAPS **ppOsRmCaps);
721 void osRmCapUnregister(OS_RM_CAPS **ppOsRmCaps);
722 NV_STATUS osRmCapRegisterSmcPartition(OS_RM_CAPS *pGpuOsRmCaps,
723 OS_RM_CAPS **ppPartitionOsRmCaps,
724 NvU32 partitionId);
725 NV_STATUS osRmCapRegisterSmcExecutionPartition(
726 OS_RM_CAPS *pPartitionOsRmCaps,
727 OS_RM_CAPS **ppExecPartitionOsRmCaps,
728 NvU32 execPartitionId);
729 NV_STATUS osRmCapRegisterSys(OS_RM_CAPS **ppOsRmCaps);
730
731 NvBool osImexChannelIsSupported(void);
732 NvS32 osImexChannelGet(NvU64 descriptor);
733 NvS32 osImexChannelCount(void);
734
735 NV_STATUS osGetRandomBytes(NvU8 *pBytes, NvU16 numBytes);
736
737 NV_STATUS osAllocWaitQueue(OS_WAIT_QUEUE **ppWq);
738 void osFreeWaitQueue(OS_WAIT_QUEUE *pWq);
739 void osWaitUninterruptible(OS_WAIT_QUEUE *pWq);
740 void osWaitInterruptible(OS_WAIT_QUEUE *pWq);
741 void osWakeUp(OS_WAIT_QUEUE *pWq);
742
743 NvU32 osGetDynamicPowerSupportMask(void);
744
745 void osUnrefGpuAccessNeeded(OS_GPU_INFO *pOsGpuInfo);
746 NV_STATUS osRefGpuAccessNeeded(OS_GPU_INFO *pOsGpuInfo);
747
748 NvU32 osGetGridCspSupport(void);
749
750 NV_STATUS osIovaMap(PIOVAMAPPING pIovaMapping);
751 void osIovaUnmap(PIOVAMAPPING pIovaMapping);
752 NV_STATUS osGetAtsTargetAddressRange(OBJGPU *pGpu,
753 NvU64 *pAddr,
754 NvU32 *pAddrWidth,
755 NvU32 *pMask,
756 NvU32 *pMaskWidth,
757 NvBool bIsPeer,
758 NvU32 peerIndex);
759 NV_STATUS osGetFbNumaInfo(OBJGPU *pGpu,
760 NvU64 *pAddrPhys,
761 NvU64 *pAddrRsvdPhys,
762 NvS32 *pNodeId);
763 NV_STATUS osGetEgmInfo(OBJGPU *pGpu,
764 NvU64 *pPhysAddr,
765 NvU64 *pSize,
766 NvS32 *pNodeId);
767 NV_STATUS osGetForcedNVLinkConnection(OBJGPU *pGpu,
768 NvU32 maxLinks,
769 NvU32 *pLinkConnection);
770 NV_STATUS osGetForcedC2CConnection(OBJGPU *pGpu,
771 NvU32 maxLinks,
772 NvU32 *pLinkConnection);
773 void osSetNVLinkSysmemLinkState(OBJGPU *pGpu,NvBool enabled);
774 NV_STATUS osGetPlatformNvlinkLinerate(OBJGPU *pGpu,NvU32 *lineRate);
775 const struct nvlink_link_handlers* osGetNvlinkLinkCallbacks(void);
776
777 void osRemoveGpu(NvU32 domain, NvU8 bus, NvU8 device);
778 NvBool osRemoveGpuSupported(void);
779
780 void initVGXSpecificRegistry(OBJGPU *);
781
782 NV_STATUS nv_vgpu_rm_get_bar_info(OBJGPU *pGpu, const NvU8 *pMdevUuid, NvU64 *barSizes,
783 NvU64 *sparseOffsets, NvU64 *sparseSizes,
784 NvU32 *sparseCount, NvBool *isBar064bit,
785 NvU8 *configParams);
786 NV_STATUS osIsVgpuVfioPresent(void);
787 NV_STATUS osIsVfioPciCorePresent(void);
788 void osWakeRemoveVgpu(NvU32, NvU32);
789 NV_STATUS rm_is_vgpu_supported_device(OS_GPU_INFO *pNv, NvU32 pmc_boot_1,
790 NvU32 pmc_boot_42);
791 NV_STATUS osLockPageableDataSection(RM_PAGEABLE_SECTION *pSection);
792 NV_STATUS osUnlockPageableDataSection(RM_PAGEABLE_SECTION *pSection);
793
794 void osFlushGpuCoherentCpuCacheRange(OS_GPU_INFO *pOsGpuInfo,
795 NvU64 cpuVirtual,
796 NvU64 size);
797 NvBool osUidTokensEqual(PUID_TOKEN arg1, PUID_TOKEN arg2);
798
799 NV_STATUS osValidateClientTokens(PSECURITY_TOKEN arg1,
800 PSECURITY_TOKEN arg2);
801 PUID_TOKEN osGetCurrentUidToken(void);
802 PSECURITY_TOKEN osGetSecurityToken(void);
803
804 NV_STATUS osIsKernelBuffer(void *pArg1, NvU32 arg2);
805
806 NV_STATUS osMapViewToSection(OS_GPU_INFO *pArg1,
807 void *pSectionHandle,
808 void **ppAddress,
809 NvU64 actualSize,
810 NvU64 sectionOffset,
811 NvBool bIommuEnabled);
812 NV_STATUS osUnmapViewFromSection(OS_GPU_INFO *pArg1,
813 void *pAddress,
814 NvBool bIommuEnabled);
815
816 NV_STATUS osOpenTemporaryFile(void **ppFile);
817 void osCloseFile(void *pFile);
818 NV_STATUS osWriteToFile(void *pFile, NvU8 *buffer,
819 NvU64 size, NvU64 offset);
820 NV_STATUS osReadFromFile(void *pFile, NvU8 *buffer,
821 NvU64 size, NvU64 offset);
822
823 NV_STATUS osSrPinSysmem(OS_GPU_INFO *pArg1,
824 NvU64 commitSize,
825 void *pMdl);
826 NV_STATUS osSrUnpinSysmem(OS_GPU_INFO *pArg1);
827
828 void osPagedSegmentAccessCheck(void);
829
830 NV_STATUS osCreateMemFromOsDescriptorInternal(OBJGPU *pGpu, void *pAddress,
831 NvU32 flags, NvU64 size,
832 MEMORY_DESCRIPTOR **ppMemDesc,
833 NvBool bCachedKernel,
834 RS_PRIV_LEVEL privilegeLevel);
835
836 NV_STATUS osReserveCpuAddressSpaceUpperBound(void **ppSectionHandle,
837 NvU64 maxSectionSize);
838 void osReleaseCpuAddressSpaceUpperBound(void *pSectionHandle);
839
840 void* osGetPidInfo(void);
841 void osPutPidInfo(void *pOsPidInfo);
842 NV_STATUS osFindNsPid(void *pOsPidInfo, NvU32 *pNsPid);
843
844 // OS Tegra IPC functions
845 NV_STATUS osTegraDceRegisterIpcClient(NvU32 interfaceType, void *usrCtx,
846 NvU32 *clientId);
847 NV_STATUS osTegraDceClientIpcSendRecv(NvU32 clientId, void *msg,
848 NvU32 msgLength);
849 NV_STATUS osTegraDceUnregisterIpcClient(NvU32 clientId);
850
851 //
852 // Define OS-layer specific type instead of #include "clk_domains.h" for
853 // CLKWHICH, avoids upwards dependency from OS interface on higher level
854 // RM modules
855 //
856 typedef NvU32 OS_CLKWHICH;
857
858 NV_STATUS osTegraSocEnableClk(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRM);
859 NV_STATUS osTegraSocDisableClk(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRM);
860 NV_STATUS osTegraSocGetCurrFreqKHz(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRM, NvU32 *pCurrFreqKHz);
861 NV_STATUS osTegraSocGetMaxFreqKHz(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRM, NvU32 *pMaxFreqKHz);
862 NV_STATUS osTegraSocGetMinFreqKHz(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRM, NvU32 *pMinFreqKHz);
863 NV_STATUS osTegraSocSetFreqKHz(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRM, NvU32 reqFreqKHz);
864 NV_STATUS osTegraSocSetParent(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRMsource, OS_CLKWHICH whichClkRMparent);
865 NV_STATUS osTegraSocGetParent(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRMsource, OS_CLKWHICH *pWhichClkRMparent);
866
867 NV_STATUS osTegraSocDeviceReset(OS_GPU_INFO *pOsGpuInfo);
868 NV_STATUS osTegraSocPmPowergate(OS_GPU_INFO *pOsGpuInfo);
869 NV_STATUS osTegraSocPmUnpowergate(OS_GPU_INFO *pOsGpuInfo);
870 NV_STATUS osGetSyncpointAperture(OS_GPU_INFO *pOsGpuInfo,
871 NvU32 syncpointId,
872 NvU64 *physAddr,
873 NvU64 *limit,
874 NvU32 *offset);
875 NV_STATUS osTegraI2CGetBusState(OS_GPU_INFO *pOsGpuInfo, NvU32 port, NvS32 *scl, NvS32 *sda);
876 NV_STATUS osTegraSocParseFixedModeTimings(OS_GPU_INFO *pOsGpuInfo,
877 NvU32 dcbIndex,
878 NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS *pTimingsPerStream,
879 NvU8 *pNumTimings);
880
881 NV_STATUS osGetVersion(NvU32 *pMajorVer,
882 NvU32 *pMinorVer,
883 NvU32 *pBuildNum,
884 NvU16 *pServicePackMaj,
885 NvU16 *pProductType);
886
887 NV_STATUS osGetIsOpenRM(NvBool *bOpenRm);
888
889 NvBool osGrService(OS_GPU_INFO *pOsGpuInfo, NvU32 grIdx, NvU32 intr, NvU32 nstatus, NvU32 addr, NvU32 dataLo);
890
891 NvBool osDispService(NvU32 Intr0, NvU32 Intr1);
892
893 NV_STATUS osReferenceObjectCount(void *pEvent);
894
895 NV_STATUS osDereferenceObjectCount(void *pEvent);
896
897 //
898 // Perform OS-specific error logging.
899 // Like libc's vsnprintf(), osErrorLogV() invalidates its va_list argument. The va_list argument
900 // may not be reused after osErrorLogV() returns. If the va_list is needed after the
901 // osErrorLogV() call, create a copy of the va_list using va_copy().
902 // The caller controls the lifetime of the va_list argument, and should free it using va_end.
903 //
904 void osErrorLogV(OBJGPU *pGpu, NvU32 num, const char * pFormat, va_list arglist);
905 void osErrorLog(OBJGPU *pGpu, NvU32 num, const char* pFormat, ...);
906
907 NV_STATUS osNvifInitialize(OBJGPU *pGpu);
908
909 NV_STATUS osNvifMethod(OBJGPU *pGpu, NvU32 func,
910 NvU32 subFunc, void *pInParam,
911 NvU16 inParamSize, NvU32 *pOutStatus,
912 void *pOutData, NvU16 *pOutDataSize);
913
914 NV_STATUS osCreateMemFromOsDescriptor(OBJGPU *pGpu, NvP64 pDescriptor,
915 NvHandle hClient, NvU32 flags,
916 NvU64 *pLimit,
917 MEMORY_DESCRIPTOR **ppMemDesc,
918 NvU32 descriptorType,
919 RS_PRIV_LEVEL privilegeLevel);
920
921 void* osMapKernelSpace(RmPhysAddr Start,
922 NvU64 Size,
923 NvU32 Mode,
924 NvU32 Protect);
925
926 void osUnmapKernelSpace(void *addr, NvU64 size);
927
928 NvBool osTestPcieExtendedConfigAccess(void *handle, NvU32 offset);
929
930 NvU32 osGetCpuFrequency(void);
931
932 void osIoWriteByte(NvU32 Address, NvU8 Value);
933
934 NvU8 osIoReadByte(NvU32 Address);
935
936 void osIoWriteWord(NvU32 Address, NvU16 Value);
937
938 NvU16 osIoReadWord(NvU32 Address);
939
940 void osIoWriteDword(NvU32 port, NvU32 data);
941
942 NvU32 osIoReadDword(NvU32 port);
943
944 // OS functions to get memory pages
945
946 NV_STATUS osGetNumMemoryPages (MEMORY_DESCRIPTOR *pMemDesc, NvU32 *pNumPages);
947 NV_STATUS osGetMemoryPages (MEMORY_DESCRIPTOR *pMemDesc, void *pPages, NvU32 *pNumPages);
948
949 NV_STATUS osGetAcpiTable(NvU32 tableSignature,
950 void **ppTable,
951 NvU32 tableSize,
952 NvU32 *retSize);
953
954 NV_STATUS osInitGetAcpiTable(void);
955
956 // Read NvGlobal regkey
957 NV_STATUS osGetNvGlobalRegistryDword(OBJGPU *, const char *pRegParmStr, NvU32 *pData);
958
959 NV_STATUS osGetIbmnpuGenregInfo(OS_GPU_INFO *pArg1,
960 NvU64 *pArg2,
961 NvU64 *pArg3);
962
963 NV_STATUS osGetIbmnpuRelaxedOrderingMode(OS_GPU_INFO *pArg1,
964 NvBool *pArg2);
965
966 void osWaitForIbmnpuRsync(OS_GPU_INFO *pArg1);
967
968 NV_STATUS osGetAcpiRsdpFromUefi(NvU32 *pRsdpAddr);
969
970 NV_STATUS osCreateNanoTimer(OS_GPU_INFO *pArg1,
971 void *tmrEvent,
972 void **tmrUserData);
973
974 NV_STATUS osStartNanoTimer(OS_GPU_INFO *pArg1,
975 void *pTimer,
976 NvU64 timeNs);
977
978 NV_STATUS osCancelNanoTimer(OS_GPU_INFO *pArg1,
979 void *pArg2);
980
981 NV_STATUS osDestroyNanoTimer(OS_GPU_INFO *pArg1,
982 void *pArg2);
983
984 NV_STATUS osGetValidWindowHeadMask(OS_GPU_INFO *pArg1,
985 NvU64 *pWindowHeadMask);
986
987 NV_STATUS osSchedule(void);
988
989 void osDmaSetAddressSize(OS_GPU_INFO *pArg1,
990 NvU32 bits);
991
992 void osClientGcoffDisallowRefcount(OS_GPU_INFO *pArg1,
993 NvBool arg2);
994
995 NV_STATUS osTegraSocGpioGetPinState(OS_GPU_INFO *pArg1,
996 NvU32 arg2,
997 NvU32 *pArg3);
998
999 void osTegraSocGpioSetPinState(OS_GPU_INFO *pArg1,
1000 NvU32 arg2,
1001 NvU32 arg3);
1002
1003 NV_STATUS osTegraSocGpioSetPinDirection(OS_GPU_INFO *pArg1,
1004 NvU32 arg2,
1005 NvU32 arg3);
1006
1007 NV_STATUS osTegraSocGpioGetPinDirection(OS_GPU_INFO *pArg1,
1008 NvU32 arg2,
1009 NvU32 *pArg3);
1010
1011 NV_STATUS osTegraSocGpioGetPinNumber(OS_GPU_INFO *pArg1,
1012 NvU32 arg2,
1013 NvU32 *pArg3);
1014
1015 NV_STATUS osTegraSocGpioGetPinInterruptStatus(OS_GPU_INFO *pArg1,
1016 NvU32 arg2,
1017 NvU32 arg3,
1018 NvBool *pArg4);
1019
1020 NV_STATUS osTegraSocGpioSetPinInterrupt(OS_GPU_INFO *pArg1,
1021 NvU32 arg2,
1022 NvU32 arg3);
1023
1024 NV_STATUS osTegraSocDsiParsePanelProps(OS_GPU_INFO *pArg1,
1025 void *pArg2);
1026
1027 NvBool osTegraSocIsDsiPanelConnected(OS_GPU_INFO *pArg1);
1028
1029 NV_STATUS osTegraSocDsiPanelEnable(OS_GPU_INFO *pArg1,
1030 void *pArg2);
1031
1032 NV_STATUS osTegraSocDsiPanelReset(OS_GPU_INFO *pArg1,
1033 void *pArg2);
1034
1035 void osTegraSocDsiPanelDisable(OS_GPU_INFO *pArg1,
1036 void *pArg2);
1037
1038 void osTegraSocDsiPanelCleanup(OS_GPU_INFO *pArg1,
1039 void *pArg2);
1040
1041 NV_STATUS osTegraSocResetMipiCal(OS_GPU_INFO *pArg1);
1042
1043 NV_STATUS osGetTegraNumDpAuxInstances(OS_GPU_INFO *pArg1,
1044 NvU32 *pArg2);
1045
1046 NvU32 osTegraSocFuseRegRead(NvU32 addr);
1047
1048 typedef void (*osTegraTsecCbFunc)(void*, void*);
1049
1050 NvU32 osTegraSocTsecSendCmd(void* cmd, osTegraTsecCbFunc cbFunc, void* cbContext);
1051
1052 NvU32 osTegraSocTsecEventRegister(osTegraTsecCbFunc cbFunc, void* cbContext, NvBool isInitEvent);
1053
1054 NvU32 osTegraSocTsecEventUnRegister(NvBool isInitEvent);
1055
1056 void* osTegraSocTsecAllocMemDesc(NvU32 numBytes, NvU32 *flcnAddr);
1057
1058 void osTegraSocTsecFreeMemDesc(void *memDesc);
1059
1060 NV_STATUS osTegraSocHspSemaphoreAcquire(NvU32 ownerId, NvBool bAcquire, NvU64 timeout);
1061
1062 NV_STATUS osTegraSocDpUphyPllInit(OS_GPU_INFO *pArg1, NvU32, NvU32);
1063
1064 NV_STATUS osTegraSocDpUphyPllDeInit(OS_GPU_INFO *pArg1);
1065
1066 NV_STATUS osGetCurrentIrqPrivData(OS_GPU_INFO *pArg1,
1067 NvU32 *pArg2);
1068
1069 NV_STATUS osGetTegraBrightnessLevel(OS_GPU_INFO *pArg1,
1070 NvU32 *pArg2);
1071
1072 NV_STATUS osSetTegraBrightnessLevel(OS_GPU_INFO *pArg1,
1073 NvU32 arg2);
1074
1075 NvBool osTegraSocGetHdcpEnabled(OS_GPU_INFO *pOsGpuInfo);
1076
1077 void osTegraGetDispSMMUStreamIds(
1078 OS_GPU_INFO *pOsGpuInfo,
1079 NvU32 *dispIsoStreamId,
1080 NvU32 *dispNisoStreamId
1081 );
1082
1083 NvBool osIsVga(OS_GPU_INFO *pArg1,
1084 NvBool bIsGpuPrimaryDevice);
1085
1086 void osInitOSHwInfo(OBJGPU *pGpu);
1087
1088 void osDestroyOSHwInfo(OBJGPU *pGpu);
1089
1090 NV_STATUS osUserHandleToKernelPtr(NvU32 hClient,
1091 NvP64 Handle,
1092 NvP64 *pHandle);
1093
1094 NV_STATUS osGetSmbiosTable(void **pBaseVAddr, NvU64 *pLength,
1095 NvU64 *pNumSubTypes, NvU32 *pVersion);
1096
1097 void osPutSmbiosTable(void *pBaseVAddr, NvU64 length);
1098
1099 NvBool osIsNvswitchPresent(void);
1100
1101 void osQueueMMUFaultHandler(OBJGPU *);
1102
1103 NvBool osIsGpuAccessible(OBJGPU *pGpu);
1104 NvBool osIsGpuShutdown(OBJGPU *pGpu);
1105
1106 NvBool osMatchGpuOsInfo(OBJGPU *pGpu, void *pOsInfo);
1107
1108 void osReleaseGpuOsInfo(void *pOsInfo);
1109
1110 void osGpuWriteReg008(OBJGPU *pGpu,
1111 NvU32 thisAddress,
1112 NvV8 thisValue);
1113
1114 void osDevWriteReg008(OBJGPU *pGpu,
1115 DEVICE_MAPPING *pMapping,
1116 NvU32 thisAddress,
1117 NvV8 thisValue);
1118
1119 NvU8 osGpuReadReg008(OBJGPU *pGpu,
1120 NvU32 thisAddress);
1121
1122 NvU8 osDevReadReg008(OBJGPU *pGpu,
1123 DEVICE_MAPPING *pMapping,
1124 NvU32 thisAddress);
1125
1126 void osGpuWriteReg016(OBJGPU *pGpu,
1127 NvU32 thisAddress,
1128 NvV16 thisValue);
1129
1130 void osDevWriteReg016(OBJGPU *pGpu,
1131 DEVICE_MAPPING *pMapping,
1132 NvU32 thisAddress,
1133 NvV16 thisValue);
1134
1135 NvU16 osGpuReadReg016(OBJGPU *pGpu,
1136 NvU32 thisAddress);
1137
1138 NvU16 osDevReadReg016(OBJGPU *pGpu,
1139 DEVICE_MAPPING *pMapping,
1140 NvU32 thisAddress);
1141
1142 void osGpuWriteReg032(OBJGPU *pGpu,
1143 NvU32 thisAddress,
1144 NvV32 thisValue);
1145
1146 void osDevWriteReg032(OBJGPU *pGpu,
1147 DEVICE_MAPPING *pMapping,
1148 NvU32 thisAddress,
1149 NvV32 thisValue);
1150
1151 NvU32 osGpuReadReg032(OBJGPU *pGpu,
1152 NvU32 thisAddress);
1153
1154 NvU32 osDevReadReg032(OBJGPU *pGpu,
1155 DEVICE_MAPPING *pMapping,
1156 NvU32 thisAddress);
1157
1158 NV_STATUS osIsr(OBJGPU *pGpu);
1159
1160 NV_STATUS osSanityTestIsr(OBJGPU *pGpu);
1161
1162 NV_STATUS osInitMapping(OBJGPU *pGpu);
1163
1164 NV_STATUS osVerifySystemEnvironment(OBJGPU *pGpu);
1165
1166 NV_STATUS osSanityTestIsr(OBJGPU *pGpu);
1167
1168 void osAllocatedRmClient(void* pOSInfo);
1169
1170 NV_STATUS osConfigurePcieReqAtomics(OS_GPU_INFO *pOsGpuInfo, NvU32 *pMask);
1171 NV_STATUS osGetPcieCplAtomicsCaps(OS_GPU_INFO *pOsGpuInfo, NvU32 *pMask);
1172
1173 NvBool osDmabufIsSupported(void);
1174
isrWrapper(NvBool testIntr,OBJGPU * pGpu)1175 static NV_INLINE NV_STATUS isrWrapper(NvBool testIntr, OBJGPU *pGpu)
1176 {
1177 //
1178 // If pGpu->testIntr is not true then use original osIsr function.
1179 // On VMware Esxi 6.0, both rm isr and dpc handlers are called from Esxi 6.0
1180 // dpc handler. Because of this when multiple GPU are present in the system,
1181 // we may get a call to rm_isr routine for a hw interrupt corresponding to a
1182 // previously initialized GPU. In that case we need to call original osIsr
1183 // function.
1184 //
1185
1186 NV_STATUS status = NV_OK;
1187
1188 if (testIntr)
1189 {
1190 status = osSanityTestIsr(pGpu);
1191 }
1192 else
1193 {
1194 status = osIsr(pGpu);
1195 }
1196
1197 return status;
1198 }
1199
1200 #define OS_PCIE_CAP_MASK_REQ_ATOMICS_32 NVBIT(0)
1201 #define OS_PCIE_CAP_MASK_REQ_ATOMICS_64 NVBIT(1)
1202 #define OS_PCIE_CAP_MASK_REQ_ATOMICS_128 NVBIT(2)
1203
1204 void osGetNumaMemoryUsage(NvS32 numaId, NvU64 *free_memory_bytes, NvU64 *total_memory_bytes);
1205
1206 NV_STATUS osNumaAddGpuMemory(OS_GPU_INFO *pOsGpuInfo, NvU64 offset,
1207 NvU64 size, NvU32 *pNumaNodeId);
1208 void osNumaRemoveGpuMemory(OS_GPU_INFO *pOsGpuInfo, NvU64 offset,
1209 NvU64 size, NvU32 numaNodeId);
1210
1211 NV_STATUS osOfflinePageAtAddress(NvU64 address);
1212
1213 //
1214 // Os 1Hz timer callback functions
1215 //
1216 // 1 second is the median and mean time between two callback runs, but the worst
1217 // case can be anywhere between 0 (back-to-back) or (1s+RMTIMEOUT).
1218 // N callbacks are at least (N-2) seconds apart.
1219 //
1220 // Callbacks can run at either DISPATCH_LEVEL or PASSIVE_LEVEL
1221 //
1222 NV_STATUS osInit1HzCallbacks(OBJTMR *pTmr);
1223 NV_STATUS osDestroy1HzCallbacks(OBJTMR *pTmr);
1224 NV_STATUS osSchedule1HzCallback(OBJGPU *pGpu, OS1HZPROC callback, void *pData, NvU32 flags);
1225 void osRemove1HzCallback(OBJGPU *pGpu, OS1HZPROC callback, void *pData);
1226 NvBool osRun1HzCallbacksNow(OBJGPU *pGpu);
1227 void osRunQueued1HzCallbacksUnderLock(OBJGPU *pGpu);
1228
1229 NV_STATUS osDoFunctionLevelReset(OBJGPU *pGpu);
1230
1231 void vgpuDevWriteReg032(
1232 OBJGPU *pGpu,
1233 NvU32 thisAddress,
1234 NvV32 thisValue,
1235 NvBool *vgpuHandled
1236 );
1237
1238 NvU32 vgpuDevReadReg032(
1239 OBJGPU *pGpu,
1240 NvU32 thisAddress,
1241 NvBool *vgpuHandled
1242 );
1243
1244 void osInitSystemStaticConfig(SYS_STATIC_CONFIG *);
1245
1246 void osDbgBugCheckOnAssert(void);
1247
1248 NvBool osBugCheckOnTimeoutEnabled(void);
1249
1250 //
1251 // TODO: to clean-up the rest of the list
1252 //
1253 OSAttachGpu osAttachGpu;
1254 OSDpcAttachGpu osDpcAttachGpu;
1255 OSDpcDetachGpu osDpcDetachGpu;
1256 OSHandleGpuLost osHandleGpuLost;
1257 OSHandleGpuSurpriseRemoval osHandleGpuSurpriseRemoval;
1258 OSInitScalabilityOptions osInitScalabilityOptions;
1259 OSQueueDpc osQueueDpc;
1260 OSSetEvent osSetEvent;
1261 OSEventNotification osEventNotification;
1262 OSEventNotificationWithInfo osEventNotificationWithInfo;
1263 OSObjectEventNotification osObjectEventNotification;
1264 OSNotifyEvent osNotifyEvent;
1265 OSFlushCpuWriteCombineBuffer osFlushCpuWriteCombineBuffer;
1266 OSDelay osDelay;
1267 OSSpinLoop osSpinLoop;
1268 OSDelayUs osDelayUs;
1269 OSDelayNs osDelayNs;
1270 OSGetCpuCount osGetCpuCount;
1271 OSGetMaximumCoreCount osGetMaximumCoreCount;
1272 OSGetCurrentProcessorNumber osGetCurrentProcessorNumber;
1273 OSGetVersionDump osGetVersionDump;
1274
1275 OSGetMaxUserVa osGetMaxUserVa;
1276 OSGetCpuVaAddrShift osGetCpuVaAddrShift;
1277 OSMemAddFilter osMemAddFilter;
1278 OSMemRemoveFilter osMemRemoveFilter;
1279 OSMemGetFilter osMemGetFilter;
1280
1281 OSAllocPagesInternal osAllocPagesInternal;
1282 OSFreePagesInternal osFreePagesInternal;
1283
1284 OSGetPageSize osGetPageSize;
1285 OSGetPageShift osGetPageShift;
1286 OSNumaMemblockSize osNumaMemblockSize;
1287 OSNumaOnliningEnabled osNumaOnliningEnabled;
1288 OSAllocPagesNode osAllocPagesNode;
1289 OSAllocAcquirePage osAllocAcquirePage;
1290 OSAllocReleasePage osAllocReleasePage;
1291 OSGetPageRefcount osGetPageRefcount;
1292 OSCountTailPages osCountTailPages;
1293 OSVirtualToPhysicalAddr osKernVirtualToPhysicalAddr;
1294 OSLockMem osLockMem;
1295 OSUnlockMem osUnlockMem;
1296 OSMapSystemMemory osMapSystemMemory;
1297 OSUnmapSystemMemory osUnmapSystemMemory;
1298 OSWriteRegistryDword osWriteRegistryDword;
1299 OSReadRegistryDword osReadRegistryDword;
1300 OSReadRegistryString osReadRegistryString;
1301 OSWriteRegistryBinary osWriteRegistryBinary;
1302 OSWriteRegistryVolatile osWriteRegistryVolatile;
1303 OSReadRegistryVolatile osReadRegistryVolatile;
1304 OSReadRegistryVolatileSize osReadRegistryVolatileSize;
1305 OSReadRegistryBinary osReadRegistryBinary;
1306 OSReadRegistryDwordBase osReadRegistryDwordBase;
1307 OSReadRegistryStringBase osReadRegistryStringBase;
1308 OSPackageRegistry osPackageRegistry;
1309 OSUnpackageRegistry osUnpackageRegistry;
1310 NV_STATUS osDestroyRegistry(void);
1311 nv_reg_entry_t* osGetRegistryList(void);
1312 NV_STATUS osSetRegistryList(nv_reg_entry_t *pRegList);
1313 OSMapPciMemoryUser osMapPciMemoryUser;
1314 OSUnmapPciMemoryUser osUnmapPciMemoryUser;
1315 OSMapPciMemoryKernelOld osMapPciMemoryKernelOld;
1316 OSMapPciMemoryKernel64 osMapPciMemoryKernel64;
1317 OSUnmapPciMemoryKernelOld osUnmapPciMemoryKernelOld;
1318 OSUnmapPciMemoryKernel64 osUnmapPciMemoryKernel64;
1319 OSMapGPU osMapGPU;
1320 OSUnmapGPU osUnmapGPU;
1321 OSLockShouldToggleInterrupts osLockShouldToggleInterrupts;
1322
1323 OSGetPerformanceCounter osGetPerformanceCounter;
1324
1325 OSI2CClosePorts osI2CClosePorts;
1326 OSWriteI2CBufferDirect osWriteI2CBufferDirect;
1327 OSReadI2CBufferDirect osReadI2CBufferDirect;
1328 OSI2CTransfer osI2CTransfer;
1329 OSSetGpuRailVoltage osSetGpuRailVoltage;
1330 OSGetGpuRailVoltage osGetGpuRailVoltage;
1331 OSGetChipInfo osGetChipInfo;
1332 OSGetGpuRailVoltageInfo osGetGpuRailVoltageInfo;
1333
1334 OSGetCurrentProcess osGetCurrentProcess;
1335 OSGetCurrentProcessName osGetCurrentProcessName;
1336 OSGetCurrentThread osGetCurrentThread;
1337 OSAttachToProcess osAttachToProcess;
1338 OSDetachFromProcess osDetachFromProcess;
1339 OSPollHotkeyState osPollHotkeyState;
1340
1341 OSIsRaisedIRQL osIsRaisedIRQL;
1342 OSIsISR osIsISR;
1343 OSGetDriverBlock osGetDriverBlock;
1344
1345 OSSyncWithRmDestroy osSyncWithRmDestroy;
1346 OSSyncWithGpuDestroy osSyncWithGpuDestroy;
1347
1348 OSModifyGpuSwStatePersistence osModifyGpuSwStatePersistence;
1349
1350 OSHandleDeferredRecovery osHandleDeferredRecovery;
1351 OSIsSwPreInitOnly osIsSwPreInitOnly;
1352 OSGetCarveoutInfo osGetCarveoutInfo;
1353 OSGetVPRInfo osGetVPRInfo;
1354 OSAllocInVPR osAllocInVPR;
1355 OSGetGenCarveout osGetGenCarveout;
1356 OSGetSysmemInfo osGetSysmemInfo;
1357 OSGC6PowerControl osGC6PowerControl;
1358 OSReadPFPciConfigInVF osReadPFPciConfigInVF;
1359
1360 OSAcquireRmSema osAcquireRmSema;
1361 OSAcquireRmSema osAcquireRmSemaForced;
1362 OSCondAcquireRmSema osCondAcquireRmSema;
1363 OSReleaseRmSema osReleaseRmSema;
1364
1365 //
1366 // When the new basic lock model is enabled then the following legacy RM
1367 // system semaphore routines are stubbed.
1368 //
1369 #define osAllocRmSema(s) (NV_OK)
1370 #define osFreeRmSema(s)
1371 #define osIsAcquiredRmSema(s) (NV_TRUE)
1372 #define osIsRmSemaOwner(s) (NV_TRUE)
1373 #define osCondReleaseRmSema(s) (NV_TRUE)
1374 #define osAcquireRmSemaForced(s) osAcquireRmSema(s)
1375 #define osGpuLockSetOwner(s,t) (NV_OK)
1376
1377 OSApiLockAcquireConfigureFlags osApiLockAcquireConfigureFlags;
1378 OSGpuLocksQueueRelease osGpuLocksQueueRelease;
1379
1380 OSFlushLog osFlushLog;
1381 OSSetSurfaceName osSetSurfaceName;
1382
1383 #define MODS_ARCH_ERROR_PRINTF(format, ...)
1384 #define MODS_ARCH_INFO_PRINTF(format, ...)
1385 #define MODS_ARCH_REPORT(event, format, ...)
1386
1387
1388 #define osAllocPages(a) osAllocPagesInternal(a)
1389 #define osFreePages(a) osFreePagesInternal(a)
1390
1391 extern NV_STATUS constructObjOS(struct OBJOS *);
1392 extern void osInitObjOS(struct OBJOS *);
1393
1394 extern OSGetTimeoutParams osGetTimeoutParams;
1395
1396 //
1397 // NV OS simulation mode defines
1398 // Keep in sync with gpu.h SIM MODE defines until osGetSimulationMode is deprecated.
1399 //
1400 #ifndef NV_SIM_MODE_DEFS
1401 #define NV_SIM_MODE_DEFS
1402 #define NV_SIM_MODE_HARDWARE 0U
1403 #define NV_SIM_MODE_RTL 1U
1404 #define NV_SIM_MODE_CMODEL 2U
1405 #define NV_SIM_MODE_MODS_AMODEL 3U
1406 #define NV_SIM_MODE_TEGRA_FPGA 4U
1407 #define NV_SIM_MODE_INVALID (~0x0U)
1408 #endif
1409
1410 //
1411 // NV Heap control defines
1412 //
1413 #define NV_HEAP_CONTROL_INTERNAL 0
1414 #define NV_HEAP_CONTROL_EXTERNAL 1
1415
1416 // osDelayUs flags
1417 #define OSDELAYUS_FLAGS_USE_TMR_DELAY NVBIT(0)
1418
1419 // osEventNotification notifyIndex all value
1420 #define OS_EVENT_NOTIFICATION_INDEX_ALL (0xffffffff)
1421
1422 // tells osEventNotification to only issue notifies/events on this subdev
1423 #define OS_EVENT_NOTIFICATION_INDEX_MATCH_SUBDEV (0x10000000)
1424
1425 // Notify callback action
1426 #define NV_OS_WRITE_THEN_AWAKEN 0x00000001
1427
1428 //
1429 // Include per-OS definitions
1430 //
1431 // #ifdef out for nvoctrans, this hides include to system headers which
1432 // breaks the tool.
1433 //
1434 // TODO - we should delete the per-OS os_custom.h files exposed to
1435 // OS-agnostic code. Cross-OS code shouldn't pull in per-OS headers or
1436 // per-OS definitions.
1437 //
1438 #pragma once
1439 #include "os_custom.h"
1440
1441 #define NV_SEMA_RELEASE_SUCCEED 0 // lock released, no waiting thread to notify
1442 #define NV_SEMA_RELEASE_FAILED 1 // failed to lock release
1443 #define NV_SEMA_RELEASE_NOTIFIED 2 // lock released, notify waiting thread
1444 #define NV_SEMA_RELEASE_DPC_QUEUED 3 // lock released, queue DPC to notify waiting thread
1445 #define NV_SEMA_RELEASE_DPC_FAILED 4 // lock released, but failed to queue a DPC to notify waiting thread
1446
1447 #define ADD_PROBE(pGpu, probeId)
1448
1449 #define IS_SIM_MODS(pOS) (pOS->bIsSimMods)
1450
1451 #endif // _OS_H_
1452
1453 #ifdef __cplusplus
1454 } // extern "C"
1455 #endif
1456
1457 #endif // _G_OS_NVOC_H_
1458