1
2 #ifndef _G_CHIPSET_NVOC_H_
3 #define _G_CHIPSET_NVOC_H_
4 #include "nvoc/runtime.h"
5
6 // Version of generated metadata structures
7 #ifdef NVOC_METADATA_VERSION
8 #undef NVOC_METADATA_VERSION
9 #endif
10 #define NVOC_METADATA_VERSION 0
11
12 #ifdef __cplusplus
13 extern "C" {
14 #endif
15
16 /*
17 * SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
18 * SPDX-License-Identifier: MIT
19 *
20 * Permission is hereby granted, free of charge, to any person obtaining a
21 * copy of this software and associated documentation files (the "Software"),
22 * to deal in the Software without restriction, including without limitation
23 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
24 * and/or sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following conditions:
26 *
27 * The above copyright notice and this permission notice shall be included in
28 * all copies or substantial portions of the Software.
29 *
30 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
31 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
32 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
33 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
34 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
35 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
36 * DEALINGS IN THE SOFTWARE.
37 */
38
39 #pragma once
40 #include "g_chipset_nvoc.h"
41
42 #ifndef CHIPSET_H
43 #define CHIPSET_H
44
45 /**************** Resource Manager Defines and Structures ******************\
46 * *
47 * Defines and structures used for the Core Logic Object. *
48 * *
49 \***************************************************************************/
50
51 #include "platform/hwbc.h"
52
53 // forward declare PcieAerCapability struct
54 struct PcieAerCapability;
55
56 // forward declaration of PexL1SubstateCapability
57 struct PexL1SubstateCapability;
58
59 // PCIe Enhanced Configuration space structure
60 typedef struct PCIECONFIGSPACEBASE PCIECONFIGSPACEBASE;
61 typedef struct PCIECONFIGSPACEBASE *PPCIECONFIGSPACEBASE;
62 struct PCIECONFIGSPACEBASE
63 {
64 RmPhysAddr baseAddress;
65 NvU32 domain;
66 NvU8 startBusNumber;
67 NvU8 endBusNumber;
68 PPCIECONFIGSPACEBASE next;
69 };
70
71 // Seen in both nvagp.c and elsewhere
72 #define PCI_MAX_DOMAINS 65536
73 #define PCI_MAX_BUSES 256
74 #define PCI_MAX_DEVICES 32
75 #define PCI_CLASS_DISPLAY_DEV 0x03
76 #define PCI_COMMAND 0x04
77 #define PCI_BASE_ADDRESS_0 0x10 /* Aperture Base */
78
79 #define PCI_VENDOR_ID_AMD 0x1022
80 #define PCI_VENDOR_ID_ALI 0x10B9
81 #define PCI_VENDOR_ID_NVIDIA 0x10DE
82
83 #define CL_MAX_LINK_WIDTH(p) ((p & 0x3f0) >> 4) // Max Link width is 9:4
84 // CL_IS_ROOT_PORT() returns NV_TRUE if root port of PCI-E Root Complex
85 // Device/Port type is 23:20
86 // Root port is 0100b
87 #define CL_IS_ROOT_PORT(p) (((p & 0xf00000) >> 20) == 0x4)
88 #define CL_IS_UPSTREAM_PORT(p) (((p & 0xf00000) >> 20) == 0x5)
89 #define CL_IS_DOWNSTREAM_PORT(p) (((p & 0xf00000) >> 20) == 0x6)
90 #define CL_AVG_LINK_WIDTH 8
91 #define CL_DAGWOOD_LINK_WIDTH 8
92 #define CL_SINGLE_DW_LINK_WIDTH 8
93
94 //
95 // Offset arguments to Pcie[Read|WriteRoot]PortConfigReg
96 //
97
98 // PCI Express capability
99 #define CL_PCIE_BEGIN 0x0100
100 #define CL_PCIE_CAP (CL_PCIE_BEGIN + 0x00)
101 #define CL_PCIE_DEV_CAP (CL_PCIE_BEGIN + 0x04)
102 #define CL_PCIE_DEV_CTRL_STATUS (CL_PCIE_BEGIN + 0x08)
103 #define CL_PCIE_LINK_CAP (CL_PCIE_BEGIN + 0x0C)
104 #define CL_PCIE_LINK_CTRL_STATUS (CL_PCIE_BEGIN + 0x10)
105 #define CL_PCIE_SLOT_CAP (CL_PCIE_BEGIN + 0x14)
106 #define CL_PCIE_SLOT_CTRL_STATUS (CL_PCIE_BEGIN + 0x18)
107 #define CL_PCIE_ROOT_CTRL_RSVDP (CL_PCIE_BEGIN + 0x1C)
108 #define CL_PCIE_ROOT_STATUS (CL_PCIE_BEGIN + 0x20)
109 #define CL_PCIE_DEV_CAP_2 (CL_PCIE_BEGIN + 0x24)
110 #define CL_PCIE_DEV_CTRL_2 (CL_PCIE_BEGIN + 0x28)
111 #define CL_PCIE_END (CL_PCIE_BEGIN + 0x2C)
112
113 // PCI Express Capabilities
114 #define CL_PCIE_CAP_SLOT NVBIT(24)
115
116 // PCI Express Link Control ASPM Control Bits
117 #define CL_PCIE_LINK_CTRL_STATUS_ASPM_L0S_BIT NVBIT(0)
118 #define CL_PCIE_LINK_CTRL_STATUS_ASPM_L1_BIT NVBIT(1)
119 #define CL_PCIE_LINK_CTRL_STATUS_ASPM_MASK \
120 (CL_PCIE_LINK_CTRL_STATUS_ASPM_L0S_BIT|CL_PCIE_LINK_CTRL_STATUS_ASPM_L1_BIT)
121
122 // PCI Express Link control ASPM capability Bits
123 #define CL_PCIE_LINK_CAP_ASPM_L0S_BIT NVBIT(10)
124 #define CL_PCIE_LINK_CAP_ASPM_L1_BIT NVBIT(11)
125 #define CL_PCIE_LINK_CAP_CLOCK_PM_BIT NVBIT(18)
126
127 // PCI Express Slot Capabilities
128 #define CL_PCIE_SLOT_CAP_HOTPLUG_SURPRISE NVBIT(5)
129 #define CL_PCIE_SLOT_CAP_HOTPLUG_CAPABLE NVBIT(6)
130
131 //
132 // CL_DEVICE_CONTROL_STATUS bits for hal
133 //
134 // From PCI-E manual
135 #define CL_PCIE_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED NVBIT(16)
136 #define CL_PCIE_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED NVBIT(17)
137 #define CL_PCIE_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED NVBIT(18)
138 #define CL_PCIE_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED NVBIT(19)
139
140 // PCI Express Latency Tolerance Reporting Capability Bit
141 #define CL_PCIE_DEV_CAP_2_LTR_SUPPORTED_BIT NVBIT(11)
142 #define CL_PCIE_DEV_CTRL_2_LTR_ENABLED_BIT NVBIT(10)
143
144 // Advanced Error Reporting capability
145 #define CL_AER_BEGIN 0x0200
146 #define CL_AER_CAP (CL_AER_BEGIN + 0x00)
147 #define CL_AER_UNCORRECTABLE_STATUS (CL_AER_BEGIN + 0x04)
148 #define CL_AER_UNCORRECTABLE_MASK (CL_AER_BEGIN + 0x08)
149 #define CL_AER_UNCORRECTABLE_SEVERITY (CL_AER_BEGIN + 0x0C)
150 #define CL_AER_CORRECTABLE_STATUS (CL_AER_BEGIN + 0x10)
151 #define CL_AER_CORRECTABLE_MASK (CL_AER_BEGIN + 0x14)
152 #define CL_AER_ADVANCED_CAP_CONTROL (CL_AER_BEGIN + 0x18)
153 #define CL_AER_HEADER_LOG (CL_AER_BEGIN + 0x1C)
154 #define CL_AER_ROOT_ERROR_COMMAND (CL_AER_BEGIN + 0x2C)
155 #define CL_AER_ROOT_ERROR_STATUS (CL_AER_BEGIN + 0x30)
156 #define CL_AER_ERROR_SOURCE (CL_AER_BEGIN + 0x34)
157 #define CL_AER_END (CL_AER_BEGIN + 0x34)
158
159 // PCI Express Device Capabilities 2
160 #define CL_PCIE_DEV_CAP_2_ATOMICS_SUPPORTED_BIT NVBIT(6)
161 #define CL_PCIE_DEV_CAP_2_ATOMIC_32BIT NVBIT(7)
162 #define CL_PCIE_DEV_CAP_2_ATOMIC_64BIT NVBIT(8)
163 #define CL_PCIE_DEV_CAP_2_ATOMIC_128BIT NVBIT(9)
164
165 // PCI Express Device Control & Status 2
166 #define CL_PCIE_DEV_CTRL_2_ATOMICS_EGRESS_BLOCK_BIT NVBIT(7)
167
168 // Defines for Atomic Mask
169 #define CL_ATOMIC_32BIT NVBIT(0)
170 #define CL_ATOMIC_64BIT NVBIT(1)
171 #define CL_ATOMIC_128BIT NVBIT(2)
172
173 #define CL_IS_L0_SUPPORTED(p) (((p) & CL_PCIE_LINK_CAP_ASPM_L0S_BIT))
174 #define CL_IS_L1_SUPPORTED(p) (((p) & CL_PCIE_LINK_CAP_ASPM_L1_BIT))
175
176 #define CL_IS_LTR_PORT_SUPPORTED(p) (((p) & CL_PCIE_DEV_CAP_2_LTR_SUPPORTED_BIT))
177 #define CL_IS_LTR_PORT_ENABLED(p) (((p) & CL_PCIE_DEV_CTRL_2_LTR_ENABLED_BIT))
178
179 #define CL_IS_ATOMICS_SUPPORTED(p) (((p) & CL_PCIE_DEV_CAP_2_ATOMICS_SUPPORTED_BIT))
180 #define CL_IS_ATOMICS_EGRESS_BLOCKED(p) (((p) & CL_PCIE_DEV_CTRL_2_ATOMICS_EGRESS_BLOCK_BIT))
181
182 #define CL_IS_32BIT_ATOMICS_SUPPORTED(p) (((p) & CL_PCIE_DEV_CAP_2_ATOMIC_32BIT))
183 #define CL_IS_64BIT_ATOMICS_SUPPORTED(p) (((p) & CL_PCIE_DEV_CAP_2_ATOMIC_64BIT))
184 #define CL_IS_128BIT_ATOMICS_SUPPORTED(p) (((p) & CL_PCIE_DEV_CAP_2_ATOMIC_128BIT))
185
186 //
187 // This defines PCI-E Advanced Error Reporting Capability structure per PCI-E manual
188 // (refer to section 7.10 of PCI Express Base Specification, v1.1)
189 //
190 typedef struct PcieAerCapability
191 {
192 NvU32 PexEnhCapHeader; // (+0x00) PCI-E Enhanced Capability Header
193 NvU32 UncorrErrStatusReg; // (+0x04) Uncorrectable Error Status Register
194 NvU32 UncorrErrMaskReg; // (+0x08) Uncorrectable Error Mask Register
195 NvU32 UncorrErrSeverityReg; // (+0x0C) Uncorrectable Error Severity Register
196 NvU32 CorrErrStatusReg; // (+0x10) Correctable Error Status Register
197 NvU32 CorrErrMaskReg; // (+0x14) Correctable Error Mask Register
198 NvU32 AEcapCrtlReg; // (+0x18) Advanced Error Capability and Control Register
199 struct { // (+0x1C) Header Log Register
200 NvU32 Header[4]; // (+0x1C-0x2B)
201 } HeaderLogReg;
202 NvU32 RootErrCmd; // (+0x2C) Root Error Command
203 NvU32 RooErrStatus; // (+0x30) Root Error Status
204 NvU32 ErrSrcReg; // (+0x34) Error Source Register (Correctable Err Src Id + Err Src Id)
205 } PcieAerCapability, *PPcieAerCapability;
206
207 // Virtual Channel Capability
208 #define CL_VC_BEGIN 0x0300
209 #define CL_VC_RESOURCE_CTRL_0 (CL_VC_BEGIN + 0x14)
210 #define CL_VC_END (CL_VC_BEGIN + 0x1C)
211
212 typedef struct
213 {
214 NvU16 deviceID; // deviceID
215 NvU16 vendorID; // vendorID
216 NvU16 subdeviceID; // subsystem deviceID
217 NvU16 subvendorID; // subsystem vendorID
218 NvU8 revisionID; // revision ID
219 } BUSINFO;
220
221 // L1 PM substates Capability
222 #define CL_L1_SS_BEGIN 0x0400
223 #define CL_L1_SS_CAP_HDR (CL_L1_SS_BEGIN + 0x00)
224 #define CL_L1_SS_CAP_REG (CL_L1_SS_BEGIN + 0x04)
225 #define CL_L1_SS_CTRL1_REG (CL_L1_SS_BEGIN + 0x08)
226 #define CL_L1_SS_CTRL2_REG (CL_L1_SS_BEGIN + 0x0C)
227 #define CL_L1_SS_END CL_L1_SS_CTRL2_REG
228
229 //
230 // This defines PCI-E L1 PM Substates Extended Capability structure per PCI-E manual
231 // (refer to section 7.xx of ECN_L1_PM_Substates_with_CLKREQ_31_May_2013_Rev10a.pdf
232 //
233 typedef struct PexL1SubstateCapability
234 {
235 NvU32 PexEnhCapHeader; // (+0x00) PCI-E Enhanced Capability Header
236 NvU32 Capabilities; // (+0x04) L1 PM Substates capabilities Register
237 NvU32 Control1Reg; // (+0x08) L1 PM Substates Control1 Register
238 NvU32 Control2Reg; // (+0x0C) L1 PM Substates Control2 Register
239 } PexL1SubstateCapability, *PPexL1SubstateCapability;
240
241 typedef struct BUSTOPOLOGYINFO BUSTOPOLOGYINFO;
242 typedef struct BUSTOPOLOGYINFO *PBUSTOPOLOGYINFO;
243 struct BUSTOPOLOGYINFO
244 {
245 PBUSTOPOLOGYINFO next;
246 void *handle;
247 BUSINFO busInfo;
248 NvU32 domain;
249 NvU8 bus, device, func, secBus;
250 NvU16 pciSubBaseClass;
251 NvBool bVgaAdapter;
252 };
253
254 typedef struct GspSystemInfo GspSystemInfo;
255
256
257 // Private field names are wrapped in PRIVATE_FIELD, which does nothing for
258 // the matching C source file, but causes diagnostics to be issued if another
259 // source file references the field.
260 #ifdef NVOC_CHIPSET_H_PRIVATE_ACCESS_ALLOWED
261 #define PRIVATE_FIELD(x) x
262 #else
263 #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x)
264 #endif
265
266
267 struct OBJCL {
268
269 // Metadata
270 const struct NVOC_RTTI *__nvoc_rtti;
271
272 // Parent (i.e. superclass or base class) object pointers
273 struct Object __nvoc_base_Object;
274
275 // Ancestor object pointers for `staticCast` feature
276 struct Object *__nvoc_pbase_Object; // obj super
277 struct OBJCL *__nvoc_pbase_OBJCL; // cl
278
279 // 37 PDB properties
280 NvBool PDB_PROP_CL_PCIE_CONFIG_ACCESSIBLE;
281 NvBool PDB_PROP_CL_DISABLE_BR03_FLOW_CONTROL;
282 NvBool PDB_PROP_CL_ASLM_SUPPORTS_NV_LINK_UPGRADE;
283 NvBool PDB_PROP_CL_ASLM_SUPPORTS_FAST_LINK_UPGRADE;
284 NvBool PDB_PROP_CL_ASLM_SUPPORTS_HOT_RESET;
285 NvBool PDB_PROP_CL_ASLM_SUPPORTS_GEN2_LINK_UPGRADE;
286 NvBool PDB_PROP_CL_FORCE_SNOOP_READS_AND_WRITES_WAR_BUG_410390;
287 NvBool PDB_PROP_CL_IS_CHIPSET_IN_ASPM_POR_LIST;
288 NvBool PDB_PROP_CL_ASPM_L0S_CHIPSET_DISABLED;
289 NvBool PDB_PROP_CL_ASPM_L1_CHIPSET_DISABLED;
290 NvBool PDB_PROP_CL_ASPM_L0S_CHIPSET_ENABLED_MOBILE_ONLY;
291 NvBool PDB_PROP_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY;
292 NvBool PDB_PROP_CL_ASPM_UPSTREAM_PORT_L1_MASK_ENABLED;
293 NvBool PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED;
294 NvBool PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED_GEFORCE;
295 NvBool PDB_PROP_CL_EXTENDED_TAG_FIELD_NOT_CAPABLE;
296 NvBool PDB_PROP_CL_NOSNOOP_NOT_CAPABLE;
297 NvBool PDB_PROP_CL_RELAXED_ORDERING_NOT_CAPABLE;
298 NvBool PDB_PROP_CL_PCIE_FORCE_GEN2_ENABLE;
299 NvBool PDB_PROP_CL_PCIE_GEN2_AT_LESS_THAN_X16_DISABLED;
300 NvBool PDB_PROP_CL_ROOTPORT_NEEDS_NOSNOOP_WAR;
301 NvBool PDB_PROP_CL_INTEL_CPU_ROOTPORT1_NEEDS_H57_WAR;
302 NvBool PDB_PROP_CL_PCIE_CONFIG_SKIP_MCFG_READ;
303 NvBool PDB_PROP_CL_ON_PCIE_GEN3_PATSBURG;
304 NvBool PDB_PROP_CL_IS_EXTERNAL_GPU;
305 NvBool PDB_PROP_CL_ALLOW_PCIE_GEN3_ON_PATSBURG_WITH_IVBE_CPU;
306 NvBool PDB_PROP_CL_BUG_999673_P2P_ARBITRARY_SPLIT_WAR;
307 NvBool PDB_PROP_CL_UPSTREAM_LTR_SUPPORTED;
308 NvBool PDB_PROP_CL_BUG_1340801_DISABLE_GEN3_ON_GIGABYTE_SNIPER_3;
309 NvBool PDB_PROP_CL_BUG_1681803_WAR_DISABLE_MSCG;
310 NvBool PDB_PROP_CL_PCIE_NON_COHERENT_USE_TC0_ONLY;
311 NvBool PDB_PROP_CL_UNSUPPORTED_CHIPSET;
312 NvBool PDB_PROP_CL_IS_CHIPSET_IO_COHERENT;
313 NvBool PDB_PROP_CL_DISABLE_IOMAP_WC;
314 NvBool PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE;
315 NvBool PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR;
316 NvBool PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS;
317
318 // Data members
319 NBADDR NBAddr;
320 NvBool EnteredRecoverySinceErrorsLastChecked;
321 struct OBJHWBC *pHWBC;
322 NvU32 br04HwbcCount;
323 NBADDR FHBAddr;
324 BUSINFO FHBBusInfo;
325 NvU32 Chipset;
326 NvU32 ChipsetSliBondType;
327 NvBool ChipsetInitialized;
328 PPCIECONFIGSPACEBASE pPcieConfigSpaceBase;
329 NBADDR chipsetIDBusAddr;
330 BUSINFO chipsetIDInfo;
331 PBUSTOPOLOGYINFO pBusTopologyInfo;
332 };
333
334 #ifndef __NVOC_CLASS_OBJCL_TYPEDEF__
335 #define __NVOC_CLASS_OBJCL_TYPEDEF__
336 typedef struct OBJCL OBJCL;
337 #endif /* __NVOC_CLASS_OBJCL_TYPEDEF__ */
338
339 #ifndef __nvoc_class_id_OBJCL
340 #define __nvoc_class_id_OBJCL 0x547dbb
341 #endif /* __nvoc_class_id_OBJCL */
342
343 // Casting support
344 extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJCL;
345
346 #define __staticCast_OBJCL(pThis) \
347 ((pThis)->__nvoc_pbase_OBJCL)
348
349 #ifdef __nvoc_chipset_h_disabled
350 #define __dynamicCast_OBJCL(pThis) ((OBJCL*)NULL)
351 #else //__nvoc_chipset_h_disabled
352 #define __dynamicCast_OBJCL(pThis) \
353 ((OBJCL*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(OBJCL)))
354 #endif //__nvoc_chipset_h_disabled
355
356 // Property macros
357 #define PDB_PROP_CL_PCIE_CONFIG_SKIP_MCFG_READ_BASE_CAST
358 #define PDB_PROP_CL_PCIE_CONFIG_SKIP_MCFG_READ_BASE_NAME PDB_PROP_CL_PCIE_CONFIG_SKIP_MCFG_READ
359 #define PDB_PROP_CL_EXTENDED_TAG_FIELD_NOT_CAPABLE_BASE_CAST
360 #define PDB_PROP_CL_EXTENDED_TAG_FIELD_NOT_CAPABLE_BASE_NAME PDB_PROP_CL_EXTENDED_TAG_FIELD_NOT_CAPABLE
361 #define PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED_GEFORCE_BASE_CAST
362 #define PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED_GEFORCE_BASE_NAME PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED_GEFORCE
363 #define PDB_PROP_CL_UPSTREAM_LTR_SUPPORTED_BASE_CAST
364 #define PDB_PROP_CL_UPSTREAM_LTR_SUPPORTED_BASE_NAME PDB_PROP_CL_UPSTREAM_LTR_SUPPORTED
365 #define PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS_BASE_CAST
366 #define PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS_BASE_NAME PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS
367 #define PDB_PROP_CL_BUG_1681803_WAR_DISABLE_MSCG_BASE_CAST
368 #define PDB_PROP_CL_BUG_1681803_WAR_DISABLE_MSCG_BASE_NAME PDB_PROP_CL_BUG_1681803_WAR_DISABLE_MSCG
369 #define PDB_PROP_CL_ON_PCIE_GEN3_PATSBURG_BASE_CAST
370 #define PDB_PROP_CL_ON_PCIE_GEN3_PATSBURG_BASE_NAME PDB_PROP_CL_ON_PCIE_GEN3_PATSBURG
371 #define PDB_PROP_CL_ASLM_SUPPORTS_NV_LINK_UPGRADE_BASE_CAST
372 #define PDB_PROP_CL_ASLM_SUPPORTS_NV_LINK_UPGRADE_BASE_NAME PDB_PROP_CL_ASLM_SUPPORTS_NV_LINK_UPGRADE
373 #define PDB_PROP_CL_ASPM_L1_CHIPSET_DISABLED_BASE_CAST
374 #define PDB_PROP_CL_ASPM_L1_CHIPSET_DISABLED_BASE_NAME PDB_PROP_CL_ASPM_L1_CHIPSET_DISABLED
375 #define PDB_PROP_CL_RELAXED_ORDERING_NOT_CAPABLE_BASE_CAST
376 #define PDB_PROP_CL_RELAXED_ORDERING_NOT_CAPABLE_BASE_NAME PDB_PROP_CL_RELAXED_ORDERING_NOT_CAPABLE
377 #define PDB_PROP_CL_ASPM_UPSTREAM_PORT_L1_MASK_ENABLED_BASE_CAST
378 #define PDB_PROP_CL_ASPM_UPSTREAM_PORT_L1_MASK_ENABLED_BASE_NAME PDB_PROP_CL_ASPM_UPSTREAM_PORT_L1_MASK_ENABLED
379 #define PDB_PROP_CL_PCIE_GEN2_AT_LESS_THAN_X16_DISABLED_BASE_CAST
380 #define PDB_PROP_CL_PCIE_GEN2_AT_LESS_THAN_X16_DISABLED_BASE_NAME PDB_PROP_CL_PCIE_GEN2_AT_LESS_THAN_X16_DISABLED
381 #define PDB_PROP_CL_UNSUPPORTED_CHIPSET_BASE_CAST
382 #define PDB_PROP_CL_UNSUPPORTED_CHIPSET_BASE_NAME PDB_PROP_CL_UNSUPPORTED_CHIPSET
383 #define PDB_PROP_CL_ASLM_SUPPORTS_GEN2_LINK_UPGRADE_BASE_CAST
384 #define PDB_PROP_CL_ASLM_SUPPORTS_GEN2_LINK_UPGRADE_BASE_NAME PDB_PROP_CL_ASLM_SUPPORTS_GEN2_LINK_UPGRADE
385 #define PDB_PROP_CL_IS_CHIPSET_IN_ASPM_POR_LIST_BASE_CAST
386 #define PDB_PROP_CL_IS_CHIPSET_IN_ASPM_POR_LIST_BASE_NAME PDB_PROP_CL_IS_CHIPSET_IN_ASPM_POR_LIST
387 #define PDB_PROP_CL_BUG_999673_P2P_ARBITRARY_SPLIT_WAR_BASE_CAST
388 #define PDB_PROP_CL_BUG_999673_P2P_ARBITRARY_SPLIT_WAR_BASE_NAME PDB_PROP_CL_BUG_999673_P2P_ARBITRARY_SPLIT_WAR
389 #define PDB_PROP_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY_BASE_CAST
390 #define PDB_PROP_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY_BASE_NAME PDB_PROP_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY
391 #define PDB_PROP_CL_ALLOW_PCIE_GEN3_ON_PATSBURG_WITH_IVBE_CPU_BASE_CAST
392 #define PDB_PROP_CL_ALLOW_PCIE_GEN3_ON_PATSBURG_WITH_IVBE_CPU_BASE_NAME PDB_PROP_CL_ALLOW_PCIE_GEN3_ON_PATSBURG_WITH_IVBE_CPU
393 #define PDB_PROP_CL_PCIE_FORCE_GEN2_ENABLE_BASE_CAST
394 #define PDB_PROP_CL_PCIE_FORCE_GEN2_ENABLE_BASE_NAME PDB_PROP_CL_PCIE_FORCE_GEN2_ENABLE
395 #define PDB_PROP_CL_DISABLE_BR03_FLOW_CONTROL_BASE_CAST
396 #define PDB_PROP_CL_DISABLE_BR03_FLOW_CONTROL_BASE_NAME PDB_PROP_CL_DISABLE_BR03_FLOW_CONTROL
397 #define PDB_PROP_CL_DISABLE_IOMAP_WC_BASE_CAST
398 #define PDB_PROP_CL_DISABLE_IOMAP_WC_BASE_NAME PDB_PROP_CL_DISABLE_IOMAP_WC
399 #define PDB_PROP_CL_PCIE_CONFIG_ACCESSIBLE_BASE_CAST
400 #define PDB_PROP_CL_PCIE_CONFIG_ACCESSIBLE_BASE_NAME PDB_PROP_CL_PCIE_CONFIG_ACCESSIBLE
401 #define PDB_PROP_CL_NOSNOOP_NOT_CAPABLE_BASE_CAST
402 #define PDB_PROP_CL_NOSNOOP_NOT_CAPABLE_BASE_NAME PDB_PROP_CL_NOSNOOP_NOT_CAPABLE
403 #define PDB_PROP_CL_ASPM_L0S_CHIPSET_DISABLED_BASE_CAST
404 #define PDB_PROP_CL_ASPM_L0S_CHIPSET_DISABLED_BASE_NAME PDB_PROP_CL_ASPM_L0S_CHIPSET_DISABLED
405 #define PDB_PROP_CL_INTEL_CPU_ROOTPORT1_NEEDS_H57_WAR_BASE_CAST
406 #define PDB_PROP_CL_INTEL_CPU_ROOTPORT1_NEEDS_H57_WAR_BASE_NAME PDB_PROP_CL_INTEL_CPU_ROOTPORT1_NEEDS_H57_WAR
407 #define PDB_PROP_CL_BUG_1340801_DISABLE_GEN3_ON_GIGABYTE_SNIPER_3_BASE_CAST
408 #define PDB_PROP_CL_BUG_1340801_DISABLE_GEN3_ON_GIGABYTE_SNIPER_3_BASE_NAME PDB_PROP_CL_BUG_1340801_DISABLE_GEN3_ON_GIGABYTE_SNIPER_3
409 #define PDB_PROP_CL_ASLM_SUPPORTS_HOT_RESET_BASE_CAST
410 #define PDB_PROP_CL_ASLM_SUPPORTS_HOT_RESET_BASE_NAME PDB_PROP_CL_ASLM_SUPPORTS_HOT_RESET
411 #define PDB_PROP_CL_IS_EXTERNAL_GPU_BASE_CAST
412 #define PDB_PROP_CL_IS_EXTERNAL_GPU_BASE_NAME PDB_PROP_CL_IS_EXTERNAL_GPU
413 #define PDB_PROP_CL_ROOTPORT_NEEDS_NOSNOOP_WAR_BASE_CAST
414 #define PDB_PROP_CL_ROOTPORT_NEEDS_NOSNOOP_WAR_BASE_NAME PDB_PROP_CL_ROOTPORT_NEEDS_NOSNOOP_WAR
415 #define PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED_BASE_CAST
416 #define PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED_BASE_NAME PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED
417 #define PDB_PROP_CL_FORCE_SNOOP_READS_AND_WRITES_WAR_BUG_410390_BASE_CAST
418 #define PDB_PROP_CL_FORCE_SNOOP_READS_AND_WRITES_WAR_BUG_410390_BASE_NAME PDB_PROP_CL_FORCE_SNOOP_READS_AND_WRITES_WAR_BUG_410390
419 #define PDB_PROP_CL_ASPM_L0S_CHIPSET_ENABLED_MOBILE_ONLY_BASE_CAST
420 #define PDB_PROP_CL_ASPM_L0S_CHIPSET_ENABLED_MOBILE_ONLY_BASE_NAME PDB_PROP_CL_ASPM_L0S_CHIPSET_ENABLED_MOBILE_ONLY
421 #define PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR_BASE_CAST
422 #define PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR_BASE_NAME PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR
423 #define PDB_PROP_CL_PCIE_NON_COHERENT_USE_TC0_ONLY_BASE_CAST
424 #define PDB_PROP_CL_PCIE_NON_COHERENT_USE_TC0_ONLY_BASE_NAME PDB_PROP_CL_PCIE_NON_COHERENT_USE_TC0_ONLY
425 #define PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE_BASE_CAST
426 #define PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE_BASE_NAME PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE
427 #define PDB_PROP_CL_IS_CHIPSET_IO_COHERENT_BASE_CAST
428 #define PDB_PROP_CL_IS_CHIPSET_IO_COHERENT_BASE_NAME PDB_PROP_CL_IS_CHIPSET_IO_COHERENT
429 #define PDB_PROP_CL_ASLM_SUPPORTS_FAST_LINK_UPGRADE_BASE_CAST
430 #define PDB_PROP_CL_ASLM_SUPPORTS_FAST_LINK_UPGRADE_BASE_NAME PDB_PROP_CL_ASLM_SUPPORTS_FAST_LINK_UPGRADE
431
432 NV_STATUS __nvoc_objCreateDynamic_OBJCL(OBJCL**, Dynamic*, NvU32, va_list);
433
434 NV_STATUS __nvoc_objCreate_OBJCL(OBJCL**, Dynamic*, NvU32);
435 #define __objCreate_OBJCL(ppNewObj, pParent, createFlags) \
436 __nvoc_objCreate_OBJCL((ppNewObj), staticCast((pParent), Dynamic), (createFlags))
437
438
439 // Wrapper macros
440
441 // Dispatch functions
442 NV_STATUS clInit_IMPL(struct OBJGPU *arg1, struct OBJCL *pCl);
443
444
445 #ifdef __nvoc_chipset_h_disabled
clInit(struct OBJGPU * arg1,struct OBJCL * pCl)446 static inline NV_STATUS clInit(struct OBJGPU *arg1, struct OBJCL *pCl) {
447 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
448 return NV_ERR_NOT_SUPPORTED;
449 }
450 #else //__nvoc_chipset_h_disabled
451 #define clInit(arg1, pCl) clInit_IMPL(arg1, pCl)
452 #endif //__nvoc_chipset_h_disabled
453
454 #define clInit_HAL(arg1, pCl) clInit(arg1, pCl)
455
456 void clUpdateConfig_IMPL(struct OBJGPU *arg1, struct OBJCL *pCl);
457
458
459 #ifdef __nvoc_chipset_h_disabled
clUpdateConfig(struct OBJGPU * arg1,struct OBJCL * pCl)460 static inline void clUpdateConfig(struct OBJGPU *arg1, struct OBJCL *pCl) {
461 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
462 }
463 #else //__nvoc_chipset_h_disabled
464 #define clUpdateConfig(arg1, pCl) clUpdateConfig_IMPL(arg1, pCl)
465 #endif //__nvoc_chipset_h_disabled
466
467 #define clUpdateConfig_HAL(arg1, pCl) clUpdateConfig(arg1, pCl)
468
469 NV_STATUS clTeardown_IMPL(struct OBJGPU *arg1, struct OBJCL *pCl);
470
471
472 #ifdef __nvoc_chipset_h_disabled
clTeardown(struct OBJGPU * arg1,struct OBJCL * pCl)473 static inline NV_STATUS clTeardown(struct OBJGPU *arg1, struct OBJCL *pCl) {
474 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
475 return NV_ERR_NOT_SUPPORTED;
476 }
477 #else //__nvoc_chipset_h_disabled
478 #define clTeardown(arg1, pCl) clTeardown_IMPL(arg1, pCl)
479 #endif //__nvoc_chipset_h_disabled
480
481 #define clTeardown_HAL(arg1, pCl) clTeardown(arg1, pCl)
482
483 void clInitPropertiesFromRegistry_IMPL(struct OBJGPU *arg1, struct OBJCL *pCl);
484
485
486 #ifdef __nvoc_chipset_h_disabled
clInitPropertiesFromRegistry(struct OBJGPU * arg1,struct OBJCL * pCl)487 static inline void clInitPropertiesFromRegistry(struct OBJGPU *arg1, struct OBJCL *pCl) {
488 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
489 }
490 #else //__nvoc_chipset_h_disabled
491 #define clInitPropertiesFromRegistry(arg1, pCl) clInitPropertiesFromRegistry_IMPL(arg1, pCl)
492 #endif //__nvoc_chipset_h_disabled
493
494 #define clInitPropertiesFromRegistry_HAL(arg1, pCl) clInitPropertiesFromRegistry(arg1, pCl)
495
496 NvU32 clInitMappingPciBusDevice_IMPL(struct OBJGPU *arg1, struct OBJCL *arg2);
497
498
499 #ifdef __nvoc_chipset_h_disabled
clInitMappingPciBusDevice(struct OBJGPU * arg1,struct OBJCL * arg2)500 static inline NvU32 clInitMappingPciBusDevice(struct OBJGPU *arg1, struct OBJCL *arg2) {
501 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
502 return 0;
503 }
504 #else //__nvoc_chipset_h_disabled
505 #define clInitMappingPciBusDevice(arg1, arg2) clInitMappingPciBusDevice_IMPL(arg1, arg2)
506 #endif //__nvoc_chipset_h_disabled
507
508 #define clInitMappingPciBusDevice_HAL(arg1, arg2) clInitMappingPciBusDevice(arg1, arg2)
509
510 NV_STATUS clFindFHBAndGetChipsetInfoIndex_IMPL(struct OBJCL *arg1, NvU16 *arg2);
511
512
513 #ifdef __nvoc_chipset_h_disabled
clFindFHBAndGetChipsetInfoIndex(struct OBJCL * arg1,NvU16 * arg2)514 static inline NV_STATUS clFindFHBAndGetChipsetInfoIndex(struct OBJCL *arg1, NvU16 *arg2) {
515 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
516 return NV_ERR_NOT_SUPPORTED;
517 }
518 #else //__nvoc_chipset_h_disabled
519 #define clFindFHBAndGetChipsetInfoIndex(arg1, arg2) clFindFHBAndGetChipsetInfoIndex_IMPL(arg1, arg2)
520 #endif //__nvoc_chipset_h_disabled
521
522 #define clFindFHBAndGetChipsetInfoIndex_HAL(arg1, arg2) clFindFHBAndGetChipsetInfoIndex(arg1, arg2)
523
524 NV_STATUS clInitPcie_IMPL(struct OBJGPU *arg1, struct OBJCL *arg2);
525
526
527 #ifdef __nvoc_chipset_h_disabled
clInitPcie(struct OBJGPU * arg1,struct OBJCL * arg2)528 static inline NV_STATUS clInitPcie(struct OBJGPU *arg1, struct OBJCL *arg2) {
529 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
530 return NV_ERR_NOT_SUPPORTED;
531 }
532 #else //__nvoc_chipset_h_disabled
533 #define clInitPcie(arg1, arg2) clInitPcie_IMPL(arg1, arg2)
534 #endif //__nvoc_chipset_h_disabled
535
536 #define clInitPcie_HAL(arg1, arg2) clInitPcie(arg1, arg2)
537
538 void clUpdatePcieConfig_IMPL(struct OBJGPU *arg1, struct OBJCL *arg2);
539
540
541 #ifdef __nvoc_chipset_h_disabled
clUpdatePcieConfig(struct OBJGPU * arg1,struct OBJCL * arg2)542 static inline void clUpdatePcieConfig(struct OBJGPU *arg1, struct OBJCL *arg2) {
543 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
544 }
545 #else //__nvoc_chipset_h_disabled
546 #define clUpdatePcieConfig(arg1, arg2) clUpdatePcieConfig_IMPL(arg1, arg2)
547 #endif //__nvoc_chipset_h_disabled
548
549 #define clUpdatePcieConfig_HAL(arg1, arg2) clUpdatePcieConfig(arg1, arg2)
550
551 NV_STATUS clTeardownPcie_IMPL(struct OBJGPU *arg1, struct OBJCL *arg2);
552
553
554 #ifdef __nvoc_chipset_h_disabled
clTeardownPcie(struct OBJGPU * arg1,struct OBJCL * arg2)555 static inline NV_STATUS clTeardownPcie(struct OBJGPU *arg1, struct OBJCL *arg2) {
556 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
557 return NV_ERR_NOT_SUPPORTED;
558 }
559 #else //__nvoc_chipset_h_disabled
560 #define clTeardownPcie(arg1, arg2) clTeardownPcie_IMPL(arg1, arg2)
561 #endif //__nvoc_chipset_h_disabled
562
563 #define clTeardownPcie_HAL(arg1, arg2) clTeardownPcie(arg1, arg2)
564
565 NV_STATUS clPcieReadPortConfigReg_IMPL(struct OBJGPU *arg1, struct OBJCL *arg2, PORTDATA *arg3, NvU32 arg4, NvU32 *arg5);
566
567
568 #ifdef __nvoc_chipset_h_disabled
clPcieReadPortConfigReg(struct OBJGPU * arg1,struct OBJCL * arg2,PORTDATA * arg3,NvU32 arg4,NvU32 * arg5)569 static inline NV_STATUS clPcieReadPortConfigReg(struct OBJGPU *arg1, struct OBJCL *arg2, PORTDATA *arg3, NvU32 arg4, NvU32 *arg5) {
570 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
571 return NV_ERR_NOT_SUPPORTED;
572 }
573 #else //__nvoc_chipset_h_disabled
574 #define clPcieReadPortConfigReg(arg1, arg2, arg3, arg4, arg5) clPcieReadPortConfigReg_IMPL(arg1, arg2, arg3, arg4, arg5)
575 #endif //__nvoc_chipset_h_disabled
576
577 #define clPcieReadPortConfigReg_HAL(arg1, arg2, arg3, arg4, arg5) clPcieReadPortConfigReg(arg1, arg2, arg3, arg4, arg5)
578
579 NV_STATUS clPcieWriteRootPortConfigReg_IMPL(struct OBJGPU *arg1, struct OBJCL *arg2, NvU32 arg3, NvU32 arg4);
580
581
582 #ifdef __nvoc_chipset_h_disabled
clPcieWriteRootPortConfigReg(struct OBJGPU * arg1,struct OBJCL * arg2,NvU32 arg3,NvU32 arg4)583 static inline NV_STATUS clPcieWriteRootPortConfigReg(struct OBJGPU *arg1, struct OBJCL *arg2, NvU32 arg3, NvU32 arg4) {
584 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
585 return NV_ERR_NOT_SUPPORTED;
586 }
587 #else //__nvoc_chipset_h_disabled
588 #define clPcieWriteRootPortConfigReg(arg1, arg2, arg3, arg4) clPcieWriteRootPortConfigReg_IMPL(arg1, arg2, arg3, arg4)
589 #endif //__nvoc_chipset_h_disabled
590
591 #define clPcieWriteRootPortConfigReg_HAL(arg1, arg2, arg3, arg4) clPcieWriteRootPortConfigReg(arg1, arg2, arg3, arg4)
592
593 NV_STATUS clPcieReadAerCapability_IMPL(struct OBJGPU *arg1, struct OBJCL *arg2, struct PcieAerCapability *arg3);
594
595
596 #ifdef __nvoc_chipset_h_disabled
clPcieReadAerCapability(struct OBJGPU * arg1,struct OBJCL * arg2,struct PcieAerCapability * arg3)597 static inline NV_STATUS clPcieReadAerCapability(struct OBJGPU *arg1, struct OBJCL *arg2, struct PcieAerCapability *arg3) {
598 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
599 return NV_ERR_NOT_SUPPORTED;
600 }
601 #else //__nvoc_chipset_h_disabled
602 #define clPcieReadAerCapability(arg1, arg2, arg3) clPcieReadAerCapability_IMPL(arg1, arg2, arg3)
603 #endif //__nvoc_chipset_h_disabled
604
605 #define clPcieReadAerCapability_HAL(arg1, arg2, arg3) clPcieReadAerCapability(arg1, arg2, arg3)
606
607 NV_STATUS clPcieReadL1SsCapability_IMPL(struct OBJGPU *arg1, struct OBJCL *arg2, struct PexL1SubstateCapability *arg3);
608
609
610 #ifdef __nvoc_chipset_h_disabled
clPcieReadL1SsCapability(struct OBJGPU * arg1,struct OBJCL * arg2,struct PexL1SubstateCapability * arg3)611 static inline NV_STATUS clPcieReadL1SsCapability(struct OBJGPU *arg1, struct OBJCL *arg2, struct PexL1SubstateCapability *arg3) {
612 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
613 return NV_ERR_NOT_SUPPORTED;
614 }
615 #else //__nvoc_chipset_h_disabled
616 #define clPcieReadL1SsCapability(arg1, arg2, arg3) clPcieReadL1SsCapability_IMPL(arg1, arg2, arg3)
617 #endif //__nvoc_chipset_h_disabled
618
619 #define clPcieReadL1SsCapability_HAL(arg1, arg2, arg3) clPcieReadL1SsCapability(arg1, arg2, arg3)
620
621 NV_STATUS clPcieReadDevCtrlStatus_IMPL(struct OBJGPU *arg1, struct OBJCL *arg2, NvU32 *arg3, NvU32 *arg4);
622
623
624 #ifdef __nvoc_chipset_h_disabled
clPcieReadDevCtrlStatus(struct OBJGPU * arg1,struct OBJCL * arg2,NvU32 * arg3,NvU32 * arg4)625 static inline NV_STATUS clPcieReadDevCtrlStatus(struct OBJGPU *arg1, struct OBJCL *arg2, NvU32 *arg3, NvU32 *arg4) {
626 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
627 return NV_ERR_NOT_SUPPORTED;
628 }
629 #else //__nvoc_chipset_h_disabled
630 #define clPcieReadDevCtrlStatus(arg1, arg2, arg3, arg4) clPcieReadDevCtrlStatus_IMPL(arg1, arg2, arg3, arg4)
631 #endif //__nvoc_chipset_h_disabled
632
633 #define clPcieReadDevCtrlStatus_HAL(arg1, arg2, arg3, arg4) clPcieReadDevCtrlStatus(arg1, arg2, arg3, arg4)
634
635 NV_STATUS clPcieClearDevCtrlStatus_IMPL(struct OBJGPU *arg1, struct OBJCL *arg2, NvU32 *arg3);
636
637
638 #ifdef __nvoc_chipset_h_disabled
clPcieClearDevCtrlStatus(struct OBJGPU * arg1,struct OBJCL * arg2,NvU32 * arg3)639 static inline NV_STATUS clPcieClearDevCtrlStatus(struct OBJGPU *arg1, struct OBJCL *arg2, NvU32 *arg3) {
640 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
641 return NV_ERR_NOT_SUPPORTED;
642 }
643 #else //__nvoc_chipset_h_disabled
644 #define clPcieClearDevCtrlStatus(arg1, arg2, arg3) clPcieClearDevCtrlStatus_IMPL(arg1, arg2, arg3)
645 #endif //__nvoc_chipset_h_disabled
646
647 #define clPcieClearDevCtrlStatus_HAL(arg1, arg2, arg3) clPcieClearDevCtrlStatus(arg1, arg2, arg3)
648
649 NvU16 clPcieReadWord_IMPL(struct OBJCL *arg1, NvU32 arg2, NvU8 arg3, NvU8 arg4, NvU8 arg5, NvU32 arg6);
650
651
652 #ifdef __nvoc_chipset_h_disabled
clPcieReadWord(struct OBJCL * arg1,NvU32 arg2,NvU8 arg3,NvU8 arg4,NvU8 arg5,NvU32 arg6)653 static inline NvU16 clPcieReadWord(struct OBJCL *arg1, NvU32 arg2, NvU8 arg3, NvU8 arg4, NvU8 arg5, NvU32 arg6) {
654 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
655 return 0;
656 }
657 #else //__nvoc_chipset_h_disabled
658 #define clPcieReadWord(arg1, arg2, arg3, arg4, arg5, arg6) clPcieReadWord_IMPL(arg1, arg2, arg3, arg4, arg5, arg6)
659 #endif //__nvoc_chipset_h_disabled
660
661 #define clPcieReadWord_HAL(arg1, arg2, arg3, arg4, arg5, arg6) clPcieReadWord(arg1, arg2, arg3, arg4, arg5, arg6)
662
663 NvU32 clPcieReadDword_IMPL(struct OBJCL *arg1, NvU32 arg2, NvU8 arg3, NvU8 arg4, NvU8 arg5, NvU32 arg6);
664
665
666 #ifdef __nvoc_chipset_h_disabled
clPcieReadDword(struct OBJCL * arg1,NvU32 arg2,NvU8 arg3,NvU8 arg4,NvU8 arg5,NvU32 arg6)667 static inline NvU32 clPcieReadDword(struct OBJCL *arg1, NvU32 arg2, NvU8 arg3, NvU8 arg4, NvU8 arg5, NvU32 arg6) {
668 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
669 return 0;
670 }
671 #else //__nvoc_chipset_h_disabled
672 #define clPcieReadDword(arg1, arg2, arg3, arg4, arg5, arg6) clPcieReadDword_IMPL(arg1, arg2, arg3, arg4, arg5, arg6)
673 #endif //__nvoc_chipset_h_disabled
674
675 #define clPcieReadDword_HAL(arg1, arg2, arg3, arg4, arg5, arg6) clPcieReadDword(arg1, arg2, arg3, arg4, arg5, arg6)
676
677 void clPcieWriteWord_IMPL(struct OBJCL *arg1, NvU32 arg2, NvU8 arg3, NvU8 arg4, NvU8 arg5, NvU32 arg6, NvU16 arg7);
678
679
680 #ifdef __nvoc_chipset_h_disabled
clPcieWriteWord(struct OBJCL * arg1,NvU32 arg2,NvU8 arg3,NvU8 arg4,NvU8 arg5,NvU32 arg6,NvU16 arg7)681 static inline void clPcieWriteWord(struct OBJCL *arg1, NvU32 arg2, NvU8 arg3, NvU8 arg4, NvU8 arg5, NvU32 arg6, NvU16 arg7) {
682 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
683 }
684 #else //__nvoc_chipset_h_disabled
685 #define clPcieWriteWord(arg1, arg2, arg3, arg4, arg5, arg6, arg7) clPcieWriteWord_IMPL(arg1, arg2, arg3, arg4, arg5, arg6, arg7)
686 #endif //__nvoc_chipset_h_disabled
687
688 #define clPcieWriteWord_HAL(arg1, arg2, arg3, arg4, arg5, arg6, arg7) clPcieWriteWord(arg1, arg2, arg3, arg4, arg5, arg6, arg7)
689
690 void clPcieWriteDword_IMPL(struct OBJCL *arg1, NvU32 arg2, NvU8 arg3, NvU8 arg4, NvU8 arg5, NvU32 arg6, NvU32 arg7);
691
692
693 #ifdef __nvoc_chipset_h_disabled
clPcieWriteDword(struct OBJCL * arg1,NvU32 arg2,NvU8 arg3,NvU8 arg4,NvU8 arg5,NvU32 arg6,NvU32 arg7)694 static inline void clPcieWriteDword(struct OBJCL *arg1, NvU32 arg2, NvU8 arg3, NvU8 arg4, NvU8 arg5, NvU32 arg6, NvU32 arg7) {
695 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
696 }
697 #else //__nvoc_chipset_h_disabled
698 #define clPcieWriteDword(arg1, arg2, arg3, arg4, arg5, arg6, arg7) clPcieWriteDword_IMPL(arg1, arg2, arg3, arg4, arg5, arg6, arg7)
699 #endif //__nvoc_chipset_h_disabled
700
701 #define clPcieWriteDword_HAL(arg1, arg2, arg3, arg4, arg5, arg6, arg7) clPcieWriteDword(arg1, arg2, arg3, arg4, arg5, arg6, arg7)
702
703 NvBool clFindBR04_IMPL(POBJGPU *pGpus, NvU32 NumGpus, NvBool flat, NvU32 devId, struct OBJCL *pCl);
704
705
706 #ifdef __nvoc_chipset_h_disabled
clFindBR04(POBJGPU * pGpus,NvU32 NumGpus,NvBool flat,NvU32 devId,struct OBJCL * pCl)707 static inline NvBool clFindBR04(POBJGPU *pGpus, NvU32 NumGpus, NvBool flat, NvU32 devId, struct OBJCL *pCl) {
708 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
709 return NV_FALSE;
710 }
711 #else //__nvoc_chipset_h_disabled
712 #define clFindBR04(pGpus, NumGpus, flat, devId, pCl) clFindBR04_IMPL(pGpus, NumGpus, flat, devId, pCl)
713 #endif //__nvoc_chipset_h_disabled
714
715 #define clFindBR04_HAL(pGpus, NumGpus, flat, devId, pCl) clFindBR04(pGpus, NumGpus, flat, devId, pCl)
716
717 NV_STATUS clResumeBridge_IMPL(struct OBJCL *pCl);
718
719
720 #ifdef __nvoc_chipset_h_disabled
clResumeBridge(struct OBJCL * pCl)721 static inline NV_STATUS clResumeBridge(struct OBJCL *pCl) {
722 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
723 return NV_ERR_NOT_SUPPORTED;
724 }
725 #else //__nvoc_chipset_h_disabled
726 #define clResumeBridge(pCl) clResumeBridge_IMPL(pCl)
727 #endif //__nvoc_chipset_h_disabled
728
729 #define clResumeBridge_HAL(pCl) clResumeBridge(pCl)
730
731 void *clFindP2PBrdg_IMPL(struct OBJCL *arg1, NvU32 arg2, NvU8 arg3, NvU8 *arg4, NvU8 *arg5, NvU8 *arg6, NvU16 *arg7, NvU16 *arg8);
732
733
734 #ifdef __nvoc_chipset_h_disabled
clFindP2PBrdg(struct OBJCL * arg1,NvU32 arg2,NvU8 arg3,NvU8 * arg4,NvU8 * arg5,NvU8 * arg6,NvU16 * arg7,NvU16 * arg8)735 static inline void *clFindP2PBrdg(struct OBJCL *arg1, NvU32 arg2, NvU8 arg3, NvU8 *arg4, NvU8 *arg5, NvU8 *arg6, NvU16 *arg7, NvU16 *arg8) {
736 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
737 return NULL;
738 }
739 #else //__nvoc_chipset_h_disabled
740 #define clFindP2PBrdg(arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) clFindP2PBrdg_IMPL(arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8)
741 #endif //__nvoc_chipset_h_disabled
742
743 #define clFindP2PBrdg_HAL(arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) clFindP2PBrdg(arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8)
744
745 void *clFindBrdgUpstreamPort_IMPL(struct OBJGPU *arg1, struct OBJCL *arg2, NvBool arg3, NvU8 *arg4, NvU8 *arg5, NvU8 *arg6, NvU16 *arg7, NvU16 *arg8, NvU8 *arg9);
746
747
748 #ifdef __nvoc_chipset_h_disabled
clFindBrdgUpstreamPort(struct OBJGPU * arg1,struct OBJCL * arg2,NvBool arg3,NvU8 * arg4,NvU8 * arg5,NvU8 * arg6,NvU16 * arg7,NvU16 * arg8,NvU8 * arg9)749 static inline void *clFindBrdgUpstreamPort(struct OBJGPU *arg1, struct OBJCL *arg2, NvBool arg3, NvU8 *arg4, NvU8 *arg5, NvU8 *arg6, NvU16 *arg7, NvU16 *arg8, NvU8 *arg9) {
750 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
751 return NULL;
752 }
753 #else //__nvoc_chipset_h_disabled
754 #define clFindBrdgUpstreamPort(arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9) clFindBrdgUpstreamPort_IMPL(arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9)
755 #endif //__nvoc_chipset_h_disabled
756
757 #define clFindBrdgUpstreamPort_HAL(arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9) clFindBrdgUpstreamPort(arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9)
758
759 NV_STATUS clSetPortPcieCapOffset_IMPL(struct OBJCL *arg1, void *arg2, NvU32 *arg3);
760
761
762 #ifdef __nvoc_chipset_h_disabled
clSetPortPcieCapOffset(struct OBJCL * arg1,void * arg2,NvU32 * arg3)763 static inline NV_STATUS clSetPortPcieCapOffset(struct OBJCL *arg1, void *arg2, NvU32 *arg3) {
764 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
765 return NV_ERR_NOT_SUPPORTED;
766 }
767 #else //__nvoc_chipset_h_disabled
768 #define clSetPortPcieCapOffset(arg1, arg2, arg3) clSetPortPcieCapOffset_IMPL(arg1, arg2, arg3)
769 #endif //__nvoc_chipset_h_disabled
770
771 #define clSetPortPcieCapOffset_HAL(arg1, arg2, arg3) clSetPortPcieCapOffset(arg1, arg2, arg3)
772
773 NV_STATUS clStorePcieConfigSpaceBaseFromMcfg_IMPL(struct OBJCL *pCl);
774
775
776 #ifdef __nvoc_chipset_h_disabled
clStorePcieConfigSpaceBaseFromMcfg(struct OBJCL * pCl)777 static inline NV_STATUS clStorePcieConfigSpaceBaseFromMcfg(struct OBJCL *pCl) {
778 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
779 return NV_ERR_NOT_SUPPORTED;
780 }
781 #else //__nvoc_chipset_h_disabled
782 #define clStorePcieConfigSpaceBaseFromMcfg(pCl) clStorePcieConfigSpaceBaseFromMcfg_IMPL(pCl)
783 #endif //__nvoc_chipset_h_disabled
784
785 #define clStorePcieConfigSpaceBaseFromMcfg_HAL(pCl) clStorePcieConfigSpaceBaseFromMcfg(pCl)
786
787 NV_STATUS clInsertPcieConfigSpaceBase_IMPL(struct OBJCL *arg1, RmPhysAddr arg2, NvU32 arg3, NvU8 arg4, NvU8 arg5);
788
789
790 #ifdef __nvoc_chipset_h_disabled
clInsertPcieConfigSpaceBase(struct OBJCL * arg1,RmPhysAddr arg2,NvU32 arg3,NvU8 arg4,NvU8 arg5)791 static inline NV_STATUS clInsertPcieConfigSpaceBase(struct OBJCL *arg1, RmPhysAddr arg2, NvU32 arg3, NvU8 arg4, NvU8 arg5) {
792 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
793 return NV_ERR_NOT_SUPPORTED;
794 }
795 #else //__nvoc_chipset_h_disabled
796 #define clInsertPcieConfigSpaceBase(arg1, arg2, arg3, arg4, arg5) clInsertPcieConfigSpaceBase_IMPL(arg1, arg2, arg3, arg4, arg5)
797 #endif //__nvoc_chipset_h_disabled
798
799 #define clInsertPcieConfigSpaceBase_HAL(arg1, arg2, arg3, arg4, arg5) clInsertPcieConfigSpaceBase(arg1, arg2, arg3, arg4, arg5)
800
801 RmPhysAddr clFindPcieConfigSpaceBase_IMPL(struct OBJCL *arg1, NvU32 arg2, NvU8 arg3);
802
803
804 #ifdef __nvoc_chipset_h_disabled
clFindPcieConfigSpaceBase(struct OBJCL * arg1,NvU32 arg2,NvU8 arg3)805 static inline RmPhysAddr clFindPcieConfigSpaceBase(struct OBJCL *arg1, NvU32 arg2, NvU8 arg3) {
806 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
807 RmPhysAddr ret;
808 portMemSet(&ret, 0, sizeof(RmPhysAddr));
809 return ret;
810 }
811 #else //__nvoc_chipset_h_disabled
812 #define clFindPcieConfigSpaceBase(arg1, arg2, arg3) clFindPcieConfigSpaceBase_IMPL(arg1, arg2, arg3)
813 #endif //__nvoc_chipset_h_disabled
814
815 #define clFindPcieConfigSpaceBase_HAL(arg1, arg2, arg3) clFindPcieConfigSpaceBase(arg1, arg2, arg3)
816
817 void clFreePcieConfigSpaceBase_IMPL(struct OBJCL *pCl);
818
819
820 #ifdef __nvoc_chipset_h_disabled
clFreePcieConfigSpaceBase(struct OBJCL * pCl)821 static inline void clFreePcieConfigSpaceBase(struct OBJCL *pCl) {
822 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
823 }
824 #else //__nvoc_chipset_h_disabled
825 #define clFreePcieConfigSpaceBase(pCl) clFreePcieConfigSpaceBase_IMPL(pCl)
826 #endif //__nvoc_chipset_h_disabled
827
828 #define clFreePcieConfigSpaceBase_HAL(pCl) clFreePcieConfigSpaceBase(pCl)
829
830 NV_STATUS clInitDeviceInfo_IMPL(struct OBJCL *arg1, struct OBJGPU *arg2);
831
832
833 #ifdef __nvoc_chipset_h_disabled
clInitDeviceInfo(struct OBJCL * arg1,struct OBJGPU * arg2)834 static inline NV_STATUS clInitDeviceInfo(struct OBJCL *arg1, struct OBJGPU *arg2) {
835 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
836 return NV_ERR_NOT_SUPPORTED;
837 }
838 #else //__nvoc_chipset_h_disabled
839 #define clInitDeviceInfo(arg1, arg2) clInitDeviceInfo_IMPL(arg1, arg2)
840 #endif //__nvoc_chipset_h_disabled
841
842 #define clInitDeviceInfo_HAL(arg1, arg2) clInitDeviceInfo(arg1, arg2)
843
844 void clCountBR_IMPL(struct OBJGPU *arg1, struct OBJCL *arg2, NvU8 *arg3);
845
846
847 #ifdef __nvoc_chipset_h_disabled
clCountBR(struct OBJGPU * arg1,struct OBJCL * arg2,NvU8 * arg3)848 static inline void clCountBR(struct OBJGPU *arg1, struct OBJCL *arg2, NvU8 *arg3) {
849 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
850 }
851 #else //__nvoc_chipset_h_disabled
852 #define clCountBR(arg1, arg2, arg3) clCountBR_IMPL(arg1, arg2, arg3)
853 #endif //__nvoc_chipset_h_disabled
854
855 #define clCountBR_HAL(arg1, arg2, arg3) clCountBR(arg1, arg2, arg3)
856
857 void clFindCommonBR_IMPL(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, struct OBJCL *pCl, NvU8 *pBR04Bus, NvBool bScanAll);
858
859
860 #ifdef __nvoc_chipset_h_disabled
clFindCommonBR(struct OBJGPU * pGpu1,struct OBJGPU * pGpu2,struct OBJCL * pCl,NvU8 * pBR04Bus,NvBool bScanAll)861 static inline void clFindCommonBR(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, struct OBJCL *pCl, NvU8 *pBR04Bus, NvBool bScanAll) {
862 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
863 }
864 #else //__nvoc_chipset_h_disabled
865 #define clFindCommonBR(pGpu1, pGpu2, pCl, pBR04Bus, bScanAll) clFindCommonBR_IMPL(pGpu1, pGpu2, pCl, pBR04Bus, bScanAll)
866 #endif //__nvoc_chipset_h_disabled
867
868 #define clFindCommonBR_HAL(pGpu1, pGpu2, pCl, pBR04Bus, bScanAll) clFindCommonBR(pGpu1, pGpu2, pCl, pBR04Bus, bScanAll)
869
870 void clFindCommonDownstreamBR_IMPL(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, struct OBJCL *pCl, NvU8 *pPciSwitchBus);
871
872
873 #ifdef __nvoc_chipset_h_disabled
clFindCommonDownstreamBR(struct OBJGPU * pGpu1,struct OBJGPU * pGpu2,struct OBJCL * pCl,NvU8 * pPciSwitchBus)874 static inline void clFindCommonDownstreamBR(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, struct OBJCL *pCl, NvU8 *pPciSwitchBus) {
875 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
876 }
877 #else //__nvoc_chipset_h_disabled
878 #define clFindCommonDownstreamBR(pGpu1, pGpu2, pCl, pPciSwitchBus) clFindCommonDownstreamBR_IMPL(pGpu1, pGpu2, pCl, pPciSwitchBus)
879 #endif //__nvoc_chipset_h_disabled
880
881 #define clFindCommonDownstreamBR_HAL(pGpu1, pGpu2, pCl, pPciSwitchBus) clFindCommonDownstreamBR(pGpu1, pGpu2, pCl, pPciSwitchBus)
882
883 void clFindBR_IMPL(struct OBJGPU *pGpu, struct OBJCL *pCl, NvU8 *pBR03Bus, NvU8 *pBR04Bus, NvBool *pBRNotBR04A03, NvBool *pNoUnsupportedBRFound, NvBool *pNoOnboardBR04);
884
885
886 #ifdef __nvoc_chipset_h_disabled
clFindBR(struct OBJGPU * pGpu,struct OBJCL * pCl,NvU8 * pBR03Bus,NvU8 * pBR04Bus,NvBool * pBRNotBR04A03,NvBool * pNoUnsupportedBRFound,NvBool * pNoOnboardBR04)887 static inline void clFindBR(struct OBJGPU *pGpu, struct OBJCL *pCl, NvU8 *pBR03Bus, NvU8 *pBR04Bus, NvBool *pBRNotBR04A03, NvBool *pNoUnsupportedBRFound, NvBool *pNoOnboardBR04) {
888 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
889 }
890 #else //__nvoc_chipset_h_disabled
891 #define clFindBR(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04) clFindBR_IMPL(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04)
892 #endif //__nvoc_chipset_h_disabled
893
894 #define clFindBR_HAL(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04) clFindBR(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04)
895
896 void clSearchBR04_IMPL(struct OBJCL *pCl, NvU8 *pBR04BusArray, NvU8 *pBR04RevArray, NvU8 *pBR04Count);
897
898
899 #ifdef __nvoc_chipset_h_disabled
clSearchBR04(struct OBJCL * pCl,NvU8 * pBR04BusArray,NvU8 * pBR04RevArray,NvU8 * pBR04Count)900 static inline void clSearchBR04(struct OBJCL *pCl, NvU8 *pBR04BusArray, NvU8 *pBR04RevArray, NvU8 *pBR04Count) {
901 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
902 }
903 #else //__nvoc_chipset_h_disabled
904 #define clSearchBR04(pCl, pBR04BusArray, pBR04RevArray, pBR04Count) clSearchBR04_IMPL(pCl, pBR04BusArray, pBR04RevArray, pBR04Count)
905 #endif //__nvoc_chipset_h_disabled
906
907 #define clSearchBR04_HAL(pCl, pBR04BusArray, pBR04RevArray, pBR04Count) clSearchBR04(pCl, pBR04BusArray, pBR04RevArray, pBR04Count)
908
909 NV_STATUS clPcieGetMaxCapableLinkWidth_IMPL(struct OBJCL *pCl, struct OBJGPU *pGpu, NvU32 *maxCapableLinkWidth);
910
911
912 #ifdef __nvoc_chipset_h_disabled
clPcieGetMaxCapableLinkWidth(struct OBJCL * pCl,struct OBJGPU * pGpu,NvU32 * maxCapableLinkWidth)913 static inline NV_STATUS clPcieGetMaxCapableLinkWidth(struct OBJCL *pCl, struct OBJGPU *pGpu, NvU32 *maxCapableLinkWidth) {
914 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
915 return NV_ERR_NOT_SUPPORTED;
916 }
917 #else //__nvoc_chipset_h_disabled
918 #define clPcieGetMaxCapableLinkWidth(pCl, pGpu, maxCapableLinkWidth) clPcieGetMaxCapableLinkWidth_IMPL(pCl, pGpu, maxCapableLinkWidth)
919 #endif //__nvoc_chipset_h_disabled
920
921 #define clPcieGetMaxCapableLinkWidth_HAL(pCl, pGpu, maxCapableLinkWidth) clPcieGetMaxCapableLinkWidth(pCl, pGpu, maxCapableLinkWidth)
922
923 NV_STATUS clPcieIsRelaxedOrderingSafe_IMPL(struct OBJCL *pCl, struct OBJGPU *pGpu, NvBool *result);
924
925
926 #ifdef __nvoc_chipset_h_disabled
clPcieIsRelaxedOrderingSafe(struct OBJCL * pCl,struct OBJGPU * pGpu,NvBool * result)927 static inline NV_STATUS clPcieIsRelaxedOrderingSafe(struct OBJCL *pCl, struct OBJGPU *pGpu, NvBool *result) {
928 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
929 return NV_ERR_NOT_SUPPORTED;
930 }
931 #else //__nvoc_chipset_h_disabled
932 #define clPcieIsRelaxedOrderingSafe(pCl, pGpu, result) clPcieIsRelaxedOrderingSafe_IMPL(pCl, pGpu, result)
933 #endif //__nvoc_chipset_h_disabled
934
935 #define clPcieIsRelaxedOrderingSafe_HAL(pCl, pGpu, result) clPcieIsRelaxedOrderingSafe(pCl, pGpu, result)
936
937 NV_STATUS clStoreBusTopologyCache_IMPL(struct OBJCL *pCl, NvU32 secDomain, NvU16 secBus);
938
939
940 #ifdef __nvoc_chipset_h_disabled
clStoreBusTopologyCache(struct OBJCL * pCl,NvU32 secDomain,NvU16 secBus)941 static inline NV_STATUS clStoreBusTopologyCache(struct OBJCL *pCl, NvU32 secDomain, NvU16 secBus) {
942 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
943 return NV_ERR_NOT_SUPPORTED;
944 }
945 #else //__nvoc_chipset_h_disabled
946 #define clStoreBusTopologyCache(pCl, secDomain, secBus) clStoreBusTopologyCache_IMPL(pCl, secDomain, secBus)
947 #endif //__nvoc_chipset_h_disabled
948
949 #define clStoreBusTopologyCache_HAL(pCl, secDomain, secBus) clStoreBusTopologyCache(pCl, secDomain, secBus)
950
951 void clFreeBusTopologyCache_IMPL(struct OBJCL *pCl);
952
953
954 #ifdef __nvoc_chipset_h_disabled
clFreeBusTopologyCache(struct OBJCL * pCl)955 static inline void clFreeBusTopologyCache(struct OBJCL *pCl) {
956 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
957 }
958 #else //__nvoc_chipset_h_disabled
959 #define clFreeBusTopologyCache(pCl) clFreeBusTopologyCache_IMPL(pCl)
960 #endif //__nvoc_chipset_h_disabled
961
962 #define clFreeBusTopologyCache_HAL(pCl) clFreeBusTopologyCache(pCl)
963
964 NvBool clIsL1MaskEnabledForUpstreamPort_IMPL(struct OBJGPU *arg1, struct OBJCL *arg2);
965
966
967 #ifdef __nvoc_chipset_h_disabled
clIsL1MaskEnabledForUpstreamPort(struct OBJGPU * arg1,struct OBJCL * arg2)968 static inline NvBool clIsL1MaskEnabledForUpstreamPort(struct OBJGPU *arg1, struct OBJCL *arg2) {
969 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
970 return NV_FALSE;
971 }
972 #else //__nvoc_chipset_h_disabled
973 #define clIsL1MaskEnabledForUpstreamPort(arg1, arg2) clIsL1MaskEnabledForUpstreamPort_IMPL(arg1, arg2)
974 #endif //__nvoc_chipset_h_disabled
975
976 #define clIsL1MaskEnabledForUpstreamPort_HAL(arg1, arg2) clIsL1MaskEnabledForUpstreamPort(arg1, arg2)
977
978 NvBool clIsL0sMaskEnabledForUpstreamPort_IMPL(struct OBJGPU *arg1, struct OBJCL *arg2);
979
980
981 #ifdef __nvoc_chipset_h_disabled
clIsL0sMaskEnabledForUpstreamPort(struct OBJGPU * arg1,struct OBJCL * arg2)982 static inline NvBool clIsL0sMaskEnabledForUpstreamPort(struct OBJGPU *arg1, struct OBJCL *arg2) {
983 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
984 return NV_FALSE;
985 }
986 #else //__nvoc_chipset_h_disabled
987 #define clIsL0sMaskEnabledForUpstreamPort(arg1, arg2) clIsL0sMaskEnabledForUpstreamPort_IMPL(arg1, arg2)
988 #endif //__nvoc_chipset_h_disabled
989
990 #define clIsL0sMaskEnabledForUpstreamPort_HAL(arg1, arg2) clIsL0sMaskEnabledForUpstreamPort(arg1, arg2)
991
992 NV_STATUS clControlL0sL1LinkControlUpstreamPort_IMPL(struct OBJGPU *arg1, struct OBJCL *arg2, NvBool arg3);
993
994
995 #ifdef __nvoc_chipset_h_disabled
clControlL0sL1LinkControlUpstreamPort(struct OBJGPU * arg1,struct OBJCL * arg2,NvBool arg3)996 static inline NV_STATUS clControlL0sL1LinkControlUpstreamPort(struct OBJGPU *arg1, struct OBJCL *arg2, NvBool arg3) {
997 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
998 return NV_ERR_NOT_SUPPORTED;
999 }
1000 #else //__nvoc_chipset_h_disabled
1001 #define clControlL0sL1LinkControlUpstreamPort(arg1, arg2, arg3) clControlL0sL1LinkControlUpstreamPort_IMPL(arg1, arg2, arg3)
1002 #endif //__nvoc_chipset_h_disabled
1003
1004 #define clControlL0sL1LinkControlUpstreamPort_HAL(arg1, arg2, arg3) clControlL0sL1LinkControlUpstreamPort(arg1, arg2, arg3)
1005
1006 NV_STATUS clChipsetAspmPublicControl_IMPL(struct OBJGPU *arg1, struct OBJCL *arg2, NvU32 arg3);
1007
1008
1009 #ifdef __nvoc_chipset_h_disabled
clChipsetAspmPublicControl(struct OBJGPU * arg1,struct OBJCL * arg2,NvU32 arg3)1010 static inline NV_STATUS clChipsetAspmPublicControl(struct OBJGPU *arg1, struct OBJCL *arg2, NvU32 arg3) {
1011 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
1012 return NV_ERR_NOT_SUPPORTED;
1013 }
1014 #else //__nvoc_chipset_h_disabled
1015 #define clChipsetAspmPublicControl(arg1, arg2, arg3) clChipsetAspmPublicControl_IMPL(arg1, arg2, arg3)
1016 #endif //__nvoc_chipset_h_disabled
1017
1018 #define clChipsetAspmPublicControl_HAL(arg1, arg2, arg3) clChipsetAspmPublicControl(arg1, arg2, arg3)
1019
1020 NvBool clRootportNeedsNosnoopWAR_FWCLIENT(struct OBJGPU *arg1, struct OBJCL *arg2);
1021
1022
1023 #ifdef __nvoc_chipset_h_disabled
clRootportNeedsNosnoopWAR(struct OBJGPU * arg1,struct OBJCL * arg2)1024 static inline NvBool clRootportNeedsNosnoopWAR(struct OBJGPU *arg1, struct OBJCL *arg2) {
1025 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
1026 return NV_FALSE;
1027 }
1028 #else //__nvoc_chipset_h_disabled
1029 #define clRootportNeedsNosnoopWAR(arg1, arg2) clRootportNeedsNosnoopWAR_FWCLIENT(arg1, arg2)
1030 #endif //__nvoc_chipset_h_disabled
1031
1032 #define clRootportNeedsNosnoopWAR_HAL(arg1, arg2) clRootportNeedsNosnoopWAR(arg1, arg2)
1033
1034 NvU16 clPcieGetGpuLostDiagnosticData_IMPL(struct OBJGPU *pGpu, struct OBJCL *arg2, NvU8 *pBuffer, NvU32 size);
1035
1036
1037 #ifdef __nvoc_chipset_h_disabled
clPcieGetGpuLostDiagnosticData(struct OBJGPU * pGpu,struct OBJCL * arg2,NvU8 * pBuffer,NvU32 size)1038 static inline NvU16 clPcieGetGpuLostDiagnosticData(struct OBJGPU *pGpu, struct OBJCL *arg2, NvU8 *pBuffer, NvU32 size) {
1039 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
1040 return 0;
1041 }
1042 #else //__nvoc_chipset_h_disabled
1043 #define clPcieGetGpuLostDiagnosticData(pGpu, arg2, pBuffer, size) clPcieGetGpuLostDiagnosticData_IMPL(pGpu, arg2, pBuffer, size)
1044 #endif //__nvoc_chipset_h_disabled
1045
1046 #define clPcieGetGpuLostDiagnosticData_HAL(pGpu, arg2, pBuffer, size) clPcieGetGpuLostDiagnosticData(pGpu, arg2, pBuffer, size)
1047
1048 NvU32 clGetChipsetL1ClockPMSupport_IMPL(struct OBJGPU *arg1, struct OBJCL *arg2);
1049
1050
1051 #ifdef __nvoc_chipset_h_disabled
clGetChipsetL1ClockPMSupport(struct OBJGPU * arg1,struct OBJCL * arg2)1052 static inline NvU32 clGetChipsetL1ClockPMSupport(struct OBJGPU *arg1, struct OBJCL *arg2) {
1053 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
1054 return 0;
1055 }
1056 #else //__nvoc_chipset_h_disabled
1057 #define clGetChipsetL1ClockPMSupport(arg1, arg2) clGetChipsetL1ClockPMSupport_IMPL(arg1, arg2)
1058 #endif //__nvoc_chipset_h_disabled
1059
1060 #define clGetChipsetL1ClockPMSupport_HAL(arg1, arg2) clGetChipsetL1ClockPMSupport(arg1, arg2)
1061
1062 NV_STATUS clConstruct_IMPL(struct OBJCL *arg_pCl);
1063
1064 #define __nvoc_clConstruct(arg_pCl) clConstruct_IMPL(arg_pCl)
1065 void clDestruct_IMPL(struct OBJCL *pCl);
1066
1067 #define __nvoc_clDestruct(pCl) clDestruct_IMPL(pCl)
1068 NvBool clUpstreamVgaDecodeEnabled_IMPL(struct OBJGPU *arg1, struct OBJCL *arg2);
1069
1070 #ifdef __nvoc_chipset_h_disabled
clUpstreamVgaDecodeEnabled(struct OBJGPU * arg1,struct OBJCL * arg2)1071 static inline NvBool clUpstreamVgaDecodeEnabled(struct OBJGPU *arg1, struct OBJCL *arg2) {
1072 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
1073 return NV_FALSE;
1074 }
1075 #else //__nvoc_chipset_h_disabled
1076 #define clUpstreamVgaDecodeEnabled(arg1, arg2) clUpstreamVgaDecodeEnabled_IMPL(arg1, arg2)
1077 #endif //__nvoc_chipset_h_disabled
1078
1079 NV_STATUS clPcieGetRootGenSpeed_IMPL(struct OBJGPU *arg1, struct OBJCL *arg2, NvU8 *arg3);
1080
1081 #ifdef __nvoc_chipset_h_disabled
clPcieGetRootGenSpeed(struct OBJGPU * arg1,struct OBJCL * arg2,NvU8 * arg3)1082 static inline NV_STATUS clPcieGetRootGenSpeed(struct OBJGPU *arg1, struct OBJCL *arg2, NvU8 *arg3) {
1083 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
1084 return NV_ERR_NOT_SUPPORTED;
1085 }
1086 #else //__nvoc_chipset_h_disabled
1087 #define clPcieGetRootGenSpeed(arg1, arg2, arg3) clPcieGetRootGenSpeed_IMPL(arg1, arg2, arg3)
1088 #endif //__nvoc_chipset_h_disabled
1089
1090 NV_STATUS clPcieGetDownstreamPortLinkCap2_IMPL(struct OBJGPU *arg1, struct OBJCL *arg2, NvU32 *arg3);
1091
1092 #ifdef __nvoc_chipset_h_disabled
clPcieGetDownstreamPortLinkCap2(struct OBJGPU * arg1,struct OBJCL * arg2,NvU32 * arg3)1093 static inline NV_STATUS clPcieGetDownstreamPortLinkCap2(struct OBJGPU *arg1, struct OBJCL *arg2, NvU32 *arg3) {
1094 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
1095 return NV_ERR_NOT_SUPPORTED;
1096 }
1097 #else //__nvoc_chipset_h_disabled
1098 #define clPcieGetDownstreamPortLinkCap2(arg1, arg2, arg3) clPcieGetDownstreamPortLinkCap2_IMPL(arg1, arg2, arg3)
1099 #endif //__nvoc_chipset_h_disabled
1100
1101 NV_STATUS clCheckUpstreamLtrSupport_IMPL(struct OBJGPU *arg1, struct OBJCL *arg2, NvBool *arg3);
1102
1103 #ifdef __nvoc_chipset_h_disabled
clCheckUpstreamLtrSupport(struct OBJGPU * arg1,struct OBJCL * arg2,NvBool * arg3)1104 static inline NV_STATUS clCheckUpstreamLtrSupport(struct OBJGPU *arg1, struct OBJCL *arg2, NvBool *arg3) {
1105 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
1106 return NV_ERR_NOT_SUPPORTED;
1107 }
1108 #else //__nvoc_chipset_h_disabled
1109 #define clCheckUpstreamLtrSupport(arg1, arg2, arg3) clCheckUpstreamLtrSupport_IMPL(arg1, arg2, arg3)
1110 #endif //__nvoc_chipset_h_disabled
1111
1112 NV_STATUS clGetAtomicTypesSupported_IMPL(NvU32 arg1, NvU8 arg2, struct OBJCL *arg3, NvU32 *arg4);
1113
1114 #ifdef __nvoc_chipset_h_disabled
clGetAtomicTypesSupported(NvU32 arg1,NvU8 arg2,struct OBJCL * arg3,NvU32 * arg4)1115 static inline NV_STATUS clGetAtomicTypesSupported(NvU32 arg1, NvU8 arg2, struct OBJCL *arg3, NvU32 *arg4) {
1116 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
1117 return NV_ERR_NOT_SUPPORTED;
1118 }
1119 #else //__nvoc_chipset_h_disabled
1120 #define clGetAtomicTypesSupported(arg1, arg2, arg3, arg4) clGetAtomicTypesSupported_IMPL(arg1, arg2, arg3, arg4)
1121 #endif //__nvoc_chipset_h_disabled
1122
1123 void clSyncWithGsp_IMPL(struct OBJCL *arg1, GspSystemInfo *arg2);
1124
1125 #ifdef __nvoc_chipset_h_disabled
clSyncWithGsp(struct OBJCL * arg1,GspSystemInfo * arg2)1126 static inline void clSyncWithGsp(struct OBJCL *arg1, GspSystemInfo *arg2) {
1127 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
1128 }
1129 #else //__nvoc_chipset_h_disabled
1130 #define clSyncWithGsp(arg1, arg2) clSyncWithGsp_IMPL(arg1, arg2)
1131 #endif //__nvoc_chipset_h_disabled
1132
1133 #undef PRIVATE_FIELD
1134
1135
1136 #endif // CHIPSET_H
1137
1138 #ifdef __cplusplus
1139 } // extern "C"
1140 #endif
1141
1142 #endif // _G_CHIPSET_NVOC_H_
1143