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Searched refs:dispChannelNum (Results 1 – 5 of 5) sorted by relevance

/open-nvidia-gpu/src/nvidia/generated/
H A Dg_disp_inst_mem_nvoc.h181 …InstMem, hClient, offset, dispChannelNum) instmemGenerateHashTableData_DISPATCH(pGpu, pInstMem, hC… argument
182 …InstMem, hClient, offset, dispChannelNum) instmemGenerateHashTableData_DISPATCH(pGpu, pInstMem, hC… argument
184 …em, hClient, hContextDma, dispChannelNum, result) instmemHashFunc_DISPATCH(pGpu, pInstMem, hClient… argument
185 …em, hClient, hContextDma, dispChannelNum, result) instmemHashFunc_DISPATCH(pGpu, pInstMem, hClient… argument
206 …*pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 hClient, NvU32 offset, NvU32 dispChannelNum) { in instmemGenerateHashTableData_DISPATCH() argument
207 …return pInstMem->__instmemGenerateHashTableData__(pGpu, pInstMem, hClient, offset, dispChannelNum); in instmemGenerateHashTableData_DISPATCH()
211 …return pInstMem->__instmemHashFunc__(pGpu, pInstMem, hClient, hContextDma, dispChannelNum, result); in instmemHashFunc_DISPATCH()
255 … *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 hClient, NvU32 offset, NvU32 dispChannelNum);
257 …*pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 hClient, NvU32 offset, NvU32 dispChannelNum) { in instmemGenerateHashTableData_4a4dee() argument
261 …tanceMemory *pInstMem, NvHandle hClient, NvHandle hContextDma, NvU32 dispChannelNum, NvU32 *result…
[all …]
/open-nvidia-gpu/src/nvidia/src/kernel/gpu/disp/arch/v03/
H A Dkern_disp_0300.c213 NvU32 dispChannelNum; in kdispGetDisplayChannelUserBaseAndSize_v03_00() local
219 status = kdispGetChannelNum_HAL(pKernelDisplay, channelClass, channelInstance, &dispChannelNum); in kdispGetDisplayChannelUserBaseAndSize_v03_00()
223 NV_ASSERT(dispChannelNum < NV_UDISP_FE_CHN_ASSY_BASEADR__SIZE_1); in kdispGetDisplayChannelUserBaseAndSize_v03_00()
225 *pOffset = NV_UDISP_FE_CHN_ASSY_BASEADR(dispChannelNum); in kdispGetDisplayChannelUserBaseAndSize_v03_00()
236 …Size = NV_UDISP_FE_CHN_ASSY_BASEADR_CURS(dispChannelNum + 1) - NV_UDISP_FE_CHN_ASSY_BASEADR_CURS(d… in kdispGetDisplayChannelUserBaseAndSize_v03_00()
240 …ize = NV_UDISP_FE_CHN_ASSY_BASEADR_WINIM(dispChannelNum + 1) - NV_UDISP_FE_CHN_ASSY_BASEADR_WINIM(… in kdispGetDisplayChannelUserBaseAndSize_v03_00()
248 …*pSize = NV_UDISP_FE_CHN_ASSY_BASEADR_WIN(dispChannelNum + 1) - NV_UDISP_FE_CHN_ASSY_BASEADR_WIN(d… in kdispGetDisplayChannelUserBaseAndSize_v03_00()
/open-nvidia-gpu/src/nvidia/src/kernel/gpu/disp/inst_mem/arch/v03/
H A Ddisp_inst_mem_0300.c100 NvU32 dispChannelNum, in instmemHashFunc_v03_00() argument
120 (((dispChannelNum & 0xF) << 6) | ((hClient >> 8) & 0x3F))^ in instmemHashFunc_v03_00()
121 ((dispChannelNum >> 4) & 0x7); in instmemHashFunc_v03_00()
134 NvU32 dispChannelNum in instmemGenerateHashTableData_v03_00() argument
139 SF_NUM(_UDISP, _HASH_TBL_CHN, dispChannelNum)); in instmemGenerateHashTableData_v03_00()
/open-nvidia-gpu/src/nvidia/src/kernel/gpu/disp/inst_mem/
H A Ddisp_inst_mem.c616 NvU32 entryOffset, dispChannelNum; in _instmemAddHashEntry() local
624 …nelNum_HAL(pKernelDisplay, pDispChannel->DispClass, pDispChannel->InstanceNumber, &dispChannelNum); in _instmemAddHashEntry()
629 … instmemHashFunc_HAL(pGpu, pInstMem, hClient, RES_GET_HANDLE(pContextDma), dispChannelNum, &hash); in _instmemAddHashEntry()
724 dispChannelNum); in _instmemAddHashEntry()
745 NvU32 dispChannelNum; in _instmemProbeHashEntry() local
751 …nelNum_HAL(pKernelDisplay, pDispChannel->DispClass, pDispChannel->InstanceNumber, &dispChannelNum); in _instmemProbeHashEntry()
757 dispChannelNum, &hash); in _instmemProbeHashEntry()
/open-nvidia-gpu/src/nvidia/src/kernel/gpu/disp/
H A Ddisp_channel.c744 NvU32 dispChannelNum; in kdispSetPushBufferParamsToPhysical_IMPL() local
747 …s = kdispGetChannelNum_HAL(pKernelDisplay, internalDispChnClass, channelInstance, &dispChannelNum); in kdispSetPushBufferParamsToPhysical_IMPL()