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Searched refs:hdr (Results 1 – 25 of 32) sorted by relevance

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/open-nvidia-gpu/src/nvidia/src/libraries/crashcat/v1/
H A Dcrashcat_report_v1.c81 if (!crashcatPacketHeaderValid(hdr)) in crashcatReportExtract_V1()
85 " bytes remaining\n", hdr, bytesRemaining); in crashcatReportExtract_V1()
149 if (!crashcatPacketHeaderValid(hdr) || in crashcatReportExtractReport_V1()
151 (crashcatPacketHeaderPayloadSize(hdr) != expPayloadSize)) in crashcatReportExtractReport_V1()
181 if (!crashcatPacketHeaderValid(hdr) || in crashcatReportExtractRiscv64CsrState_V1()
183 (crashcatPacketHeaderPayloadSize(hdr) != expPayloadSize)) in crashcatReportExtractRiscv64CsrState_V1()
213 if (!crashcatPacketHeaderValid(hdr) || in crashcatReportExtractRiscv64GprState_V1()
215 (crashcatPacketHeaderPayloadSize(hdr) != expPayloadSize)) in crashcatReportExtractRiscv64GprState_V1()
243 if (!crashcatPacketHeaderValid(hdr) || in crashcatReportExtractRiscv64Trace_V1()
251 const NvU32 payloadSize = crashcatPacketHeaderPayloadSize(hdr); in crashcatReportExtractRiscv64Trace_V1()
[all …]
/open-nvidia-gpu/src/common/uproc/os/common/include/
H A Dnv-crashcat-decoder.h89 NV_CRASHCAT_PACKET_FORMAT_VERSION crashcatPacketHeaderFormatVersion(NvCrashCatPacketHeader hdr) in crashcatPacketHeaderFormatVersion() argument
92 hdr); in crashcatPacketHeaderFormatVersion()
96 NvLength crashcatPacketHeaderPayloadSize(NvCrashCatPacketHeader hdr) in crashcatPacketHeaderPayloadSize() argument
100 (NV_CRASHCAT_MEM_UNIT_SIZE)DRF_VAL64(_CRASHCAT, _PACKET_HEADER, _PAYLOAD_UNIT_SIZE, hdr); in crashcatPacketHeaderPayloadSize()
114 NvBool crashcatPacketHeaderValid(NvCrashCatPacketHeader hdr) in crashcatPacketHeaderValid() argument
116 return (FLD_TEST_DRF64(_CRASHCAT, _PACKET_HEADER, _SIGNATURE, _VALID, hdr) && in crashcatPacketHeaderValid()
117 (crashcatPacketHeaderFormatVersion(hdr) > 0) && in crashcatPacketHeaderValid()
118 (crashcatPacketHeaderFormatVersion(hdr) <= NV_CRASHCAT_PACKET_FORMAT_VERSION_LAST) && in crashcatPacketHeaderValid()
119 (crashcatPacketHeaderPayloadSize(hdr) > 0)); in crashcatPacketHeaderValid()
126 NV_CRASHCAT_PACKET_TYPE crashcatPacketHeaderV1Type(NvCrashCatPacketHeader_V1 hdr) in crashcatPacketHeaderV1Type() argument
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/open-nvidia-gpu/src/nvidia-modeset/src/
H A Dnvkms-flip.c137 pProposedApiHead->dirty.hdr = TRUE; in UpdateProposedFlipStateOneApiHead()
142 pProposedApiHead->dirty.hdr = TRUE; in UpdateProposedFlipStateOneApiHead()
147 pProposedApiHead->dirty.hdr = TRUE; in UpdateProposedFlipStateOneApiHead()
154 pProposedApiHead->dirty.hdr = TRUE; in UpdateProposedFlipStateOneApiHead()
165 if (pProposedApiHead->dirty.hdr) { in UpdateProposedFlipStateOneApiHead()
346 pProposedApiHead->hdr.colorBpc = in InitNvKmsFlipWorkArea()
397 if (pProposedApiHead->dirty.hdr) { in FlipEvoOneApiHead()
415 if (pProposedApiHead->dirty.hdr) { in FlipEvoOneApiHead()
417 pProposedApiHead->hdr.colorSpace; in FlipEvoOneApiHead()
419 pProposedApiHead->hdr.colorBpc; in FlipEvoOneApiHead()
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/open-nvidia-gpu/kernel-open/nvidia-uvm/
H A Duvm_kvmalloc.c242 uvm_vmalloc_hdr_t *hdr; in get_hdr() local
244 hdr = container_of(p, uvm_vmalloc_hdr_t, ptr); in get_hdr()
245 UVM_ASSERT(hdr->alloc_size > UVM_KMALLOC_THRESHOLD); in get_hdr()
246 return hdr; in get_hdr()
251 uvm_vmalloc_hdr_t *hdr; in alloc_internal() local
267 hdr = vzalloc(sizeof(*hdr) + size); in alloc_internal()
269 hdr = vmalloc(sizeof(*hdr) + size); in alloc_internal()
271 if (!hdr) in alloc_internal()
274 hdr->alloc_size = size; in alloc_internal()
275 return hdr->ptr; in alloc_internal()
/open-nvidia-gpu/src/common/nvswitch/kernel/flcn/
H A Dflcnqueuerd_nvswitch.c142 bufferGenHdr = bMsg ? ((RM_FLCN_MSG *)pData)->msgGen.hdr : in _flcnQueueReadData_IMPL()
143 ((RM_FLCN_CMD *)pData)->cmdGen.hdr; in _flcnQueueReadData_IMPL()
239 bufferGenHdr = bMsg ? ((RM_FLCN_MSG *)pData)->msgGen.hdr : in _flcnQueueReaderGetNextHeader()
240 ((RM_FLCN_CMD *)pData)->cmdGen.hdr; in _flcnQueueReaderGetNextHeader()
257 bufferGenHdr = bMsg ? ((RM_FLCN_MSG *)pData)->msgGen.hdr : in _flcnQueueReaderGetNextHeader()
258 ((RM_FLCN_CMD *)pData)->cmdGen.hdr; in _flcnQueueReaderGetNextHeader()
306 bufferGenHdr = bMsg ? ((RM_FLCN_MSG *)pData)->msgGen.hdr : in _flcnQueueReaderReadBody()
307 ((RM_FLCN_CMD *)pData)->cmdGen.hdr; in _flcnQueueReaderReadBody()
394 device, pFlcn, pQueue, &((RM_FLCN_MSG *)pData)->msgGen.hdr, in _flcnQueueReaderReadHeader()
400 device, pFlcn, pQueue, &((RM_FLCN_CMD *)pData)->cmdGen.hdr, in _flcnQueueReaderReadHeader()
H A Dflcnqueue_nvswitch.c391 pFlcnCmd->cmdGen.hdr.unitId = RM_FLCN_UNIT_ID_REWIND; in _flcnQueuePopulateRewindCmd()
393 return pFlcnCmd->cmdGen.hdr.size; in _flcnQueuePopulateRewindCmd()
479 __FUNCTION__, pCmd->cmdGen.hdr.size); in _flcnQueueCmdWrite_IMPL()
537 __FUNCTION__, pCmd->cmdGen.hdr.unitId); in _flcnQueueCmdWrite_IMPL()
1106 __FUNCTION__, pMsgGen->hdr.unitId, pMsgGen->hdr.seqNumId); in _flcnQueueEventHandle_IMPL()
1130 if (pEventInfo->unitId == pMsgGen->hdr.unitId) in _flcnQueueEventHandle_IMPL()
1194 __FUNCTION__, pMsgGen->hdr.seqNumId); in _flcnQueueResponseHandle_IMPL()
1201 NVSWITCH_ASSERT(pSeqInfo->pMsgResp->hdr.size == pMsgGen->hdr.size); in _flcnQueueResponseHandle_IMPL()
1473 pCmd->cmdGen.hdr.seqNumId = pSeqInfo->seqNum; in _flcnQueueCmdPostNonBlocking_IMPL()
1559 if (pCmd->cmdGen.hdr.size < RM_FLCN_QUEUE_HDR_SIZE) in _flcnQueueCmdValidate()
[all …]
H A Dflcnrtosdebug_nvswitch.c86 pFlcnCmd->cmdGen.hdr.unitId, in flcnRtosDumpCmdQueue_nvswitch()
87 pFlcnCmd->cmdGen.hdr.size, in flcnRtosDumpCmdQueue_nvswitch()
88 pFlcnCmd->cmdGen.hdr.seqNumId, in flcnRtosDumpCmdQueue_nvswitch()
89 pFlcnCmd->cmdGen.hdr.ctrlFlags, in flcnRtosDumpCmdQueue_nvswitch()
H A Dflcn_call_hal_nvswitch.c114 pCmd->cmdGen.hdr.unitId, pCmd->cmdGen.hdr.size, pCmd->cmdGen.hdr.ctrlFlags, in flcnQueueCmdPostBlocking()
115 pCmd->cmdGen.hdr.seqNumId, pCmd->cmdGen.cmd, (NvU8)pCmd->cmdGen.cmd); in flcnQueueCmdPostBlocking()
125 pCmd->cmdGen.hdr.unitId, pCmd->cmdGen.hdr.size, pCmd->cmdGen.hdr.ctrlFlags, in flcnQueueCmdPostBlocking()
126 pCmd->cmdGen.hdr.seqNumId, pCmd->cmdGen.cmd, (NvU8)pCmd->cmdGen.cmd); in flcnQueueCmdPostBlocking()
/open-nvidia-gpu/src/common/nvswitch/kernel/ls10/
H A Dsoe_ls10.c101 cmd.hdr.unitId = RM_SOE_UNIT_NULL; in _nvswitch_soe_send_test_cmd()
103 cmd.hdr.size = RM_FLCN_QUEUE_HDR_SIZE; in _nvswitch_soe_send_test_cmd()
256 cmd.hdr.unitId = RM_SOE_UNIT_CORE; in nvswitch_soe_issue_nport_reset_ls10()
303 cmd.hdr.unitId = RM_SOE_UNIT_CORE; in nvswitch_soe_restore_nport_state_ls10()
357 cmd.hdr.unitId = RM_SOE_UNIT_CORE; in nvswitch_set_nport_tprod_state_ls10()
411 cmd.hdr.unitId = RM_SOE_UNIT_CORE; in nvswitch_soe_init_l2_state_ls10()
464 cmd.hdr.unitId = RM_SOE_UNIT_CORE; in nvswitch_soe_set_nport_interrupts_ls10()
538 cmd.hdr.unitId = RM_SOE_UNIT_CORE; in nvswitch_soe_disable_nport_fatal_interrupts_ls10()
1160 soeMessage.hdr.unitId, in _soeProcessMessages_LS10()
1161 soeMessage.hdr.size, in _soeProcessMessages_LS10()
[all …]
H A Dsmbpbi_ls10.c113 cmd.hdr.unitId = RM_SOE_UNIT_SMBPBI; in nvswitch_smbpbi_log_message_ls10()
114 cmd.hdr.size = RM_SOE_CMD_SIZE(SMBPBI, LOG_MESSAGE); in nvswitch_smbpbi_log_message_ls10()
177 cmd.hdr.unitId = RM_SOE_UNIT_SMBPBI; in nvswitch_smbpbi_send_init_data_ls10()
178 cmd.hdr.size = RM_SOE_CMD_SIZE(SMBPBI, INIT_DATA); in nvswitch_smbpbi_send_init_data_ls10()
H A Dtherm_ls10.c499 cmd.hdr.unitId = RM_SOE_UNIT_CORE; in nvswitch_ctrl_therm_read_voltage_ls10()
500 cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, GET_VOLTAGE); in nvswitch_ctrl_therm_read_voltage_ls10()
502 msg.hdr.unitId = RM_SOE_UNIT_CORE; in nvswitch_ctrl_therm_read_voltage_ls10()
503 msg.hdr.size = RM_SOE_MSG_SIZE(CORE, GET_VOLTAGE); in nvswitch_ctrl_therm_read_voltage_ls10()
583 cmd.hdr.unitId = RM_SOE_UNIT_CORE; in nvswitch_ctrl_therm_read_power_ls10()
584 cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, GET_POWER); in nvswitch_ctrl_therm_read_power_ls10()
586 msg.hdr.unitId = RM_SOE_UNIT_CORE; in nvswitch_ctrl_therm_read_power_ls10()
587 msg.hdr.size = RM_SOE_MSG_SIZE(CORE, GET_POWER); in nvswitch_ctrl_therm_read_power_ls10()
H A Dinforom_ls10.c661 bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR; in nvswitch_bbx_add_sxid_ls10()
662 bbxCmd.hdr.size = sizeof(bbxCmd); in nvswitch_bbx_add_sxid_ls10()
701 bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR; in nvswitch_bbx_unload_ls10()
702 bbxCmd.hdr.size = sizeof(bbxCmd); in nvswitch_bbx_unload_ls10()
740 bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR; in nvswitch_bbx_load_ls10()
741 bbxCmd.hdr.size = sizeof(bbxCmd); in nvswitch_bbx_load_ls10()
817 bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR; in nvswitch_bbx_get_sxid_ls10()
818 bbxCmd.hdr.size = sizeof(bbxCmd); in nvswitch_bbx_get_sxid_ls10()
941 bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR; in nvswitch_bbx_get_data_ls10()
942 bbxCmd.hdr.size = sizeof(bbxCmd); in nvswitch_bbx_get_data_ls10()
H A Dminion_ls10.c686 regval |= DRF_NUM(_MINION, _INBAND_SEND_DATA, _FLAGS,inBandData->hdr.data); in nvswitch_minion_send_inband_data_ls10()
821 nvlink_inband_drv_hdr_t hdr; in nvswitch_minion_receive_inband_data_ls10() local
835 hdr.data = DRF_VAL(_MINION, _INBAND_SEND_DATA, _FLAGS, regVal); in nvswitch_minion_receive_inband_data_ls10()
840 if ((hdr.data & (NVLINK_INBAND_DRV_HDR_TYPE_START | in nvswitch_minion_receive_inband_data_ls10()
848 if (hdr.data & NVLINK_INBAND_DRV_HDR_TYPE_START) in nvswitch_minion_receive_inband_data_ls10()
923 if (hdr.data & NVLINK_INBAND_DRV_HDR_TYPE_END) in nvswitch_minion_receive_inband_data_ls10()
/open-nvidia-gpu/src/nvidia-modeset/include/
H A Dnvkms-flip-workarea.h38 } hdr; member
45 NvU32 hdr : 1; member
/open-nvidia-gpu/src/common/nvswitch/kernel/lr10/
H A Dsoe_lr10.c212 cmd.hdr.unitId = RM_SOE_UNIT_NULL; in _nvswitch_soe_send_test_cmd()
214 cmd.hdr.size = RM_FLCN_QUEUE_HDR_SIZE; in _nvswitch_soe_send_test_cmd()
1597 cmd.hdr.unitId = RM_SOE_UNIT_CORE; in _soeDmaStartTest()
1841 cmd.hdr.unitId = RM_SOE_UNIT_BIF; in _soeSetPexEOM_LR10()
1940 cmd.hdr.unitId = RM_SOE_UNIT_BIF; in _soeGetPexEomStatus_LR10()
2030 cmd.hdr.unitId = RM_SOE_UNIT_BIF; in _soeGetUphyDlnCfgSpace_LR10()
2077 cmd.hdr.unitId = RM_SOE_UNIT_THERM; in _soeForceThermalSlowdown_LR10()
2119 cmd.hdr.unitId = RM_SOE_UNIT_BIF; in _soeSetPcieLinkSpeed_LR10()
2239 soeMessage.hdr.unitId, in _soeProcessMessages_LR10()
2240 soeMessage.hdr.size, in _soeProcessMessages_LR10()
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H A Dsmbpbi_lr10.c142 cmd.hdr.unitId = RM_SOE_UNIT_SMBPBI; in nvswitch_smbpbi_post_init_hal_lr10()
143 cmd.hdr.size = RM_SOE_CMD_SIZE(SMBPBI, INIT); in nvswitch_smbpbi_post_init_hal_lr10()
606 cmd.hdr.unitId = RM_SOE_UNIT_SMBPBI; in nvswitch_smbpbi_send_unload_lr10()
607 cmd.hdr.size = RM_SOE_CMD_SIZE(SMBPBI, UNLOAD); in nvswitch_smbpbi_send_unload_lr10()
/open-nvidia-gpu/src/common/nvswitch/kernel/
H A Dspi_nvswitch.c50 cmd.hdr.unitId = RM_SOE_UNIT_SPI; in nvswitch_spi_init()
51 cmd.hdr.size = RM_FLCN_QUEUE_HDR_SIZE + sizeof(RM_SOE_SPI_CMD); in nvswitch_spi_init()
H A Dsmbpbi_nvswitch.c184 cmd.hdr.unitId = RM_SOE_UNIT_SMBPBI; in nvswitch_smbpbi_set_link_error_info()
185 cmd.hdr.size = RM_SOE_CMD_SIZE(SMBPBI, SET_LINK_ERROR_INFO); in nvswitch_smbpbi_set_link_error_info()
H A Dbios_nvswitch.c83 cmd.hdr.unitId = RM_SOE_UNIT_CORE; in _nvswitch_core_bios_read()
84 cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, BIOS); in _nvswitch_core_bios_read()
/open-nvidia-gpu/src/common/nvswitch/common/inc/
H A Drmsoecmdif.h63 RM_FLCN_QUEUE_HDR hdr; member
90 RM_FLCN_QUEUE_HDR hdr; member
/open-nvidia-gpu/src/nvidia/arch/nvalloc/common/inc/
H A Dflcnifcmn.h91 RM_FLCN_QUEUE_HDR hdr; member
100 RM_FLCN_QUEUE_HDR hdr; member
/open-nvidia-gpu/src/common/nvswitch/kernel/soe/
H A Dsoe_nvswitch.c130 NvU32 cmdSize = pCmd->cmdGen.hdr.size; in _soeQueueCmdValidate_IMPL()
155 if (!RM_SOE_UNITID_IS_VALID(pCmd->cmdGen.hdr.unitId)) in _soeQueueCmdValidate_IMPL()
159 __FUNCTION__, pCmd->cmdGen.hdr.unitId); in _soeQueueCmdValidate_IMPL()
/open-nvidia-gpu/src/common/nvswitch/kernel/inc/ls10/
H A Dminion_ls10.h59 nvlink_inband_drv_hdr_t hdr; member
/open-nvidia-gpu/src/common/nvswitch/kernel/inforom/
H A Dinforom_nvswitch.c483 soeCmd.hdr.unitId = RM_SOE_UNIT_IFR; in _nvswitch_inforom_read_file()
484 soeCmd.hdr.size = sizeof(soeCmd); in _nvswitch_inforom_read_file()
572 soeCmd.hdr.unitId = RM_SOE_UNIT_IFR; in _nvswitch_inforom_write_file()
573 soeCmd.hdr.size = sizeof(soeCmd); in _nvswitch_inforom_write_file()
/open-nvidia-gpu/src/common/modeset/timing/
H A Dnvt_edidext_displayid.c229 …DISPLAYID_DATA_BLOCK_HEADER * hdr = (DISPLAYID_DATA_BLOCK_HEADER *) (section->data + block_locatio… in CODE_SEGMENT() local
230 …NvBool is_prod_id = remaining_length > 3 && block_location == 0 && hdr->type == 0 && hdr->data_byt… in CODE_SEGMENT()
234 if (hdr->type == 0 && !is_prod_id) in CODE_SEGMENT()
277 DISPLAYID_DATA_BLOCK_HEADER * hdr = (DISPLAYID_DATA_BLOCK_HEADER *) pBlock; in CODE_SEGMENT() local
284 if (hdr->data_bytes > max_length - NVT_DISPLAYID_DATABLOCK_HEADER_LEN) in CODE_SEGMENT()
289 *pLength = hdr->data_bytes + NVT_DISPLAYID_DATABLOCK_HEADER_LEN; in CODE_SEGMENT()
291 switch (hdr->type) in CODE_SEGMENT()

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