1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2019-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef GSP_STATIC_CONFIG_H 25 #define GSP_STATIC_CONFIG_H 26 27 // 28 // This header describes the set of static GPU configuration information 29 // that is collected during GSP RM init and made available to the 30 // CPU RM (aka GSP client) via NV_RM_RPC_GET_GSP_STATIC_INFO() call. 31 32 #include "ctrl/ctrl0080/ctrl0080gpu.h" 33 #include "ctrl/ctrl0080/ctrl0080gr.h" 34 #include "ctrl/ctrl2080/ctrl2080bios.h" 35 #include "ctrl/ctrl2080/ctrl2080fb.h" 36 #include "ctrl/ctrl2080/ctrl2080gpu.h" 37 38 #include "gpu/gpu.h" // COMPUTE_BRANDING_TYPE 39 #include "gpu/gpu_acpi_data.h" // ACPI_METHOD_DATA 40 #include "vgpu/rpc_headers.h" // MAX_GPC_COUNT 41 #include "platform/chipset/chipset.h" // BUSINFO 42 #include "gpu/nvbitmask.h" // NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX 43 44 // VF related info for GSP-RM 45 typedef struct GSP_VF_INFO 46 { 47 NvU32 totalVFs; 48 NvU32 firstVFOffset; 49 NvU64 FirstVFBar0Address; 50 NvU64 FirstVFBar1Address; 51 NvU64 FirstVFBar2Address; 52 NvBool b64bitBar0; 53 NvBool b64bitBar1; 54 NvBool b64bitBar2; 55 } GSP_VF_INFO; 56 57 // Cache config registers from pcie space 58 typedef struct 59 { 60 // Link capabilities 61 NvU32 linkCap; 62 } GSP_PCIE_CONFIG_REG; 63 64 typedef struct GspSMInfo_t 65 { 66 NvU32 version; 67 NvU32 regBankCount; 68 NvU32 regBankRegCount; 69 NvU32 maxWarpsPerSM; 70 NvU32 maxThreadsPerWarp; 71 NvU32 geomGsObufEntries; 72 NvU32 geomXbufEntries; 73 NvU32 maxSPPerSM; 74 NvU32 rtCoreCount; 75 } GspSMInfo; 76 77 typedef struct 78 { 79 NvU32 ecidLow; 80 NvU32 ecidHigh; 81 NvU32 ecidExtended; 82 } EcidManufacturingInfo; 83 84 // Fetched from GSP-RM into CPU-RM 85 typedef struct GspStaticConfigInfo_t 86 { 87 NvU8 grCapsBits[NV0080_CTRL_GR_CAPS_TBL_SIZE]; 88 NV2080_CTRL_GPU_GET_GID_INFO_PARAMS gidInfo; 89 NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS gpcInfo; 90 NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS tpcInfo[MAX_GPC_COUNT]; 91 NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS zcullInfo[MAX_GPC_COUNT]; 92 NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS SKUInfo; 93 NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS fbRegionInfoParams; 94 95 NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS sriovCaps; 96 NvU32 sriovMaxGfid; 97 98 NvU32 engineCaps[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX]; 99 100 GspSMInfo SM_info; 101 102 NvBool poisonFuseEnabled; 103 104 NvU64 fb_length; 105 NvU64 fbio_mask; 106 NvU32 fb_bus_width; 107 NvU32 fb_ram_type; 108 NvU64 fbp_mask; 109 NvU32 l2_cache_size; 110 111 NvU32 gfxpBufferSize[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL]; 112 NvU32 gfxpBufferAlignment[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL]; 113 114 NvU8 gpuNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH]; 115 NvU8 gpuShortNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH]; 116 NvU16 gpuNameString_Unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH]; 117 NvBool bGpuInternalSku; 118 NvBool bIsQuadroGeneric; 119 NvBool bIsQuadroAd; 120 NvBool bIsNvidiaNvs; 121 NvBool bIsVgx; 122 NvBool bGeforceSmb; 123 NvBool bIsTitan; 124 NvBool bIsTesla; 125 NvBool bIsMobile; 126 NvBool bIsGc6Rtd3Allowed; 127 NvBool bIsGcOffRtd3Allowed; 128 NvBool bIsGcoffLegacyAllowed; 129 130 /* "Total Board Power" refers to power requirement of GPU, 131 * while in GC6 state. Majority of this power will be used 132 * to keep V-RAM active to preserve its content. 133 * Some energy maybe consumed by Always-on components on GPU chip. 134 * This power will be provided by 3.3v voltage rail. 135 */ 136 NvU16 RTD3GC6TotalBoardPower; 137 138 /* PERST# (i.e. PCI Express Reset) is a sideband signal 139 * generated by the PCIe Host to indicate the PCIe devices, 140 * that the power-rails and the reference-clock are stable. 141 * The endpoint device typically uses this signal as a global reset. 142 */ 143 NvU16 RTD3GC6PerstDelay; 144 145 NvU64 bar1PdeBase; 146 NvU64 bar2PdeBase; 147 148 NvBool bVbiosValid; 149 NvU32 vbiosSubVendor; 150 NvU32 vbiosSubDevice; 151 152 NvBool bPageRetirementSupported; 153 154 NvBool bSplitVasBetweenServerClientRm; 155 156 NvBool bClRootportNeedsNosnoopWAR; 157 158 VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS displaylessMaxHeads; 159 VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS displaylessMaxResolution; 160 NvU64 displaylessMaxPixels; 161 162 // Client handle for internal RMAPI control. 163 NvHandle hInternalClient; 164 165 // Device handle for internal RMAPI control. 166 NvHandle hInternalDevice; 167 168 // Subdevice handle for internal RMAPI control. 169 NvHandle hInternalSubdevice; 170 171 NvBool bSelfHostedMode; 172 NvBool bAtsSupported; 173 174 NvBool bIsGpuUefi; 175 NvBool bIsEfiInit; 176 177 EcidManufacturingInfo ecidInfo[2]; 178 } GspStaticConfigInfo; 179 180 // Pushed from CPU-RM to GSP-RM 181 typedef struct GspSystemInfo 182 { 183 NvU64 gpuPhysAddr; 184 NvU64 gpuPhysFbAddr; 185 NvU64 gpuPhysInstAddr; 186 NvU64 gpuPhysIoAddr; 187 NvU64 nvDomainBusDeviceFunc; 188 NvU64 simAccessBufPhysAddr; 189 NvU64 notifyOpSharedSurfacePhysAddr; 190 NvU64 pcieAtomicsOpMask; 191 NvU64 consoleMemSize; 192 NvU64 maxUserVa; 193 NvU32 pciConfigMirrorBase; 194 NvU32 pciConfigMirrorSize; 195 NvU32 PCIDeviceID; 196 NvU32 PCISubDeviceID; 197 NvU32 PCIRevisionID; 198 NvU32 pcieAtomicsCplDeviceCapMask; 199 NvU8 oorArch; 200 NvU64 clPdbProperties; 201 NvU32 Chipset; 202 NvBool bGpuBehindBridge; 203 NvBool bFlrSupported; 204 NvBool b64bBar0Supported; 205 NvBool bMnocAvailable; 206 NvBool bUpstreamL0sUnsupported; 207 NvBool bUpstreamL1Unsupported; 208 NvBool bUpstreamL1PorSupported; 209 NvBool bUpstreamL1PorMobileOnly; 210 NvU8 upstreamAddressValid; 211 BUSINFO FHBBusInfo; 212 BUSINFO chipsetIDInfo; 213 ACPI_METHOD_DATA acpiMethodData; 214 NvU32 hypervisorType; 215 NvBool bIsPassthru; 216 NvU64 sysTimerOffsetNs; 217 GSP_VF_INFO gspVFInfo; 218 NvBool bIsPrimary; 219 NvBool isGridBuild; 220 GSP_PCIE_CONFIG_REG pcieConfigReg; 221 NvU32 gridBuildCsp; 222 NvBool bPreserveVideoMemoryAllocations; 223 NvBool bTdrEventSupported; 224 NvBool bFeatureStretchVblankCapable; 225 NvBool bClockBoostSupported; 226 } GspSystemInfo; 227 228 229 #endif /* GSP_STATIC_CONFIG_H */ 230