1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef _PMGR_NVSWITCH_H_ 25 #define _PMGR_NVSWITCH_H_ 26 27 #include "ctrl_dev_nvswitch.h" 28 29 #define NVSWITCH_BITS_PER_BYTE 8 30 31 #define NVSWITCH_HIGH NV_TRUE 32 #define NVSWITCH_LOW NV_FALSE 33 34 /*! Extract the first byte of a 10-bit address. */ 35 #define NVSWITCH_GET_ADDRESS_10BIT_FIRST(a) ((NvU8)((((a) >> 8) & 0x6) | 0xF0)) 36 37 /*! Extract the second byte of a 10-bit address. */ 38 #define NVSWITCH_GET_ADDRESS_10BIT_SECOND(a) ((NvU8)(((a) >> 1) & 0xFF)) 39 40 /*! Attaching read to read application interface */ 41 #define NVSWITCH_I2C_READ(a,b) _nvswitch_i2c_i2cRead(device, a, b) 42 43 #define NVSWITCH_I2C_DELAY(a) NVSWITCH_NSEC_DELAY(a) 44 45 #define NVSWITCH_MAX_I2C_PORTS 4 46 47 /*! bit 0 of address set indicates read cycle to follow */ 48 #define NVSWITCH_I2C_READCYCLE ((NvU8)0x01) 49 50 /*! Determine if an address is valid in the 7-bit address space. */ 51 #define NVSWITCH_I2C_IS_7BIT_I2C_ADDRESS(a) ((a) <= 0xFF) 52 53 /*! Determine if an address is valid in the 10-bit address space. */ 54 #define NVSWITCH_I2C_IS_10BIT_I2C_ADDRESS(a) ((a) <= 0x7FF) 55 56 // by-the-spec delay defaults (yields 100KHz) 57 #define NVSWITCH_I2C_PROFILE_STANDARD_tF 300 58 #define NVSWITCH_I2C_PROFILE_STANDARD_tR 1000 59 #define NVSWITCH_I2C_PROFILE_STANDARD_tSUDAT 1800 // actually, spec calls for (min) 250, but we've borrowed from tHDDAT 60 #define NVSWITCH_I2C_PROFILE_STANDARD_tHDDAT 1900 // actually, spec calls for (max) 3450, but we've loaned time to tSUDAT 61 #define NVSWITCH_I2C_PROFILE_STANDARD_tHIGH 4000 62 #define NVSWITCH_I2C_PROFILE_STANDARD_tSUSTO 4000 63 #define NVSWITCH_I2C_PROFILE_STANDARD_tHDSTA 4000 64 #define NVSWITCH_I2C_PROFILE_STANDARD_tSUSTA 4700 65 #define NVSWITCH_I2C_PROFILE_STANDARD_tBUF 4700 66 #define NVSWITCH_I2C_PROFILE_STANDARD_tLOW 4700 // NVSWITCH_I2C_PROFILE_STANDARD_tSUDAT + NVSWITCH_I2C_PROFILE_STANDARD_tR + NVSWITCH_I2C_PROFILE_STANDARD_tHDDAT 67 #define NVSWITCH_I2C_PROFILE_STANDARD_CYCLEPERIOD 10000 // NVSWITCH_I2C_PROFILE_STANDARD_tF + NVSWITCH_I2C_PROFILE_STANDARD_tLOW + NVSWITCH_I2C_PROFILE_STANDARD_tR + NVSWITCH_I2C_PROFILE_STANDARD_tHIGH 68 69 // by-the-spec delay defaults (yields 400KHz) 70 #define NVSWITCH_I2C_PROFILE_FAST_tF 300 71 #define NVSWITCH_I2C_PROFILE_FAST_tR 300 72 #define NVSWITCH_I2C_PROFILE_FAST_tSUDAT 200 // actually, spec calls for (min) 100, but we've borrowed from tHDDAT 73 #define NVSWITCH_I2C_PROFILE_FAST_tHDDAT 800 // actually, spec calls for (max) 900, but we've loaned time to tSUDAT 74 #define NVSWITCH_I2C_PROFILE_FAST_tHIGH 600 75 #define NVSWITCH_I2C_PROFILE_FAST_tSUSTO 600 76 #define NVSWITCH_I2C_PROFILE_FAST_tHDSTA 600 77 #define NVSWITCH_I2C_PROFILE_FAST_tSUSTA 600 78 #define NVSWITCH_I2C_PROFILE_FAST_tBUF 1300 79 #define NVSWITCH_I2C_PROFILE_FAST_tLOW 1300 // NVSWITCH_I2C_PROFILE_STANDARD_tSUDAT + NVSWITCH_I2C_PROFILE_STANDARD_tR + NVSWITCH_I2C_PROFILE_STANDARD_tHDDAT 80 #define NVSWITCH_I2C_PROFILE_FAST_CYCLEPERIOD 2500 // NVSWITCH_I2C_PROFILE_STANDARD_tF + NVSWITCH_I2C_PROFILE_STANDARD_tLOW + NVSWITCH_I2C_PROFILE_STANDARD_tR + NVSWITCH_I2C_PROFILE_STANDARD_tHIGH 81 82 /*! 83 * The I2C specification does not specify any timeout conditions for clock 84 * stretching, i.e. any device can hold down SCL as long as it likes so this 85 * value needs to be adjusted on case by case basis. 86 */ 87 #define NVSWITCH_I2C_SCL_CLK_TIMEOUT_1200US 1200 88 #define NVSWITCH_I2C_SCL_CLK_TIMEOUT_1000KHZ (NVSWITCH_I2C_SCL_CLK_TIMEOUT_100KHZ * 4) 89 #define NVSWITCH_I2C_SCL_CLK_TIMEOUT_400KHZ (NVSWITCH_I2C_SCL_CLK_TIMEOUT_100KHZ * 4) 90 #define NVSWITCH_I2C_SCL_CLK_TIMEOUT_300KHZ (NVSWITCH_I2C_SCL_CLK_TIMEOUT_100KHZ * 3) 91 #define NVSWITCH_I2C_SCL_CLK_TIMEOUT_200KHZ (NVSWITCH_I2C_SCL_CLK_TIMEOUT_100KHZ * 2) 92 #define NVSWITCH_I2C_SCL_CLK_TIMEOUT_100KHZ (NVSWITCH_I2C_SCL_CLK_TIMEOUT_1200US / 10) 93 94 /* A reasonable SCL timeout is five cycles at 20 KHz. Full use should be rare 95 * in devices, occurring when in the middle of a real-time task. That comes to 96 * 25 clock cycles at 100 KHz, or 250 us. */ 97 #define NVSWITCH_I2C_SCL_CLK_TIMEOUT_250US 250 98 99 /* We don't want I2C to deal with traffic slower than 20 KHz (50 us cycle). 100 */ 101 #define NVSWITCH_I2C_MAX_CYCLE_US 50 102 103 /* The longest HW I2C transaction: S BYTE*2 S BYTE*4 P, at 1 each for S/P, and 104 * 9 for each byte (+ack). */ 105 #define NVSWITCH_I2C_HW_MAX_CYCLES ((1 * 3) + (9 * 6)) 106 107 /* We determine the HW operational timeout as the longest operation, plus two 108 * long SCL clock stretches. */ 109 #define I2C_HW_IDLE_TIMEOUT_NS (1000 * \ 110 ((NVSWITCH_I2C_MAX_CYCLE_US * NVSWITCH_I2C_HW_MAX_CYCLES) + (NVSWITCH_I2C_SCL_CLK_TIMEOUT_1200US * 2))) 111 112 // 113 // PMGR board configuration information 114 // 115 116 #define NVSWITCH_DESCRIBE_I2C_DEVICE(_port, _addr, _type, _rdWrAccessMask) \ 117 {NVSWITCH_I2C_PORT ## _port, _addr, NVSWITCH_I2C_DEVICE ## _type, _rdWrAccessMask} 118 119 #define NVSWITCH_DESCRIBE_GPIO_PIN(_pin, _func, _hw_select, _misc_io) \ 120 {_pin, NVSWITCH_GPIO_ENTRY_FUNCTION ## _func, _hw_select, \ 121 NVSWITCH_GPIO_ENTRY_MISC_IO_ ## _misc_io} 122 123 /*! Structure containing a description of the I2C bus as needed by the software 124 * bit-banging implementation. 125 */ 126 typedef struct 127 { 128 NvU32 sclOut; // Bit number for SCL Output 129 NvU32 sdaOut; // Bit number for SDA Output 130 131 NvU32 sclIn; // Bit number for SCL Input 132 NvU32 sdaIn; // Bit number for SDA Input 133 134 NvU32 port; // Port number of the driving lines 135 NvU32 curLine; // Required for isLineHighFunction 136 137 NvU32 regCache; // Keeps the cache value of registers. 138 // 139 // The following timings are used as stand-ins for I2C spec timings, so 140 // that different speed modes may share the same code. 141 // 142 NvU16 tF; 143 NvU16 tR; 144 NvU16 tSuDat; 145 NvU16 tHdDat; 146 NvU16 tHigh; 147 NvU16 tSuSto; 148 NvU16 tHdSta; 149 NvU16 tSuSta; 150 NvU16 tBuf; 151 NvU16 tLow; 152 } NVSWITCH_I2C_SW_BUS; 153 154 /*! @brief Internal Command structure for HW I2C to perform I2C transaction */ 155 typedef struct 156 { 157 NvU32 port; 158 NvU32 bRead; 159 NvU32 cntl; 160 NvU32 data; 161 NvU32 bytesRemaining; 162 NvS32 status; 163 NvU8 *pMessage; 164 NvBool bBlockProtocol; 165 } NVSWITCH_I2C_HW_CMD, *PNVSWITCH_I2C_HW_CMD; 166 167 typedef enum { 168 i2cProfile_Standard, 169 i2cProfile_Fast, 170 i2cProfile_End 171 } NVSWITCH_I2CPROFILE; 172 173 typedef enum 174 { 175 pmgrReg_i2cAddr, 176 pmgrReg_i2cCntl, 177 pmgrReg_i2cTiming, 178 pmgrReg_i2cOverride, 179 pmgrReg_i2cPoll, 180 pmgrReg_i2cData, 181 pmgrReg_unsupported 182 } NVSWITCH_PMGRREG_TYPE; 183 184 185 // I2C Speed limits 186 #define NVSWITCH_I2C_SPEED_LIMIT_NONE NV_U16_MAX //Close enough to not having a speed limit. 187 #define NVSWITCH_I2C_SPEED_1000KHZ 1000 188 #define NVSWITCH_I2C_SPEED_400KHZ 400 189 #define NVSWITCH_I2C_SPEED_300KHZ 300 190 #define NVSWITCH_I2C_SPEED_200KHZ 200 191 #define NVSWITCH_I2C_SPEED_100KHZ 100 192 193 enum 194 { 195 i2cSpeedLimit_dcb = 0, 196 i2cSpeedLimit_ctrl, 197 198 // Always leave as last element! 199 NVSWITCH_I2C_SPEED_LIMIT_MAX_DEVICES 200 }; 201 202 203 // Timing for I2C cycles (allows for possibility of tweaking timing) 204 typedef struct __NVSWITCH_NVSWITCH_I2CTIMING 205 { 206 NvU32 tR; // at 100KHz, normally 1000ns 207 NvU32 tF; // at 100KHz, normally 300ns 208 NvU32 tHIGH; // at 100KHz, normally 4000ns 209 NvU32 tSUDAT; // at 100KHz, normally 250ns (min), but we borrow time from tHDDAT to improve clock phase 210 NvU32 tHDDAT; // at 100KHz, normally 3450ns (max), but we loan time to tSUDAT to improve clock phase 211 NvU32 tSUSTO; // at 100KHz, normally 4000ns 212 NvU32 tHDSTA; // at 100KHz, normally 4000ns 213 NvU32 tBUF; // at 100KHz, normally 4700ns 214 215 NvU32 tLOW; // computed to be: tSUDAT + tR + tHDDAT 216 217 NvU32 speed; // Port speed 218 219 } NVSWITCH_I2CTIMING; 220 221 #define NV_NVSWITCH_I2C_DEVICE_WRITE_ACCESS_LEVEL 2:0 222 #define NV_NVSWITCH_I2C_DEVICE_READ_ACCESS_LEVEL 5:3 223 #define NV_NVSWITCH_I2C_DEVICE_ACCESS_LEVEL_PUBLIC 0x00000000 224 #define NV_NVSWITCH_I2C_DEVICE_ACCESS_LEVEL_PRIVILEGED 0x00000001 225 #define NV_NVSWITCH_I2C_DEVICE_ACCESS_LEVEL_INTERNAL 0x00000002 226 #define NV_NVSWITCH_I2C_DEVICE_ACCESS_LEVEL_INACCESSIBLE 0x00000003 227 #define NV_NVSWITCH_I2C_DEVICE_READ_ACCESS_LEVEL_PUBLIC NV_NVSWITCH_I2C_DEVICE_ACCESS_LEVEL_PUBLIC 228 #define NV_NVSWITCH_I2C_DEVICE_READ_ACCESS_LEVEL_PRIVILEGED NV_NVSWITCH_I2C_DEVICE_ACCESS_LEVEL_PRIVILEGED 229 #define NV_NVSWITCH_I2C_DEVICE_READ_ACCESS_LEVEL_INTERNAL NV_NVSWITCH_I2C_DEVICE_ACCESS_LEVEL_INTERNAL 230 #define NV_NVSWITCH_I2C_DEVICE_READ_ACCESS_LEVEL_INACCESSIBLE NV_NVSWITCH_I2C_DEVICE_ACCESS_LEVEL_INACCESSIBLE 231 #define NV_NVSWITCH_I2C_DEVICE_WRITE_ACCESS_LEVEL_PUBLIC NV_NVSWITCH_I2C_DEVICE_ACCESS_LEVEL_PUBLIC 232 #define NV_NVSWITCH_I2C_DEVICE_WRITE_ACCESS_LEVEL_PRIVILEGED NV_NVSWITCH_I2C_DEVICE_ACCESS_LEVEL_PRIVILEGED 233 #define NV_NVSWITCH_I2C_DEVICE_WRITE_ACCESS_LEVEL_INTERNAL NV_NVSWITCH_I2C_DEVICE_ACCESS_LEVEL_INTERNAL 234 #define NV_NVSIWTCH_I2C_DEVICE_WRITE_ACCESS_LEVEL_INACCESSIVLE NV_NVSWITCH_I2C_DEVICE_ACCESS_LEVEL_INACCESSIBLE 235 236 typedef struct NVSWITCH_I2C_DEVICE_DESCRIPTOR 237 { 238 NVSWITCH_I2C_PORT_TYPE i2cPortLogical; //<! Logical I2C port where the device sits 239 NvU32 i2cAddress; //<! I2C slave address 240 NVSWITCH_I2C_DEVICE_TYPE i2cDeviceType; 241 NvU8 i2cRdWrAccessMask; 242 } NVSWITCH_I2C_DEVICE_DESCRIPTOR_TYPE; 243 244 245 typedef struct NVSWITCH_OBJI2C *PNVSWITCH_OBJI2C; 246 247 #define NVSWITCH_I2C_SPEED_MODE_100KHZ 0 248 #define NVSWITCH_I2C_SPEED_MODE_200KHZ 1 249 #define NVSWITCH_I2C_SPEED_MODE_300KHZ 2 250 #define NVSWITCH_I2C_SPEED_MODE_400KHZ 3 251 #define NVSWITCH_I2C_SPEED_MODE_1000KHZ 4 252 253 typedef struct _nvswitch_tag_i2c_port 254 { 255 // Timing for I2C cycles (allows for possibility of tweaking timing) 256 NVSWITCH_I2CTIMING Timing; 257 258 NVSWITCH_I2C_HW_CMD hwCmd; 259 260 NvU32 defaultSpeedMode; 261 } NVSWITCH_I2CPORT, *PNVSWITCH_I2CPORT; 262 263 264 struct NVSWITCH_OBJI2C 265 { 266 // 267 // Addresses of I2C ports 268 // 269 // Note: The index of array is logical port number NOT physical 270 // 271 NVSWITCH_I2CPORT Ports[NVSWITCH_MAX_I2C_PORTS]; 272 273 // 274 // Private data 275 // 276 277 // I2C Mutex/Synchronization state 278 NvU32 I2CAcquired; 279 280 NvU32 PortInfo[NVSWITCH_MAX_I2C_PORTS]; 281 #define NV_I2C_PORTINFO_DEFINED 0:0 282 #define NV_I2C_PORTINFO_DEFINED_ABSENT 0x00000000 283 #define NV_I2C_PORTINFO_DEFINED_PRESENT 0x00000001 284 #define NV_I2C_PORTINFO_ACCESS_ALLOWED 1:1 285 #define NV_I2C_PORTINFO_ACCESS_ALLOWED_FALSE 0x00000000 286 #define NV_I2C_PORTINFO_ACCESS_ALLOWED_TRUE 0x00000001 287 288 NVSWITCH_I2C_DEVICE_DESCRIPTOR_TYPE *device_list; 289 NvU32 device_list_size; 290 291 // I2C device allow list 292 NVSWITCH_I2C_DEVICE_DESCRIPTOR_TYPE *i2c_allow_list; 293 NvU32 i2c_allow_list_size; 294 295 // For I2C via SOE support 296 NvBool soeI2CSupported; 297 NvBool kernelI2CSupported; 298 void *pCpuAddr; 299 NvU64 dmaHandle; 300 }; 301 302 // 303 // Thermal 304 // 305 306 #define NVSWITCH_THERM_METHOD_UNKNOWN 0x00 307 #define NVSWITCH_THERM_METHOD_I2C 0x01 308 #define NVSWITCH_THERM_METHOD_MCU 0x02 309 310 typedef struct nvswitch_tdiode_info_type 311 { 312 NvU32 method; 313 struct NVSWITCH_I2C_DEVICE_DESCRIPTOR *method_i2c_info; 314 315 NvS32 A; 316 NvS32 B; 317 NvS32 offset; 318 } NVSWITCH_TDIODE_INFO_TYPE; 319 320 void nvswitch_i2c_destroy(nvswitch_device *device); 321 void nvswitch_i2c_init(nvswitch_device *device); 322 323 #endif //_PMGR_NVSWITCH_H_ 324