1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #pragma once 25 26 #include <nvtypes.h> 27 28 // 29 // This file was generated with FINN, an NVIDIA coding tool. 30 // Source file: ctrl/ctrl2080/ctrl2080internal.finn 31 // 32 33 #include "nvimpshared.h" 34 #include "cc_drv.h" 35 #include "ctrl/ctrl2080/ctrl2080base.h" 36 37 #include "ctrl/ctrl2080/ctrl2080gpu.h" 38 #include "ctrl/ctrl2080/ctrl2080gr.h" /* Some controls derivative of 2080gr */ 39 #include "ctrl/ctrl0080/ctrl0080msenc.h" /* NV0080_CTRL_MSENC_CAPS_TBL_SIZE */ 40 #include "ctrl/ctrl0080/ctrl0080bsp.h" /* NV0080_CTRL_BSP_CAPS_TBL_SIZE */ 41 #include "ctrl/ctrl2080/ctrl2080fifo.h" /* NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO */ 42 #include "ctrl/ctrl0073/ctrl0073system.h" /* NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS */ 43 #include "ctrl/ctrl0000/ctrl0000system.h" 44 #include "ctrl/ctrl90f1.h" 45 #include "ctrl/ctrl30f1.h" 46 #include "nvcfg_sdk.h" 47 48 /*! 49 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO 50 * 51 * This command obtains information from physical RM for use by CPU-RM. 52 * 53 * feHwSysCap 54 * Display IP v03_00 and later. 55 * Contents of capability register. 56 * 57 * windowPresentMask 58 * Display IP v03_00 and later. 59 * Mask for the present WINDOWs actually on the current chip. 60 * bFbRemapperEnabled 61 * Display IP v02_01 and later. 62 * Indicates that the display remapper HW exists and is enabled. 63 * numHeads 64 * Display IP v02_01 and later. 65 * Provides the number of heads HW support. 66 */ 67 68 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO (0x20800a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ 69 70 #define NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0x1U) 71 72 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS { 73 NvU32 feHwSysCap; 74 NvU32 windowPresentMask; 75 NvBool bFbRemapperEnabled; 76 NvU32 numHeads; 77 NvU32 i2cPort; 78 NvU32 internalDispActiveMask; 79 NvU32 embeddedDisplayPortMask; 80 NvBool bExternalMuxSupported; 81 NvBool bInternalMuxSupported; 82 } NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS; 83 84 85 86 // 87 // MemorySystem settings that are static after GPU state init/load is finished. 88 // 89 // Fields are shared between the VGPU guest/GSP Client as well as the VGPU 90 // host/GSP-RM. 91 // 92 #define NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID (0x1CU) 93 94 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS { 95 /*! Determines if RM should use 1 to 1 Comptagline allocation policy */ 96 NvBool bOneToOneComptagLineAllocation; 97 98 /*! Determines if RM should use 1 to 4 Comptagline allocation policy */ 99 NvBool bUseOneToFourComptagLineAllocation; 100 101 /*! Determines if RM should use raw Comptagline allocation policy */ 102 NvBool bUseRawModeComptaglineAllocation; 103 104 /*! Has COMPBIT_BACKING_SIZE been overridden to zero (i.e. disabled)? */ 105 NvBool bDisableCompbitBacking; 106 107 /*! Determine if we need to disable post L2 compression */ 108 NvBool bDisablePostL2Compression; 109 110 /*! Is ECC DRAM feature supported? */ 111 NvBool bEnabledEccFBPA; 112 113 NvBool bL2PreFill; 114 115 /*! L2 cache size */ 116 NV_DECLARE_ALIGNED(NvU64 l2CacheSize, 8); 117 118 /*! Indicate whether fpba is present or not */ 119 NvBool bFbpaPresent; 120 121 /*! Size covered by one comptag */ 122 NvU32 comprPageSize; 123 124 /*! log32(comprPageSize) */ 125 NvU32 comprPageShift; 126 127 /*! RAM type */ 128 NvU32 ramType; 129 130 /*! LTC count */ 131 NvU32 ltcCount; 132 133 /*! LTS per LTC count */ 134 NvU32 ltsPerLtcCount; 135 } NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS; 136 137 /*! 138 * Retrieve Memory System Static data. 139 */ 140 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_STATIC_CONFIG (0x20800a1c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID" */ 141 142 /* 143 * NV2080_CTRL_CMD_INTERNAL_REGISTER_UVM_ACCESS_CNTR_BUFFER 144 * 145 * This command sends access counter buffer pages allocated by CPU-RM 146 * to be setup and enabled in physical RM. 147 * 148 * accessCounterIndex 149 * Index of access counter buffer to register. 150 * 151 * bufferSize 152 * Size of the access counter buffer to register. 153 * 154 * bufferPteArray 155 * Pages of access counter buffer. 156 * 157 * Possible status values returned are: 158 * NV_OK 159 */ 160 #define NV2080_CTRL_CMD_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER (0x20800a1d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID" */ 161 162 #define NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES 64 163 #define NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID (0x1DU) 164 165 typedef struct NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS { 166 NvU32 accessCounterIndex; 167 NvU32 bufferSize; 168 NV_DECLARE_ALIGNED(NvU64 bufferPteArray[NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES], 8); 169 } NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS; 170 171 /* 172 * NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER 173 * 174 * This command requests physical RM to disable the access counter buffer. 175 * 176 * accessCounterIndex 177 * Index of access counter buffer to unregister. 178 * 179 * Possible status values returned are: 180 * NV_OK 181 */ 182 #define NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER (0x20800a1e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID" */ 183 184 #define NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID (0x1EU) 185 186 typedef struct NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS { 187 NvU32 accessCounterIndex; 188 } NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS; 189 190 #define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES 8 191 192 /*! 193 * @ref NV2080_CTRL_CMD_GR_GET_CAPS_V2 194 */ 195 196 197 198 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CAPS { 199 NvU8 capsTbl[NV0080_CTRL_GR_CAPS_TBL_SIZE]; 200 } NV2080_CTRL_INTERNAL_STATIC_GR_CAPS; 201 202 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS_MESSAGE_ID (0x20U) 203 204 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS { 205 NV2080_CTRL_INTERNAL_STATIC_GR_CAPS engineCaps[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 206 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS; 207 208 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS (0x20800a1f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID" */ 209 210 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID (0x1FU) 211 212 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS; 213 214 /*! 215 * @ref NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER 216 * @ref NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS 217 */ 218 219 220 221 #define NV2080_CTRL_INTERNAL_GR_MAX_SM 240 222 223 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER { 224 struct { 225 NvU16 gpcId; 226 NvU16 localTpcId; 227 NvU16 localSmId; 228 NvU16 globalTpcId; 229 NvU16 virtualGpcId; 230 NvU16 migratableTpcId; 231 } globalSmId[NV2080_CTRL_INTERNAL_GR_MAX_SM]; 232 233 NvU16 numSm; 234 NvU16 numTpc; 235 } NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER; 236 237 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x23U) 238 239 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS { 240 NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER globalSmOrder[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 241 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS; 242 243 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER (0x20800a22) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID" */ 244 245 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x22U) 246 247 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS; 248 249 /*! 250 * BSP Static data. 251 */ 252 253 #define NV2080_CTRL_CMD_INTERNAL_MAX_BSPS 8 254 255 typedef struct NV2080_CTRL_INTERNAL_BSP_CAPS { 256 NvU8 capsTbl[NV0080_CTRL_BSP_CAPS_TBL_SIZE]; 257 } NV2080_CTRL_INTERNAL_BSP_CAPS; 258 259 typedef struct NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS { 260 NV2080_CTRL_INTERNAL_BSP_CAPS caps[NV2080_CTRL_CMD_INTERNAL_MAX_BSPS]; 261 NvBool valid[NV2080_CTRL_CMD_INTERNAL_MAX_BSPS]; 262 } NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS; 263 264 /*! 265 * MSENC Static data. 266 */ 267 268 #define NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS 8 269 270 typedef struct NV2080_CTRL_INTERNAL_MSENC_CAPS { 271 NvU8 capsTbl[NV0080_CTRL_MSENC_CAPS_TBL_SIZE]; 272 } NV2080_CTRL_INTERNAL_MSENC_CAPS; 273 274 typedef struct NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS { 275 NV2080_CTRL_INTERNAL_MSENC_CAPS caps[NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS]; 276 NvBool valid[NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS]; 277 } NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS; 278 279 280 #define NV2080_CTRL_INTERNAL_GR_MAX_GPC 12 281 #define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT 10 282 283 /*! 284 * @ref NV2080_CTRL_CMD_GR_GET_GPC_MASK 285 * @ref NV2080_CTRL_CMD_GR_GET_TPC_MASK 286 * @ref NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK 287 */ 288 289 290 291 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS { 292 NvU32 gpcMask; 293 294 /*! 295 * tpcMask is indexed by logical GPC ID for MIG case 296 * and indexed by physical GPC ID for non-MIG case 297 */ 298 NvU32 tpcMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 299 300 /*! 301 * tpcCount is always indexed by logical GPC ID 302 */ 303 NvU32 tpcCount[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 304 NvU32 physGpcMask; 305 NvU32 mmuPerGpc[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 306 307 NvU32 tpcToPesMap[NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT]; 308 NvU32 numPesPerGpc[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 309 310 /*! 311 * zcullMask is always indexed by physical GPC ID 312 */ 313 NvU32 zcullMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 314 315 NvU32 physGfxGpcMask; 316 NvU32 numGfxTpc; 317 } NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS; 318 319 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID (0x27U) 320 321 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS { 322 /*! 323 * floorsweeping masks which are indexed via local GR index 324 */ 325 NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS floorsweepingMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 326 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS; 327 328 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS (0x20800a26) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID" */ 329 330 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID (0x26U) 331 332 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS; 333 334 /* 335 * NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES 336 * 337 * This command returns physical addresses of specified context buffer. 338 * To obtain addresses of whole buffer firstPage has to be advanced on 339 * subsequent invocations of the control until whole buffer is probed. 340 * If the buffer is contiguous, only single address will be returned by 341 * this control. 342 * 343 * bufferType[IN] 344 * Buffer type as returned by GET_CTX_BUFFER_INFO. 345 * 346 * firstPage[IN] 347 * Index of the first page to return in 'physAddrs' array. 348 * 349 * numPages[OUT] 350 * Number of entries filled in 'physAddrs' array. This will be 0 351 * if firstPage is greater or equal to number of pages managed by 'hBuffer'. 352 * 353 * physAddrs[OUT] 354 * Physical addresses of pages comprising specified buffer. 355 * 356 * bNoMorePages[OUT] 357 * End of buffer reached. Either 'physAddrs' contains last page of the 358 * buffer or 'firstPage' specifies index past the buffer. 359 */ 360 #define NV2080_CTRL_KGR_MAX_BUFFER_PTES 128 361 #define NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES (0x20800a28) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID" */ 362 363 #define NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID (0x28U) 364 365 typedef struct NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS { 366 NvHandle hUserClient; 367 NvHandle hChannel; 368 NvU32 bufferType; 369 NvU32 firstPage; 370 NvU32 numPages; 371 NV_DECLARE_ALIGNED(NvU64 physAddrs[NV2080_CTRL_KGR_MAX_BUFFER_PTES], 8); 372 NvBool bNoMorePages; 373 } NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS; 374 375 /*! 376 * NV2080_CTRL_INTERNAL_MEMDESC_INFO 377 * 378 * A generic container structure representing a memory region to be used as a 379 * component of other control call parameters. 380 * 381 */ 382 typedef struct NV2080_CTRL_INTERNAL_MEMDESC_INFO { 383 NV_DECLARE_ALIGNED(NvU64 base, 8); 384 NV_DECLARE_ALIGNED(NvU64 size, 8); 385 NV_DECLARE_ALIGNED(NvU64 alignment, 8); 386 NvU32 addressSpace; 387 NvU32 cpuCacheAttrib; 388 } NV2080_CTRL_INTERNAL_MEMDESC_INFO; 389 390 /*! 391 * @ref NV0080_CTRL_CMD_GR_GET_INFO 392 * @ref NV0080_CTRL_CMD_GR_GET_INFO_V2 393 * @ref NV2080_CTRL_CMD_GR_GET_INFO 394 * @ref NV2080_CTRL_CMD_GR_GET_INFO_V2 395 */ 396 397 398 399 /*! 400 * @ref NV2080_CTRL_GR_INFO 401 */ 402 typedef struct NV2080_CTRL_INTERNAL_GR_INFO { 403 NvU32 index; 404 NvU32 data; 405 } NV2080_CTRL_INTERNAL_GR_INFO; 406 407 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_INFO { 408 NV2080_CTRL_INTERNAL_GR_INFO infoList[NV0080_CTRL_GR_INFO_MAX_SIZE]; 409 } NV2080_CTRL_INTERNAL_STATIC_GR_INFO; 410 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_MESSAGE_ID (0x2BU) 411 412 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS { 413 NV2080_CTRL_INTERNAL_STATIC_GR_INFO engineInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 414 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS; 415 416 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO (0x20800a2a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID" */ 417 418 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID (0x2AU) 419 420 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS; 421 422 /*! 423 * @ref NV2080_CTRL_CMD_GR_GET_ZCULL_INFO 424 */ 425 426 427 428 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO { 429 NvU32 widthAlignPixels; 430 NvU32 heightAlignPixels; 431 NvU32 pixelSquaresByAliquots; 432 NvU32 aliquotTotal; 433 NvU32 zcullRegionByteMultiplier; 434 NvU32 zcullRegionHeaderSize; 435 NvU32 zcullSubregionHeaderSize; 436 NvU32 subregionCount; 437 NvU32 subregionWidthAlignPixels; 438 NvU32 subregionHeightAlignPixels; 439 } NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO; 440 441 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x2DU) 442 443 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS { 444 NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO engineZcullInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 445 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS; 446 447 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO (0x20800a2c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID" */ 448 449 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x2CU) 450 451 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS; 452 453 /*! 454 * @ref NV2080_CTRL_CMD_GR_GET_ROP_INFO 455 */ 456 457 458 459 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO { 460 NvU32 ropUnitCount; 461 NvU32 ropOperationsFactor; 462 NvU32 ropOperationsCount; 463 } NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO; 464 465 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x2FU) 466 467 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS { 468 NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO engineRopInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 469 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS; 470 471 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO (0x20800a2e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID" */ 472 473 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x2EU) 474 475 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS; 476 477 /*! 478 * @ref NV2080_CTRL_CMD_GR_GET_PPC_MASK 479 */ 480 481 482 483 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS { 484 NvU32 mask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 485 } NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS; 486 487 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_MESSAGE_ID (0x31U) 488 489 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS { 490 NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS enginePpcMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 491 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS; 492 493 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS (0x20800a30) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID" */ 494 495 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID (0x30U) 496 497 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS; 498 499 /*! 500 * @ref NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES 501 * @ref NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE 502 */ 503 504 505 506 #define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT 0x1a 507 508 typedef struct NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO { 509 NvU32 size; 510 NvU32 alignment; 511 } NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO; 512 513 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO { 514 NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO engine[NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT]; 515 } NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO; 516 517 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID (0x33U) 518 519 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS { 520 NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO engineContextBuffersInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 521 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS; 522 523 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID" */ 524 525 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID (0x32U) 526 527 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS; 528 529 /*! 530 * @ref NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER 531 */ 532 533 534 535 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER { 536 NvU8 imla0; 537 NvU8 fmla16; 538 NvU8 dp; 539 NvU8 fmla32; 540 NvU8 ffma; 541 NvU8 imla1; 542 NvU8 imla2; 543 NvU8 imla3; 544 NvU8 imla4; 545 } NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER; 546 547 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x35U) 548 549 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS { 550 NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER smIssueRateModifier[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 551 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS; 552 553 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER (0x20800a34) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID" */ 554 555 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x34U) 556 557 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS; 558 559 /* 560 * NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS 561 * 562 * This command obtains information from physical RM for use by CPU-RM. 563 */ 564 565 #define NV2080_CTRL_CMD_INTERNAL_GPU_GET_CHIP_INFO (0x20800a36) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID" */ 566 567 /* 568 * Maximum number of register bases to return. 569 * These are indexed by NV_REG_BASE_* constants from gpu.h, and this value needs 570 * to be updated if NV_REG_BASE_LAST ever goes over it. See the ct_assert() in gpu.h 571 */ 572 #define NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX 16 573 #define NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID (0x36U) 574 575 typedef struct NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS { 576 NvU8 chipSubRev; 577 NvU32 emulationRev1; 578 NvBool isCmpSku; 579 NvU32 pciDeviceId; 580 NvU32 pciSubDeviceId; 581 NvU32 pciRevisionId; 582 NvU32 regBases[NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX]; 583 } NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS; 584 585 /** 586 * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE 587 * 588 * Set whether or not context switch logging is enabled 589 * 590 * bEnable 591 * Enable/Disable status for context switch logging 592 */ 593 #define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE (0x20800a37) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID" */ 594 595 /** 596 * NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE 597 * 598 * Retrieve whether or not context switch logging is enabled 599 * 600 * bEnable 601 * Enable/Disable status for context switch logging 602 */ 603 #define NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE (0x20800a38) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID" */ 604 605 typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS { 606 NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); 607 NvBool bEnable; 608 } NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS; 609 610 #define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x37U) 611 612 typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS; 613 614 #define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x38U) 615 616 typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS; 617 618 /** 619 * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET 620 * 621 * Set read offset into FECS context switch trace record 622 * 623 * offset 624 * Value indicating number of records by which to offset 625 */ 626 #define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET (0x20800a39) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID" */ 627 628 /** 629 * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET 630 * 631 * Set write offset into FECS context switch trace record 632 * 633 * offset 634 * Value indicating number of records by which to offset 635 */ 636 #define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET (0x20800a3a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID" */ 637 638 /** 639 * NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET 640 * 641 * Get read offset into FECS context switch trace record 642 * 643 * offset 644 * Value indicating number of records by which to offset 645 */ 646 647 #define NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET (0x20800a3b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID" */ 648 649 typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS { 650 NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); 651 NvU32 offset; 652 } NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS; 653 654 #define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x39U) 655 656 typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS; 657 658 #define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID (0x3AU) 659 660 typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS; 661 662 #define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x3BU) 663 664 typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS; 665 666 /** 667 * NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE 668 * 669 * Get size of FECS record 670 * 671 * fecsRecordSize 672 * Size of FECS record 673 */ 674 675 676 677 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE (0x20800a3d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID" */ 678 679 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE { 680 NvU32 fecsRecordSize; 681 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE; 682 683 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3CU) 684 685 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS { 686 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE fecsRecordSize[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 687 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS; 688 689 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3DU) 690 691 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS; 692 693 /** 694 * NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES 695 * 696 * Get HW defines used to extract information from FECS records 697 * 698 * fecsRecordSize 699 * Size of FECS record 700 * 701 * timestampHiTagMask 702 * Mask for high bits of raw timestamp to extract tag 703 * 704 * timestampHiTagShift 705 * Shift for high bits of raw timestamp to extract tag 706 * 707 * timestampVMask 708 * Mask to extract timestamp from raw timestamp 709 * 710 * numLowerBitsZeroShift 711 * Number of bits timestamp is shifted by 712 */ 713 714 715 716 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES { 717 NvU32 fecsRecordSize; 718 NvU32 timestampHiTagMask; 719 NvU8 timestampHiTagShift; 720 NV_DECLARE_ALIGNED(NvU64 timestampVMask, 8); 721 NvU8 numLowerBitsZeroShift; 722 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES; 723 724 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID (0x3EU) 725 726 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS { 727 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES fecsTraceDefines[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES], 8); 728 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS; 729 730 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES (0x20800a3f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID" */ 731 732 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID (0x3FU) 733 734 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS; 735 736 /** 737 * NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE 738 * 739 * Parse the DEVICE_INFO2_TABLE on the physical side and return it to kernel. 740 */ 741 typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO { 742 NvU32 faultId; 743 NvU32 instanceId; 744 NvU32 typeEnum; 745 NvU32 resetId; 746 NvU32 devicePriBase; 747 NvU32 isEngine; 748 NvU32 rlEngId; 749 NvU32 runlistPriBase; 750 NvU32 groupId; 751 NvU32 ginTargetId; 752 NvU32 deviceBroadcastPriBase; 753 } NV2080_CTRL_INTERNAL_DEVICE_INFO; 754 #define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES 256 755 756 #define NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE (0x20800a40) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */ 757 758 #define NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID (0x40U) 759 760 typedef struct NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS { 761 NvU32 numEntries; 762 NV2080_CTRL_INTERNAL_DEVICE_INFO deviceInfoTable[NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES]; 763 } NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS; 764 765 #define NV2080_CTRL_CMD_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP (0x20800a41) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID" */ 766 767 #define NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE 4096 768 #define NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES 4096 769 770 #define NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID (0x41U) 771 772 typedef struct NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS { 773 NvU32 userRegisterAccessMapSize; 774 NvU32 compressedSize; 775 NvU8 compressedData[NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE]; 776 NvU32 profilingRangesSize; 777 NvU8 profilingRanges[NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES]; 778 } NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS; 779 780 /** 781 * Get GR PDB properties synchronized between Kernel and Physical 782 * 783 * bPerSubCtxheaderSupported 784 * @ref PDB_PROP_GR_SUPPORTS_PER_SUBCONTEXT_CONTEXT_HEADER 785 */ 786 787 788 789 typedef struct NV2080_CTRL_INTERNAL_NV_RANGE { 790 NV_DECLARE_ALIGNED(NvU64 lo, 8); 791 NV_DECLARE_ALIGNED(NvU64 hi, 8); 792 } NV2080_CTRL_INTERNAL_NV_RANGE; 793 794 /*! 795 * NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS 796 * 797 * This structure specifies a target swizz-id and mem_range to update 798 * 799 * swizzId[IN] 800 * - Targeted swizz-id for which the memRange is being set 801 * 802 * memAddrRange[IN] 803 * - Memory Range for given GPU instance 804 */ 805 #define NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x43U) 806 807 typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS { 808 NvU32 swizzId; 809 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NV_RANGE memAddrRange, 8); 810 } NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS; 811 812 #define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a44) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */ 813 814 #define NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x44U) 815 816 typedef NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS; 817 818 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a43) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */ 819 820 821 822 #define NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x45U) 823 824 typedef struct NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS { 825 NvBool bTeardown; 826 } NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS; 827 828 #define NV2080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR (0x20800a46) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID" */ 829 #define NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x46U) 830 831 typedef NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS; 832 833 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES { 834 NvBool bPerSubCtxheaderSupported; 835 } NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES; 836 837 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x47U) 838 839 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS { 840 NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES pdbTable[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 841 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS; 842 843 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES (0x20800a48) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID" */ 844 845 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x48U) 846 847 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS; 848 849 /*! 850 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM 851 * 852 * This command writes instance memory information in the display hardware registers. 853 * 854 * instMemPhysAddr 855 * GPU physical address or IOVA address of the display instance memory. 856 * 857 * instMemSize 858 * Size of the display instance memory. 859 * 860 * instMemAddrSpace 861 * Address space of the display instance memory. 862 * 863 * instMemCpuCacheAttr 864 * Cache attribute of the display instance memory. 865 */ 866 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM (0x20800a49) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID" */ 867 868 #define NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID (0x49U) 869 870 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS { 871 NV_DECLARE_ALIGNED(NvU64 instMemPhysAddr, 8); 872 NV_DECLARE_ALIGNED(NvU64 instMemSize, 8); 873 NvU32 instMemAddrSpace; 874 NvU32 instMemCpuCacheAttr; 875 } NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS; 876 877 /* 878 * NV2080_CTRL_INTERNAL_GPU_RECOVER_ALL_COMPUTE_CONTEXTS 879 * 880 * This command issues RC recovery for all compute contexts running on the given GPU. 881 */ 882 #define NV2080_CTRL_CMD_INTERNAL_RECOVER_ALL_COMPUTE_CONTEXTS (0x20800a4a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x4A" */ 883 884 /*! 885 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION 886 * 887 * This command obtains IP version of display engine for use by Kernel RM. 888 * 889 * ipVersion 890 * IP Version of display engine. 891 * 892 * Possible status values returned are: 893 * NV_OK 894 * NV_ERR_NOT_SUPPORTED - DISP has been disabled 895 */ 896 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION (0x20800a4b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID" */ 897 898 #define NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID (0x4BU) 899 900 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS { 901 NvU32 ipVersion; 902 } NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS; 903 904 /*! 905 * NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE 906 * 907 * This command determines the current status of MIG MODE from Physical RM. 908 * 909 * smcMode [OUT] 910 * Current MIG MODE of the GPU. Values range NV2080_CTRL_GPU_INFO_GPU_SMC_MODE* 911 */ 912 #define NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE (0x20800a4c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID" */ 913 914 #define NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID (0x4CU) 915 916 typedef struct NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS { 917 NvU32 smcMode; 918 } NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS; 919 920 /*! 921 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR 922 * 923 * head 924 * This parameter specifies the head for which the callback is to be registered/unregistered. This value must be 925 * less than the maximum number of heads supported by the GPU subdevice. 926 * 927 * rgLineNum 928 * This indicates the RG scanout line number on which the callback will be executed. 929 * 930 * intrLine 931 * Enable: [out] Which interrupt line was allocated for this head. 932 * Disable: [in] Which interrupt line to deallocate. 933 * 934 * bEnable 935 * Should we allocate or deallocate an interrupt line? 936 * 937 * Possible status values returned are: 938 * NV_OK 939 * NV_ERR_GENERIC - There was no available interrupt to allocate. 940 * NV_ERR_INVALID_ARGUMENT 941 */ 942 943 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR (0x20800a4d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID" */ 944 945 #define NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID (0x4DU) 946 947 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS { 948 NvU32 head; 949 NvU32 rgLineNum; 950 NvU32 intrLine; 951 NvBool bEnable; 952 } NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS; 953 954 /*! 955 * NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO 956 * 957 * Description of a supported GPU instance. 958 * 959 * partitionFlag [OUT] 960 * Allocation flag to be used to allocate a partition with this profile. 961 * 962 * grCount [OUT] 963 * # GR engines, including the GFX capable ones. 964 * 965 * gfxGrCount [OUT] 966 * # GR engines capable of Gfx, which is a subset of the GR engines included in grCount 967 * 968 * gpcCount [OUT] 969 * # total gpcs, including the GFX capable ones. 970 * 971 * virtualGpcCount [OUT] 972 * # virtualized gpcs, including the GFX capable ones. 973 * 974 * gfxGpcCount [OUT] 975 * # total gpcs capable of Gfx. This is a subset of the GPCs included in gpcCount. 976 * 977 * veidCount [OUT] 978 * # total veids 979 * 980 * smCount [OUT] 981 * # total SMs 982 * 983 * ceCount [OUT] 984 * # CE engines 985 * 986 * nvEncCount [OUT] 987 * # NVENC engines 988 * 989 * nvDecCount [OUT] 990 * # NVDEC engines 991 * 992 * nvJpgCount [OUT] 993 * # NVJPG engines 994 * 995 * nvOfaCount [OUT] 996 * # NVOFA engines 997 * 998 * validCTSIdMask [OUT] 999 * # mask of CTS IDs which can be assigned under this profile 1000 * 1001 * validGfxCTSIdMask [OUT] 1002 * # mask of CTS IDs that contain Gfx capable Grs which can be assigned under this profile 1003 */ 1004 #define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 60 1005 1006 1007 1008 typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO { 1009 NvU32 partitionFlag; 1010 NvU32 grCount; 1011 NvU32 gfxGrCount; 1012 NvU32 gpcCount; 1013 NvU32 virtualGpcCount; 1014 NvU32 gfxGpcCount; 1015 NvU32 veidCount; 1016 NvU32 smCount; 1017 NvU32 ceCount; 1018 NvU32 nvEncCount; 1019 NvU32 nvDecCount; 1020 NvU32 nvJpgCount; 1021 NvU32 nvOfaCount; 1022 NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8); 1023 NV_DECLARE_ALIGNED(NvU64 validGfxCTSIdMask, 8); 1024 } NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO; 1025 1026 /*! 1027 * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS 1028 * 1029 * Returns the list of supported GPU instance profiles. 1030 * 1031 * count [OUT] 1032 * Number of supported profiles. 1033 * 1034 * table [OUT] 1035 * Supported profiles. 1036 */ 1037 #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID (0x4FU) 1038 1039 typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS { 1040 NvU32 count; 1041 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO table[NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES], 8); 1042 } NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS; 1043 1044 /*! 1045 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM 1046 * 1047 * This command instructs the physical MemorySystem to set up memory partitioning 1048 * exterior boundaries in hardware. 1049 * 1050 * partitionableMemSize [input] 1051 * Size of the partitionable memory in bytes 1052 * 1053 * bottomRsvdSize [input] 1054 * Size of the reserved region below partitionable memory in bytes 1055 * 1056 * topRsvdSize [input] 1057 * Size of the reserved region above partitionable memory in bytes 1058 * 1059 * partitionableStartAddr [output] 1060 * Start address of the partitionable memory, aligned to HW constraints 1061 * 1062 * partitionableEndAddr [output] 1063 * End address of the partitionable memory, aligned to HW constraints 1064 */ 1065 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM (0x20800a51) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID" */ 1066 1067 #define NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID (0x51U) 1068 1069 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS { 1070 NV_DECLARE_ALIGNED(NvU64 partitionableMemSize, 8); 1071 NV_DECLARE_ALIGNED(NvU64 bottomRsvdSize, 8); 1072 NV_DECLARE_ALIGNED(NvU64 topRsvdSize, 8); 1073 NV_DECLARE_ALIGNED(NvU64 partitionableStartAddr, 8); 1074 NV_DECLARE_ALIGNED(NvU64 partitionableEndAddr, 8); 1075 } NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS; 1076 1077 1078 1079 #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE 4 1080 1081 #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x52U) 1082 1083 typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS { 1084 NV_DECLARE_ALIGNED(NvU64 engineMask[NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE], 8); 1085 } NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS; 1086 1087 #define NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS 2 1088 #define NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID 64 1089 /*! 1090 * NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS 1091 * 1092 * Promote a single partition's runlist buffers allocated by kernel Client RM to Physical RM 1093 * 1094 * rlBuffers [IN] 1095 * 2D array of runlist buffers for a single partition 1096 * 1097 * runlistIdMask [IN] 1098 * Mask of runlists belonging to partition 1099 * 1100 */ 1101 #define NV2080_CTRL_CMD_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS (0x20800a53) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID" */ 1102 1103 #define NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID (0x53U) 1104 1105 typedef struct NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS { 1106 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MEMDESC_INFO rlBuffers[NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID][NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS], 8); 1107 NV_DECLARE_ALIGNED(NvU64 runlistIdMask, 8); 1108 NvU32 swizzId; 1109 } NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS; 1110 1111 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_SET_IMP_INIT_INFO (0x20800a54) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID" */ 1112 1113 #define NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID (0x54U) 1114 1115 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS { 1116 TEGRA_IMP_IMPORT_DATA tegraImpImportData; 1117 } NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS; 1118 1119 #define NV2080_CTRL_CMD_INTERNAL_GET_EGPU_BRIDGE_INFO (0x20800a55) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID" */ 1120 1121 #define NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID (0x55U) 1122 1123 typedef struct NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS { 1124 NvU16 pciDeviceId; 1125 NvU16 pciSubDeviceId; 1126 NvBool iseGPUBridge; 1127 NvU8 approvedBusType; 1128 } NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS; 1129 1130 #define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_NONE (0x00000000) 1131 #define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_CUSTOM (0x00000001) 1132 #define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB2 (0x00000002) 1133 #define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB3 (0x00000003) 1134 1135 1136 /*! 1137 * NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR 1138 * 1139 * This command triggers a sysmembar to flush VIDMEM writes. 1140 * This command accepts no parameters. 1141 * 1142 */ 1143 #define NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR (0x20800a70) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x70" */ 1144 1145 /* 1146 * NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL 1147 * 1148 * Setup local PCIE P2P Mailbox 1149 * 1150 * local2Remote[IN] 1151 * Local peer ID of remote gpu on local gpu 1152 * 1153 * remote2Local[IN] 1154 * Remote peer ID of local gpu on remote gpu 1155 * 1156 * localP2PDomainRemoteAddr[IN] 1157 * P2P domain remote address on local gpu 1158 * 1159 * remoteP2PDomainLocalAddr[IN] 1160 * P2P domain local address on remote gpu 1161 * 1162 * remoteWMBoxLocalAddr[IN] 1163 * Local mailbox address on remote gpu 1164 * 1165 * p2pWmbTag[OUT] 1166 * Tag for mailbox to transport from local to remote GPU 1167 * 1168 * bNeedWarBug999673[IN] 1169 * Set to true if WAR for bug 999673 is required 1170 * 1171 * Possible status values returned are: 1172 * NV_OK 1173 * NV_ERR_NOT_SUPPORTED 1174 */ 1175 #define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL (0x20800a71) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID" */ 1176 1177 #define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID (0x71U) 1178 1179 typedef struct NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS { 1180 NvU32 local2Remote; 1181 NvU32 remote2Local; 1182 NV_DECLARE_ALIGNED(NvU64 localP2PDomainRemoteAddr, 8); 1183 NV_DECLARE_ALIGNED(NvU64 remoteP2PDomainLocalAddr, 8); 1184 NV_DECLARE_ALIGNED(NvU64 remoteWMBoxLocalAddr, 8); 1185 NV_DECLARE_ALIGNED(NvU64 p2pWmbTag, 8); 1186 NvBool bNeedWarBug999673; 1187 } NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS; 1188 1189 /* 1190 * NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE 1191 * 1192 * Setup remote PCIE P2P Mailbox 1193 * 1194 * local2Remote[IN] 1195 * Local peer ID of remote gpu on local gpu 1196 * 1197 * remote2Local[IN] 1198 * Remote peer ID of local gpu on remote gpu 1199 * 1200 * localP2PDomainRemoteAddr[IN] 1201 * P2P domain remote address on local gpu 1202 * 1203 * remoteP2PDomainLocalAddr[IN] 1204 * P2P domain local address on remote gpu 1205 * 1206 * remoteWMBoxAddrU64[IN] 1207 * Mailbox address on remote gpu 1208 * 1209 * p2pWmbTag[IN] 1210 * Tag for mailbox to transport from local to remote GPU 1211 * 1212 * Possible status values returned are: 1213 * NV_OK 1214 * NV_ERR_NOT_SUPPORTED 1215 */ 1216 #define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE (0x20800a72) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID" */ 1217 1218 #define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID (0x72U) 1219 1220 typedef struct NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS { 1221 NvU32 local2Remote; 1222 NvU32 remote2Local; 1223 NV_DECLARE_ALIGNED(NvU64 localP2PDomainRemoteAddr, 8); 1224 NV_DECLARE_ALIGNED(NvU64 remoteP2PDomainLocalAddr, 8); 1225 NV_DECLARE_ALIGNED(NvU64 remoteWMBoxAddrU64, 8); 1226 NV_DECLARE_ALIGNED(NvU64 p2pWmbTag, 8); 1227 } NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS; 1228 1229 /* 1230 * NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX 1231 * 1232 * Destroy PCIE P2P Mailbox 1233 * 1234 * peerIdx[IN] 1235 * Peer ID of the P2P destination GPU 1236 * 1237 * bNeedWarBug999673[IN] 1238 * Set to true if WAR for bug 999673 is required 1239 * 1240 * Possible status values returned are: 1241 * NV_OK 1242 * NV_ERR_NOT_SUPPORTED 1243 */ 1244 #define NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX (0x20800a73) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID" */ 1245 1246 #define NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID (0x73U) 1247 1248 typedef struct NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS { 1249 NvU32 peerIdx; 1250 NvBool bNeedWarBug999673; 1251 } NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS; 1252 1253 /* 1254 * NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING 1255 * 1256 * Create C2C mapping to a given peer GPU 1257 * 1258 * peerId[IN] 1259 * Peer ID for local to remote GPU 1260 * 1261 * Possible status values returned are: 1262 * NV_OK 1263 * NV_ERR_NOT_SUPPORTED 1264 */ 1265 #define NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING (0x20800a74) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID" */ 1266 1267 #define NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID (0x74U) 1268 1269 typedef struct NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS { 1270 NvU32 peerId; 1271 } NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS; 1272 1273 /* 1274 * NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING 1275 * 1276 * Remove C2C mapping to a given peer GPU 1277 * 1278 * peerId[IN] 1279 * Peer ID for local to remote GPU 1280 * 1281 * Possible status values returned are: 1282 * NV_OK 1283 * NV_ERR_NOT_SUPPORTED 1284 */ 1285 #define NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING (0x20800a75) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID" */ 1286 1287 #define NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID (0x75U) 1288 1289 typedef struct NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS { 1290 NvU32 peerId; 1291 } NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS; 1292 1293 /*! 1294 * NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES 1295 * 1296 * Retrieves the corresponding SPAs (per the given GFID's VMMU mappings) 1297 * for the given array of GPAs. 1298 * 1299 * gfid [IN] 1300 * GFID to translate GPAs for 1301 * 1302 * numEntries [IN] 1303 * Number of entries (<= NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES) 1304 * to translate (i.e. number of elements in gpaEntries) 1305 * 1306 * gpaEntries [IN] 1307 * Array of GPAs to translate 1308 * 1309 * spaEntries [OUT] 1310 * Resulting array of SPAs 1311 */ 1312 #define NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES (0x20800a57) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID" */ 1313 1314 #define NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES 128 1315 1316 #define NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID (0x57U) 1317 1318 typedef struct NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS { 1319 NvU32 gfid; 1320 NvU32 numEntries; 1321 NV_DECLARE_ALIGNED(NvU64 gpaEntries[NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES], 8); 1322 NV_DECLARE_ALIGNED(NvU64 spaEntries[NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES], 8); 1323 } NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS; 1324 1325 /*! 1326 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER 1327 * 1328 * Pass required pushbuffer parameters from kernel RM to Physical RM 1329 * 1330 * addressSpace [IN] 1331 * Address space of pushbuffer whtether it is ADDR_SYSMEM or ADDR_FBMEM 1332 * 1333 * physicalAddr [IN] 1334 * Physical address of pushbuffer 1335 * 1336 * addressSpace [IN] 1337 * Limit of the pushbuffer address, it should be less than 4K 1338 * 1339 * cacheSnoop [IN] 1340 * Cachesnoop supported or not 1341 * 1342 * channelInstance [IN] 1343 * Channel instance pass by the client to get corresponding dispchannel 1344 * 1345 * hclass [IN] 1346 * External class ID pass by the client to get the channel class 1347 * 1348 * valid [IN] 1349 * This bit indicates whether pushbuffer parameters are valid or not 1350 * 1351 * pbTargetAperture [IN] 1352 * Indicates the PushBuffer Target Aperture type (IOVA, PCI, PCI_COHERENT or NVM) 1353 * 1354 */ 1355 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER (0x20800a58) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID" */ 1356 1357 #define NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID (0x58U) 1358 1359 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS { 1360 NvU32 addressSpace; 1361 NV_DECLARE_ALIGNED(NvU64 physicalAddr, 8); 1362 NV_DECLARE_ALIGNED(NvU64 limit, 8); 1363 NvU32 cacheSnoop; 1364 NvU32 hclass; 1365 NvU32 channelInstance; 1366 NvBool valid; 1367 NvU32 pbTargetAperture; 1368 } NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS; 1369 1370 /*! 1371 * NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO 1372 * 1373 * This command obtains information from physical RM for use by CPU-RM. 1374 * 1375 * replayableFaultBufferSize 1376 * Default size of replayable fault buffer 1377 * 1378 * nonReplayableFaultBufferSize 1379 * Default size of non-replayable fault buffer 1380 * 1381 */ 1382 1383 #define NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO (0x20800a59) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ 1384 1385 #define NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0x59U) 1386 1387 typedef struct NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS { 1388 NvU32 replayableFaultBufferSize; 1389 NvU32 replayableShadowFaultBufferMetadataSize; 1390 NvU32 nonReplayableFaultBufferSize; 1391 NvU32 nonReplayableShadowFaultBufferMetadataSize; 1392 } NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS; 1393 1394 /*! 1395 * @ref NV2080_CTRL_CMD_GR_GET_CTXSW_MODES 1396 */ 1397 #define NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES (0x20800a5a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID" */ 1398 1399 #define NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID (0x5AU) 1400 1401 typedef NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS; 1402 1403 /*! 1404 * NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE 1405 * 1406 * Get heap reservation size needed by different module 1407 */ 1408 #define NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE (0x20800a5b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID" */ 1409 1410 #define NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID (0x5BU) 1411 1412 typedef struct NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS { 1413 NvU32 moduleIndex; 1414 NvU32 size; 1415 } NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS; 1416 1417 /*! 1418 * NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE 1419 * 1420 * tableLen [OUT] 1421 * Number of valid records in table field. 1422 * 1423 * table [OUT] 1424 * Interrupt table for Kernel RM. 1425 * 1426 * subtreeMap [OUT] 1427 * Subtree range for each NV2080_INTR_CATEGORY. 1428 */ 1429 #define NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE (0x20800a5c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID" */ 1430 1431 #define NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE 128 1432 1433 /*! 1434 * Categories of interrupts. 1435 * 1436 * Each of these categories get a separate range of interrupt subtrees (top 1437 * level bits). 1438 */ 1439 typedef enum NV2080_INTR_CATEGORY { 1440 NV2080_INTR_CATEGORY_DEFAULT = 0, 1441 NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = 1, 1442 NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = 2, 1443 NV2080_INTR_CATEGORY_RUNLIST = 3, 1444 NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = 4, 1445 NV2080_INTR_CATEGORY_UVM_OWNED = 5, 1446 NV2080_INTR_CATEGORY_UVM_SHARED = 6, 1447 NV2080_INTR_CATEGORY_ENUM_COUNT = 7, 1448 } NV2080_INTR_CATEGORY; 1449 1450 #define NV2080_INTR_INVALID_SUBTREE NV_U8_MAX 1451 1452 typedef struct NV2080_INTR_CATEGORY_SUBTREE_MAP { 1453 NvU8 subtreeStart; 1454 NvU8 subtreeEnd; 1455 } NV2080_INTR_CATEGORY_SUBTREE_MAP; 1456 1457 typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY { 1458 NvU16 engineIdx; 1459 NvU32 pmcIntrMask; 1460 NvU32 vectorStall; 1461 NvU32 vectorNonStall; 1462 } NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY; 1463 1464 #define NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID (0x5CU) 1465 1466 typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS { 1467 NvU32 tableLen; 1468 NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY table[NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE]; 1469 NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT]; 1470 } NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS; 1471 1472 /* Index to retrieve the needed heap space for specific module */ 1473 #define NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_GR (0x00000000) 1474 1475 /* 1476 * NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK 1477 * 1478 * Checking if the reservation / release of the PERFMON HW is possible 1479 * 1480 * bReservation [IN] 1481 * NV_TRUE -> request for reservation, NV_FALSE -> request for release 1482 * 1483 */ 1484 #define NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK (0x20800a98) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID" */ 1485 1486 1487 #define NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID (0x98U) 1488 1489 typedef struct NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS { 1490 NvBool bReservation; 1491 } NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS; 1492 1493 /*! 1494 * NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET 1495 * 1496 * Reserving / Releasing PERFMON HW 1497 * 1498 * bReservation [IN] 1499 * NV_TRUE -> request for reservation, NV_FALSE -> request for release 1500 * 1501 * bClientHandlesGrGating [IN] 1502 * DM-TODO: Add comment for this 1503 * 1504 * bRmHandlesIdleSlow [IN] 1505 * If the IDLE slowdown is required 1506 * 1507 */ 1508 #define NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET (0x20800a99) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID" */ 1509 1510 #define NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID (0x99U) 1511 1512 typedef struct NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS { 1513 NvBool bReservation; 1514 NvBool bClientHandlesGrGating; 1515 NvBool bRmHandlesIdleSlow; 1516 } NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS; 1517 1518 /*! 1519 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES 1520 * 1521 * Get active display devices 1522 * 1523 * displayMask [OUT] 1524 * Get the mask of the active display devices in VBIOS 1525 * 1526 * numHeads [OUT] 1527 * Number of heads display supported. 1528 * 1529 */ 1530 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES (0x20800a5d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID" */ 1531 1532 #define NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID (0x5DU) 1533 1534 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS { 1535 1536 NvU32 displayMask; 1537 NvU32 numHeads; 1538 } NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS; 1539 1540 1541 1542 /* 1543 * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES 1544 * 1545 * Get FB Mem page ranges for all possible swizzIds 1546 * 1547 * fbMemPageRanges [OUT] 1548 * Mem page ranges for each swizzId in the form of {lo, hi} 1549 */ 1550 #define NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a60) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID" */ 1551 1552 #define NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID 15 1553 1554 #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x60U) 1555 1556 typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS { 1557 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NV_RANGE fbMemPageRanges[NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID], 8); 1558 } NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS; 1559 1560 /*! 1561 * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS 1562 * 1563 * This command is an internal command sent from Kernel RM to Physical RM 1564 * to get number of channels for a given runlist ID 1565 * 1566 * runlistId [IN] 1567 * numChannels [OUT] 1568 */ 1569 #define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS (0x20800a61) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID" */ 1570 1571 #define NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID (0x61U) 1572 1573 typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS { 1574 NvU32 runlistId; 1575 NvU32 numChannels; 1576 } NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS; 1577 1578 /*! 1579 * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES 1580 * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PROFILES 1581 */ 1582 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES (0x20800a63) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID" */ 1583 1584 #define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID (0x63U) 1585 1586 typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS; 1587 1588 /*! 1589 * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES 1590 * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES 1591 */ 1592 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES (0x20800a65) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID" */ 1593 1594 #define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x65U) 1595 1596 typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS; 1597 1598 /*! 1599 * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES 1600 * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES 1601 */ 1602 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a66) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID" */ 1603 1604 #define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x66U) 1605 1606 typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS; 1607 1608 /*! 1609 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG 1610 * NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG 1611 * 1612 * This command retrieves memory config from HW 1613 * 1614 * memBoundaryCfgA [OUT] 1615 * Memory boundary config A (4KB aligned) 1616 * 1617 * memBoundaryCfgB [OUT] 1618 * Memory boundary config B (4KB aligned) 1619 * 1620 * memBoundaryCfgC [OUT] 1621 * Memory boundary config C (64KB aligned) 1622 * 1623 * memBoundaryCfg [OUT] 1624 * Memory boundary config (64KB aligned) 1625 * 1626 * memBoundaryCfgValInit [OUT] 1627 * Memory boundary config initial value (64KB aligned) 1628 */ 1629 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a68) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID" */ 1630 1631 #define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID (0x68U) 1632 1633 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS { 1634 NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgA, 8); 1635 NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgB, 8); 1636 NvU32 memBoundaryCfgC; 1637 NvU32 memBoundaryCfg; 1638 NvU32 memBoundaryCfgValInit; 1639 } NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS; 1640 1641 #define NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a67) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID" */ 1642 1643 #define NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID (0x67U) 1644 1645 typedef NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS; 1646 1647 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE (0x20800a6b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID" */ 1648 1649 #define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE 8 1650 1651 #define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID (0x6BU) 1652 1653 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS { 1654 NvU32 data[NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE]; 1655 } NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS; 1656 1657 /*! 1658 * NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT 1659 * 1660 * Invoke RC recovery after watchdog timeout is hit. 1661 */ 1662 #define NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT (0x20800a6a) /* finn: Evaluated from "((FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6a)" */ 1663 1664 /* ! 1665 * This command disables cuda limit activation at teardown of the client. 1666 */ 1667 #define NV2080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE (0x20800a7a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7A" */ 1668 1669 /* 1670 * This command is cleaning up OPTP when a client is found to have 1671 * been terminated unexpectedly. 1672 */ 1673 #define NV2080_CTRL_CMD_INTERNAL_PERF_OPTP_CLI_CLEAR (0x20800a7c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7C" */ 1674 1675 /* ! 1676 * This command is used to get the current AUX power state of the sub-device. 1677 */ 1678 #define NV2080_CTRL_CMD_INTERNAL_PERF_GET_AUX_POWER_STATE (0x20800a81) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID" */ 1679 1680 #define NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID (0x81U) 1681 1682 typedef struct NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS { 1683 NvU32 powerState; 1684 } NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS; 1685 1686 /*! 1687 * This command can be used to boost P-State up one level or to the highest for a limited 1688 * duration for the associated subdevice. Boosts from different clients are being tracked 1689 * independently. Note that there are other factors that can limit P-States so the resulting 1690 * P-State may differ from expectation. 1691 * 1692 * flags 1693 * This parameter specifies the actual command. _CLEAR is to clear existing boost. 1694 * _BOOST_1LEVEL is to boost P-State one level higher. _BOOST_TO_MAX is to boost 1695 * to the highest P-State. 1696 * duration 1697 * This parameter specifies the duration of the boost in seconds. This has to be less 1698 * than NV2080_CTRL_PERF_BOOST_DURATION_MAX. 1699 * 1700 * Possible status values returned are: 1701 * NV_OK 1702 * NV_ERR_INVALID_PARAM_STRUCT 1703 * NV_ERR_INVALID_ARGUMENT 1704 */ 1705 #define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_2X (0x20800a9a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID" */ 1706 1707 #define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID (0x9AU) 1708 1709 typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X { 1710 1711 NvBool flags; 1712 NvU32 duration; 1713 } NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X; 1714 1715 #define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_PSTATE 0U 1716 #define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK 1U 1717 #define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK 1718 #define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM (0x2U) /* finn: Evaluated from "NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST + 1" */ 1719 1720 /*! 1721 * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL 1722 * 1723 * Activate/Deactivate GPU Boost Sync algorithm 1724 * 1725 * bActivate [IN] 1726 * GPU Boost Sync algorithm: 1727 * NV_TRUE -> activate 1728 * NV_FALSE -> deactivate 1729 * 1730 */ 1731 #define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL (0x20800a7e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID" */ 1732 1733 #define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID (0x7EU) 1734 1735 typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS { 1736 NvBool bActivate; 1737 } NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS; 1738 1739 /*! 1740 * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS 1741 * 1742 * Apply given limits to a specific subdevice 1743 * 1744 * flags [IN] 1745 * DM-TODO: write description here 1746 * 1747 * bBridgeless [IN] 1748 * Bridgeless information, for now supporting only MIO bridges 1749 * 1750 * currLimits 1751 * Array of limits that will be applied 1752 * 1753 */ 1754 #define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS (0x20800a7f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID" */ 1755 1756 #define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID (0x7FU) 1757 1758 typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS { 1759 NvU32 flags; 1760 NvBool bBridgeless; 1761 NvU32 currLimits[NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM]; 1762 } NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS; 1763 1764 /*! 1765 * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO 1766 * 1767 * Data for GPU Boost Sync structure initialization 1768 * 1769 * hysteresisus [OUT] 1770 * Hysteresis value for GPU Boost synchronization hysteresis algorithm. 1771 * 1772 * bHystersisEnable [OUT] 1773 * hysteresis algorithm for SLI GPU Boost synchronization: 1774 * NV_TRUE -> enabled, 1775 * NV_FALSE -> disabled 1776 * 1777 * bSliGpuBoostSyncEnable [OUT] 1778 * SLI GPU Boost feature is: 1779 * NV_TRUE -> enabled, 1780 * NV_FALSE -> disabled 1781 * 1782 */ 1783 #define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO (0x20800a80) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID" */ 1784 1785 #define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID (0x80U) 1786 1787 typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS { 1788 NV_DECLARE_ALIGNED(NvU64 hysteresisus, 8); 1789 NvBool bHystersisEnable; 1790 NvBool bSliGpuBoostSyncEnable; 1791 } NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS; 1792 1793 /* 1794 * NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER 1795 * 1796 * This command sends replayable fault buffer pages allocated by CPU-RM 1797 * to be setup and enabled in physical RM. 1798 * 1799 * hClient 1800 * Client handle. 1801 * 1802 * hObject 1803 * Object handle. 1804 * 1805 * faultBufferSize 1806 * Size of the replayable fault buffer to register. 1807 * 1808 * faultBufferPteArray 1809 * Pages of replayable fault buffer. 1810 * 1811 * Possible status values returned are: 1812 * NV_OK 1813 */ 1814 #define NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER (0x20800a9b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ 1815 1816 #define NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES 256 1817 #define NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9BU) 1818 1819 typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS { 1820 NvHandle hClient; 1821 NvHandle hObject; 1822 NvU32 faultBufferSize; 1823 NV_DECLARE_ALIGNED(NvU64 faultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES], 8); 1824 } NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS; 1825 1826 /* 1827 * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER 1828 * 1829 * This command requests physical RM to disable the replayable fault buffer. 1830 * 1831 * Possible status values returned are: 1832 * NV_OK 1833 */ 1834 #define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER (0x20800a9c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x9C" */ 1835 1836 // Valid fault buffer types 1837 #define NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE (0x00000000) 1838 #define NV2080_CTRL_FAULT_BUFFER_REPLAYABLE (0x00000001) 1839 1840 /* 1841 * NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER 1842 * 1843 * This command sends client shadow fault buffer pages allocated by CPU-RM 1844 * to be setup and enabled in physical RM. 1845 * 1846 * shadowFaultBufferQueuePhysAddr 1847 * Physical address of shadow fault buffer queue. 1848 * 1849 * faultBufferSize 1850 * Size of the client shadow fault buffer to register. 1851 * 1852 * shadowFaultBufferPteArray 1853 * Pages of client shadow fault buffer. 1854 * 1855 * shadowFaultBufferType 1856 * Replayable or non-replayable fault buffer 1857 * 1858 * faultBufferSharedMemoryPhysAddr 1859 * Fault buffer shared memory address. Used only by the Replayable fault buffer. 1860 * 1861 * Possible status values returned are: 1862 * NV_OK 1863 */ 1864 #define NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ 1865 1866 #define NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES 3000 1867 #define NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9DU) 1868 1869 typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS { 1870 NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferQueuePhysAddr, 8); 1871 NvU32 shadowFaultBufferSize; 1872 NvU32 shadowFaultBufferMetadataSize; 1873 NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES], 8); 1874 NvU32 shadowFaultBufferType; 1875 NV_DECLARE_ALIGNED(NvU64 faultBufferSharedMemoryPhysAddr, 8); 1876 } NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS; 1877 1878 /* 1879 * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER 1880 * 1881 * This command requests physical RM to disable the client shadow fault buffer. 1882 * 1883 * shadowFaultBufferType 1884 * Replayable or non-replayable fault buffer 1885 * 1886 * Possible status values returned are: 1887 * NV_OK 1888 */ 1889 #define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ 1890 1891 #define NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9EU) 1892 1893 typedef struct NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS { 1894 NvU32 shadowFaultBufferType; 1895 } NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS; 1896 1897 /* 1898 * NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER 1899 * 1900 * Pin PDEs for Global VA range on the server RM and then mirror the client's page 1901 * directory/tables in the server. 1902 * 1903 * Possible status values returned are: 1904 * NV_OK 1905 */ 1906 #define NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER (0x20800a9f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID" */ 1907 1908 #define NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID (0x9FU) 1909 1910 typedef struct NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS { 1911 NV_DECLARE_ALIGNED(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS PdeCopyParams, 8); 1912 } NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS; 1913 1914 /*! 1915 * NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X 1916 * 1917 * This command can be used to boost P-State the highest for a limited 1918 * duration for the associated subdevice. Boosts from different clients are being tracked 1919 * independently. Note that there are other factors that can limit P-States so the resulting 1920 * P-State may differ from expectation. 1921 * 1922 * flags [IN] 1923 * This parameter specifies the actual command. _CLEAR is to clear existing boost. 1924 * and _BOOST_TO_MAX is to boost to the highest P-State. 1925 * 1926 * boostDuration [IN] 1927 * This parameter specifies the duration of the boost in seconds. This has to be less 1928 * than NV2080_CTRL_PERF_BOOST_DURATION_MAX. 1929 * 1930 * gfId [IN] 1931 * This specifies Id of the Kernel RM that is requesting the Boost 1932 * 1933 * bOverrideInfinite[IN] 1934 * This parameter specifies if we want to override already registered infinite boost for the specific Kernel RM. 1935 * This should be NV_TRUE only in case when we are removing the current infinite boost for a specific Kernel RM 1936 * and setting the boost duration to a next maximum duration registered for the Kernel RM in question. 1937 * 1938 * Possible status values returned are: 1939 * NV_OK 1940 * NV_ERR_INVALID_PARAM_STRUCT 1941 * NV_ERR_INVALID_ARGUMENT 1942 */ 1943 #define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X (0x20800aa0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID" */ 1944 1945 #define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID (0xA0U) 1946 1947 typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X { 1948 NvU32 flags; 1949 NvU32 boostDuration; 1950 NvU32 gfId; 1951 NvBool bOverrideInfinite; 1952 } NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X; 1953 1954 /*! 1955 * NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X 1956 * 1957 * Clear the boost for specific Kernel RM 1958 * 1959 * bIsCudaClient [IN] 1960 * Specifies if the request is for clearing the CUDA boost or regular boost 1961 * NV_TRUE -> CUDA boost, NV_FALSE otherwise 1962 * 1963 * gfId [IN] 1964 * Specifies Id of the Kernel RM that is requesting Boost clear 1965 * 1966 */ 1967 #define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X (0x20800aa1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID" */ 1968 1969 #define NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID (0xA1U) 1970 1971 typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X { 1972 1973 NvBool bIsCudaClient; 1974 NvU32 gfId; 1975 } NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X; 1976 1977 /* 1978 * NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO 1979 * 1980 * Retrieves skyline information about the GPU. Params are sized to currently known max 1981 * values, but will need to be modified in the future should that change. 1982 */ 1983 #define NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO (0x20800aa2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID" */ 1984 1985 #define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES 8 1986 #define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS 12 1987 /*! 1988 * NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO 1989 * skylineVgpcSize[OUT] 1990 * - TPC count of non-singleton VGPCs 1991 * singletonVgpcMask[OUT] 1992 * - Mask of active Singletons 1993 * maxInstances[OUT] 1994 * - Max allowed instances of this skyline concurrently on a GPU 1995 * computeSizeFlag 1996 * - One of NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* flags which is associated with this skyline 1997 * numNonSingletonVgpcs 1998 * - Number of VGPCs with non-zero TPC counts which are not singletons 1999 */ 2000 typedef struct NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO { 2001 NvU8 skylineVgpcSize[NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS]; 2002 NvU32 singletonVgpcMask; 2003 NvU32 maxInstances; 2004 NvU32 computeSizeFlag; 2005 NvU32 numNonSingletonVgpcs; 2006 } NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO; 2007 2008 /*! 2009 * NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS 2010 * skylineTable[OUT] 2011 * - TPC count of non-singleton VGPCs 2012 * - Mask of singleton vGPC IDs active 2013 * - Max Instances of this skyline possible concurrently 2014 * - Associated compute size with the indexed skyline 2015 * - Number of VGPCs with non-zero TPC counts which are not singletons 2016 * validEntries[OUT] 2017 * - Number of entries which contain valid info in skylineInfo 2018 */ 2019 #define NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID (0xA2U) 2020 2021 typedef struct NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS { 2022 NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO skylineTable[NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES]; 2023 NvU32 validEntries; 2024 } NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS; 2025 2026 /*! 2027 * @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE 2028 */ 2029 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE (0x20800aa3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID" */ 2030 2031 #define NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID (0xA3U) 2032 2033 typedef NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS; 2034 2035 /*! 2036 * @ref NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION 2037 */ 2038 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE (0x20800aa4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ 2039 2040 #define NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA4U) 2041 2042 typedef NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS; 2043 2044 /*! 2045 * @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONS 2046 */ 2047 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES (0x20800aa5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID" */ 2048 2049 #define NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID (0xA5U) 2050 2051 typedef NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS; 2052 2053 /*! 2054 * @ref NV2080_CTRL_CMD_GPU_GET_PARTITIONS 2055 */ 2056 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES (0x20800aa6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID" */ 2057 2058 #define NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID (0xA6U) 2059 2060 typedef NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS; 2061 2062 /*! 2063 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED 2064 * 2065 * Tell Physical RM whether any ZBC-kind surfaces are allocated. 2066 * If PF and all VFs report false, ZBC table can be flushed by Physical RM. 2067 * 2068 * bZbcReferenced [IN] 2069 * NV_TRUE -> ZBC-kind (and no _SKIP_ZBCREFCOUNT flag) are allocated in Kernel RM 2070 * 2071 */ 2072 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED (0x20800a69) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID" */ 2073 2074 #define NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID (0x69U) 2075 2076 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS { 2077 NvBool bZbcSurfacesExist; 2078 } NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS; 2079 2080 /*! 2081 * NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE 2082 * 2083 * Export the resource and placement information about a gpu instance such that a 2084 * similar gpu instance can be recreated from scratch in the same position on the 2085 * same or similar GPU. Note that different GPUs may have different physical 2086 * resources due to floorsweeping, and an imported gpu instance is not guaranteed 2087 * to get the exact same resources as the exported gpu instance, but the imported 2088 * gpu instance should behave identically with respect to fragmentation and 2089 * placement / span positioning. 2090 */ 2091 #define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE (0x20800aa7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ 2092 2093 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE (0x20800aa8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ 2094 2095 /*! 2096 * NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE 2097 * 2098 * Create a gpu instance resembling the exported instance info. Note that 2099 * different GPUs may have different physical resources due to floorsweeping, 2100 * and an imported gpu instance is not guaranteed to get the exact same resources 2101 * as the exported gpu instance, but the imported gpu instance should behave 2102 * identically with respect to fragmentation and placement / span positioning. 2103 */ 2104 #define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE (0x20800aa9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ 2105 2106 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE (0x20800aaa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ 2107 2108 #define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE 4 2109 typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO { 2110 NV_DECLARE_ALIGNED(NvU64 enginesMask[NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE], 8); 2111 NvU32 partitionFlags; 2112 NvU32 gpcMask; 2113 NvU32 virtualGpcCount; 2114 NvU32 veidOffset; 2115 NvU32 veidCount; 2116 } NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO; 2117 2118 typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS { 2119 NvU32 swizzId; 2120 NvU8 uuid[NV_GI_UUID_LEN]; 2121 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO info, 8); 2122 } NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS; 2123 2124 #define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA7U) 2125 2126 typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS; 2127 2128 #define NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA8U) 2129 2130 typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS; 2131 2132 #define NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA9U) 2133 2134 typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS; 2135 2136 #define NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xAAU) 2137 2138 typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS; 2139 2140 /*! 2141 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT 2142 * 2143 * Invalidate and/or evict the L2 cache 2144 * 2145 * flags [IN] 2146 * flags that specify required actions 2147 * 2148 */ 2149 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT (0x20800a6c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID" */ 2150 2151 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID (0x6cU) 2152 2153 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS { 2154 NvU32 flags; 2155 } NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS; 2156 2157 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL (0x00000001) 2158 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_FIRST (0x00000002) 2159 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_LAST (0x00000004) 2160 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_NORMAL (0x00000008) 2161 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN (0x00000010) 2162 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_WAIT_FB_PULL (0x00000020) 2163 2164 /*! 2165 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES 2166 * 2167 * Flush all L2 Rams and Caches using the ELPG flush 2168 * 2169 */ 2170 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES (0x20800a6d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6D" */ 2171 2172 /*! 2173 * NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO 2174 * 2175 * This command obtains information from physical RM for use by CPU-RM 2176 * 2177 * Data fields -> 2178 * bPcieGen4Capable - tells whether PCIe is Gen4 capable 2179 */ 2180 #define NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO (0x20800aac) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ 2181 2182 #define NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0xacU) 2183 2184 typedef struct NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS { 2185 NvBool bPcieGen4Capable; 2186 NvBool bIsC2CLinkUp; 2187 NvBool bIsDeviceMultiFunction; 2188 NvBool bGcxPmuCfgSpaceRestore; 2189 NV_DECLARE_ALIGNED(NvU64 dmaWindowStartAddress, 8); 2190 } NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS; 2191 2192 /*! 2193 * NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG 2194 * 2195 * Program HSHUB Peer Conn Config space. 2196 * 2197 * programPeerMask[IN] 2198 * If nonzero, the peer mask for programming peers based on hshub connectivity. 2199 * 2200 * invalidatePeerMask[IN] 2201 * If nonzero, the peer mask for invalidating peers. 2202 * 2203 * programPciePeerMask[IN] 2204 * If nonzero, the peer mask for programming peers in pcie case. 2205 * 2206 * Possible status values returned are: 2207 * NV_OK 2208 * NV_WARN_NOTHING_TO_DO 2209 * If all peer masks are zero. 2210 */ 2211 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG (0x20800a88) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID" */ 2212 2213 #define NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID (0x88U) 2214 2215 typedef struct NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS { 2216 NvU32 programPeerMask; 2217 NvU32 invalidatePeerMask; 2218 NvU32 programPciePeerMask; 2219 } NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS; 2220 2221 /*! 2222 * NV2080_CTRL_CMD_INTERNAL_HSHUB_FIRST_LINK_PEER_ID 2223 * 2224 * Given a mask of link ids, find the first with a valid peerId. 2225 * 2226 * linkMask[IN] 2227 * Mask of linkIds to check. 2228 * 2229 * peerId[OUT] 2230 * The peerId for the lowest-index link with a valid peerId, if any. 2231 * If none found, NV2080_CTRLINTERNAL_HSHUB_FIRST_LINK_PEER_ID_INVALID_PEER (return value will still be NV_OK). 2232 * 2233 * Possible status values returned are: 2234 * NV_OK 2235 * 2236 */ 2237 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_FIRST_LINK_PEER_ID (0x20800a89) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS_MESSAGE_ID" */ 2238 2239 #define NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_INVALID_PEER 0xffffffff 2240 2241 #define NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS_MESSAGE_ID (0x89U) 2242 2243 typedef struct NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS { 2244 NvU32 linkMask; 2245 NvU32 peerId; 2246 } NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS; 2247 2248 /*! 2249 * NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS 2250 * 2251 * Get the Hshub Ids connected to the other end of links. 2252 * 2253 * linkMask[IN] 2254 * A mask of link ids to query. 2255 * 2256 * hshubIds[OUT] 2257 * For each set bit in the link mask, the peer Hshub Id. 2258 * 2259 * Possible status values returned are: 2260 * NV_OK 2261 * NV_WARN_NOTHING_TO_DO 2262 * If the mask is zero. 2263 */ 2264 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS (0x20800a8a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID" */ 2265 #define NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE 32 2266 2267 #define NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID (0x8aU) 2268 2269 typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS { 2270 NvU32 linkMask; 2271 NvU8 hshubIds[NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE]; 2272 } NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS; 2273 2274 /*! 2275 * NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS 2276 * 2277 * Return the number of HSHUB units. 2278 * 2279 * numHshubs[OUT] 2280 * 2281 * Possible status values returned are: 2282 * NV_OK 2283 */ 2284 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS (0x20800a8b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID" */ 2285 2286 #define NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID (0x8bU) 2287 2288 typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS { 2289 NvU32 numHshubs; 2290 } NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS; 2291 2292 /*! 2293 * NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID 2294 * 2295 * Return the next hshubId after the given hshubId. 2296 * 2297 * hshubId[IN/OUT] 2298 * 2299 * Possible status values returned are: 2300 * NV_OK 2301 */ 2302 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID (0x20800a8c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID" */ 2303 2304 #define NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID (0x8cU) 2305 2306 typedef struct NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS { 2307 NvU8 hshubId; 2308 } NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS; 2309 2310 /*! 2311 * NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG 2312 * 2313 * Program HSHUB for EGM peer id. 2314 * 2315 * egmPeerId[IN] 2316 * EGM peer id to program in the HSHUB registers. 2317 * 2318 * Possible status values returned are: 2319 * NV_OK 2320 */ 2321 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG (0x20800a8d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID" */ 2322 2323 #define NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID (0x8dU) 2324 2325 typedef struct NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS { 2326 NvU32 egmPeerId; 2327 } NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS; 2328 2329 /* 2330 * NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR 2331 * 2332 * Enable compute peer addressing mode 2333 * This command accepts no parameters. 2334 */ 2335 2336 #define NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR (0x20800aad) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xad" */ 2337 2338 /* 2339 * NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR 2340 * 2341 * Get/Set NVSwitch fabric address for FLA 2342 * 2343 * [In] bGet 2344 * Whether to get or set the NVSwitch fabric address 2345 * [In/Out] addr 2346 * Address that is to be set or retrieved. 2347 */ 2348 #define NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID (0xaeU) 2349 2350 typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS { 2351 NvBool bGet; 2352 NV_DECLARE_ALIGNED(NvU64 addr, 8); 2353 } NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS; 2354 2355 #define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR (0x20800aae) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID" */ 2356 2357 /*! 2358 * NV2080_CTRL_CMD_INTERNAL_BIF_GET_ASPM_L1_FLAGS 2359 * 2360 * This command obtains information from physical RM for use by CPU-RM 2361 * 2362 * Data fields -> 2363 * bCyaMaskL1 2364 * bEnableAspmDtL1 2365 */ 2366 #define NV2080_CTRL_CMD_INTERNAL_BIF_GET_ASPM_L1_FLAGS (0x20800ab0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS_MESSAGE_ID" */ 2367 2368 #define NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS_MESSAGE_ID (0xb0U) 2369 2370 typedef struct NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS { 2371 NvBool bCyaMaskL1; 2372 NvBool bEnableAspmDtL1; 2373 } NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS; 2374 2375 /*! 2376 * NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT 2377 * 2378 * Sets number of VM slots that are active in VGPU's scheduler 2379 * 2380 * maxActiveVGpuVMCount [IN] 2381 * Number of VM slots that are active in vGPU's scheduler. 2382 * 2383 * Possible status values returned are: 2384 * NV_OK 2385 * NV_ERR_OUT_OF_RANGE - Passed value is out of range 2386 * NV_ERR_NO_MEMORY - Out of memory 2387 */ 2388 #define NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT (0x20800ab1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID" */ 2389 2390 /*! 2391 * Maximum value of VM slots that are active in vGPU's scheduler. 2392 */ 2393 #define NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_MAX_ACTIVE_VGPU_VM_COUNT_MAX_VALUE 32 2394 2395 #define NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID (0xB1U) 2396 2397 typedef struct NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS { 2398 NvU8 maxActiveVGpuVMCount; 2399 } NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS; 2400 2401 /*! 2402 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS 2403 * 2404 * Disable all NVLINK FB peers 2405 * 2406 */ 2407 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS (0x20800a6e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6E" */ 2408 2409 /*! 2410 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE 2411 * 2412 * Program GPU in raw / legacy compression mode 2413 * 2414 */ 2415 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE (0x20800a6f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID" */ 2416 2417 #define NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID (0x6fU) 2418 2419 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS { 2420 NvBool bRawMode; 2421 } NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS; 2422 2423 /* 2424 * NV2080_CTRL_CMD_INTERNAL_CCU_GET_SAMPLE_INFO 2425 * 2426 * This command gets the CCU samples Info from physical-RM. 2427 * 2428 * Possible status values returned are: 2429 * NV_OK 2430 * NV_ERR_NOT_SUPPORTED 2431 */ 2432 #define NV2080_CTRL_CMD_INTERNAL_CCU_GET_SAMPLE_INFO (0x20800ab2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xB2" */ 2433 2434 typedef struct NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS { 2435 NvU32 ccuSampleSize; 2436 } NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS; 2437 2438 /* 2439 * NV2080_CTRL_CMD_INTERNAL_CCU_MAP 2440 * 2441 * This command gets the shared buffer memory descriptor from the CPU-RM and maps to it 2442 * in physical-RM. 2443 * 2444 * Possible status values returned are: 2445 * NV_OK 2446 * NV_ERR_INVALID_ARGUMENT 2447 * NV_ERR_INVALID_ADDRESS 2448 */ 2449 #define NV2080_CTRL_CMD_INTERNAL_CCU_MAP (0x20800ab3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID" */ 2450 2451 #define NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX 1 2452 2453 typedef struct NV2080_CTRL_INTERNAL_CCU_MAP_INFO { 2454 NV_DECLARE_ALIGNED(NvU64 phyAddr, 8); 2455 NvU32 shrBufSize; 2456 NvU32 cntBlkSize; 2457 } NV2080_CTRL_INTERNAL_CCU_MAP_INFO; 2458 2459 #define NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID (0xB3U) 2460 2461 typedef struct NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS { 2462 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_CCU_MAP_INFO mapInfo[NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE + NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX], 8); 2463 } NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS; 2464 2465 /* 2466 * NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP 2467 * 2468 * This command unmaps the shared buffer memory mapping in physical-RM 2469 * 2470 * Possible status values returned are: 2471 * NV_OK 2472 */ 2473 #define NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP (0x20800ab4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID" */ 2474 2475 #define NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID (0xB4U) 2476 2477 typedef struct NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS { 2478 NvBool bDevShrBuf; 2479 NvBool bMigShrBuf; 2480 } NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS; 2481 2482 /*! 2483 * NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO 2484 * 2485 * [in] gpuId 2486 * GPU ID. 2487 * [in] gpuInstance 2488 * GPU instance. 2489 * [in] p2pCaps 2490 * Peer to peer capabilities discovered between the GPUs. 2491 * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. 2492 * [in] p2pOptimalReadCEs 2493 * Mask of CEs to use for p2p reads over Nvlink. 2494 * [in] p2pOptimalWriteCEs 2495 * Mask of CEs to use for p2p writes over Nvlink. 2496 * [in] p2pCapsStatus 2497 * Status of all supported p2p capabilities. 2498 * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. 2499 * [in] busPeerId 2500 * Bus peer ID. For an invalid or a non-existent peer this field 2501 * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. 2502 * [in] busEgmPeerId 2503 * Bus EGM peer ID. For an invalid or a non-existent peer this field 2504 * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. 2505 */ 2506 typedef struct NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO { 2507 NvU32 gpuId; 2508 NvU32 gpuInstance; 2509 NvU32 p2pCaps; 2510 NvU32 p2pOptimalReadCEs; 2511 NvU32 p2pOptimalWriteCEs; 2512 NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; 2513 NvU32 busPeerId; 2514 NvU32 busEgmPeerId; 2515 } NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO; 2516 2517 /*! 2518 * NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS 2519 * 2520 * An internal call to propagate the peer to peer capabilities of peer GPUs 2521 * to the Physical RM. These capabilities are to be consumed by the vGPU GSP plugin. 2522 * This control is used to both add and and update the peer to peer capabilities. 2523 * The existing GPU entries will be updated and those which don't exist will be added. 2524 * Use NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS to remove the added entries. 2525 * 2526 * [in] peerGpuCount 2527 * The number of the peerGpuInfos entries. 2528 * [in] peerGpuInfos 2529 * The array of NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS entries, describing 2530 * the peer to peer capabilities of the specified GPUs. 2531 * 2532 * Possible status values returned are: 2533 * NV_OK 2534 * NV_ERR_INVALID_ARGUMENT - Invalid peerGpuCount 2535 * NV_ERR_INSUFFICIENT_RESOURCES - Total GPU count exceeds the maximum value 2536 */ 2537 #define NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS (0x20800ab5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID" */ 2538 2539 #define NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID (0xB5U) 2540 2541 typedef struct NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS { 2542 NvU32 peerGpuCount; 2543 NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO peerGpuInfos[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 2544 } NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS; 2545 2546 /*! 2547 * NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS 2548 * 2549 * An internal call to remove the cached peer to peer capabilities of peer GPUs 2550 * from the Physical RM. 2551 * 2552 * [in] peerGpuIdCount 2553 * The number of the peerGpuIds entries. 2554 * [in] peerGpuIds 2555 * The array of GPU IDs, specifying the GPU for which the entries need to be removed. 2556 * 2557 * Possible status values returned are: 2558 * NV_OK 2559 * NV_ERR_INVALID_ARGUMENT - Invalid peerGpuIdCount 2560 * NV_ERR_OBJECT_NOT_FOUND - Invalid peerGpuIds[] entry 2561 */ 2562 #define NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS (0x20800ab6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID" */ 2563 2564 #define NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID (0xB6U) 2565 2566 typedef struct NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS { 2567 NvU32 peerGpuIdCount; 2568 NvU32 peerGpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 2569 } NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS; 2570 2571 2572 2573 /*! 2574 * NV2080_CTRL_CMD_INTERNAL_BUS_GET_PCIE_P2P_CAPS 2575 * 2576 * This command returns the GPU's PCIE P2P caps 2577 * 2578 * [in] bCommonPciSwitchFound 2579 * All GPUs are under the same PCI switch 2580 * [out] p2pReadCapsStatus 2581 * [out] p2pWriteCapsStatus 2582 * These members returns status of all supported p2p capabilities. Valid 2583 * status values include: 2584 * NV0000_P2P_CAPS_STATUS_OK 2585 * P2P capability is supported. 2586 * NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED 2587 * Chipset doesn't support p2p capability. 2588 * NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED 2589 * GPU doesn't support p2p capability. 2590 * NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED 2591 * IOH topology isn't supported. For e.g. root ports are on different 2592 * IOH. 2593 * NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY 2594 * P2P Capability is disabled by a regkey. 2595 * NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED 2596 * P2P Capability is not supported. 2597 * 2598 * Possible status values returned are: 2599 * NV_OK 2600 * NV_ERR_INVALID_ARGUMENT 2601 * NV_ERR_INVALID_PARAM_STRUCT 2602 */ 2603 #define NV2080_CTRL_CMD_INTERNAL_GET_PCIE_P2P_CAPS (0x20800ab8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID" */ 2604 2605 #define NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID (0xB8U) 2606 2607 typedef struct NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS { 2608 NvBool bCommonPciSwitchFound; 2609 NvU8 p2pReadCapsStatus; 2610 NvU8 p2pWriteCapsStatus; 2611 } NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS; 2612 2613 /*! 2614 * NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO 2615 * 2616 * Enable/disable PCIe Relaxed Ordering. 2617 * 2618 */ 2619 #define NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO (0x20800ab9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID" */ 2620 2621 #define NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID (0xB9U) 2622 2623 typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS { 2624 // Enable/disable PCIe relaxed ordering 2625 NvBool enableRo; 2626 } NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS; 2627 2628 /* 2629 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE 2630 * 2631 * An internal call to invoke the sequence VGA register reads & writes to 2632 * perform save and restore of VGA 2633 * 2634 * [in] bSave 2635 * To indicate whether save or restore needs to be performed. 2636 * [in] bUseVbios 2637 * Primary VGA indication from OS. 2638 * [out] bReturnEarly 2639 * To indicate caller to return after this call. 2640 * 2641 * Possible status values returned are: 2642 * NV_OK 2643 * NV_ERR_INVALID_OPERATION 2644 * NV_ERR_NOT_SUPPORTED 2645 */ 2646 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE (0x20800a76) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */ 2647 2648 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x76U) 2649 2650 typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS { 2651 NvBool bSave; 2652 NvBool bUseVbios; 2653 NvBool bReturnEarly; 2654 } NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS; 2655 2656 /*! 2657 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE 2658 * 2659 * To perform save or restore operation from/to saved fonts. 2660 * 2661 * [in] bSave 2662 * To indicate whether save or restore needs to be performed. 2663 * [in] bUseVbios 2664 * Primary VGA indication from OS. 2665 * [in] bVbiosCallSuccessful 2666 * Indicates if vbios invocation was successful or not. 2667 * 2668 * Possible status values returned are: 2669 * NV_OK 2670 * NV_ERR_NOT_SUPPORTED 2671 */ 2672 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE (0x20800a77) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */ 2673 2674 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x77U) 2675 2676 typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS { 2677 NvBool bSave; 2678 NvBool bUseVbios; 2679 NvBool bVbiosCallSuccessful; 2680 } NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS; 2681 2682 /*! 2683 * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES 2684 * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES 2685 */ 2686 2687 /*! 2688 * NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE 2689 * 2690 * This structure specifies resources in an execution partition 2691 * 2692 * computeSize[OUT] 2693 * - NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* associated with this profile 2694 * 2695 * gfxGpcCount[OUT] 2696 * - Total Number of GFX Supporting GPCs in this partition 2697 * 2698 * gpcCount[OUT] 2699 * - Total Number of GPCs in this partition (including GFX Supported GPCs) 2700 * 2701 * veidCount[OUT] 2702 * - Number of VEIDs allocated to this profile 2703 * 2704 * smCount[OUT] 2705 * - Number of SMs usable in this profile 2706 */ 2707 typedef struct NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE { 2708 NvU8 computeSize; 2709 NvU32 gfxGpcCount; 2710 NvU32 gpcCount; 2711 NvU32 veidCount; 2712 NvU32 smCount; 2713 NvU32 physicalSlots; 2714 } NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE; 2715 2716 /*! 2717 * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS 2718 * 2719 * This structure specifies resources in an execution partition 2720 * 2721 * profileCount[OUT] 2722 * - Total Number of profiles filled 2723 * 2724 * profiles[OUT] 2725 * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles 2726 */ 2727 #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBBU) 2728 2729 typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS { 2730 NvU32 profileCount; 2731 NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE]; 2732 } NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS; 2733 2734 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID" */ 2735 2736 #define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBAU) 2737 2738 typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS; 2739 2740 2741 2742 /* 2743 * NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE 2744 * 2745 * This command sets the ccu stream to enable/disable state. 2746 * 2747 * Possible status values returned are: 2748 * NV_OK 2749 * NV_ERR_INVALID_ARGUMENT 2750 * NV_ERR_NOT_SUPPORTED 2751 */ 2752 2753 #define NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE (0x20800abd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID" */ 2754 2755 #define NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID (0xBDU) 2756 2757 typedef struct NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS { 2758 NvBool bStreamState; 2759 } NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS; 2760 2761 /*! 2762 * NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT 2763 * 2764 * Attach GPU to the external device. 2765 * 2766 * [in] bExtDevFound 2767 * To enable GPIO interrupts. 2768 * 2769 * Possible status values returned are: 2770 * NV_OK 2771 * NV_ERR_GENERIC 2772 * NV_ERR_NOT_SUPPORTED 2773 */ 2774 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT (0x20800abe) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID" */ 2775 2776 #define NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID (0xBEU) 2777 2778 typedef struct NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS { 2779 NvBool bExtDevFound; 2780 } NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS; 2781 2782 /*! 2783 * NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS 2784 * 2785 * Optimize the Gsync timing parameters 2786 * 2787 * [in] timingParameters 2788 * Timing parameters passed by client. 2789 * 2790 * Possible status values returned are: 2791 * NV_OK 2792 * NV_ERR_GENERIC 2793 * NV_ERR_NOT_SUPPORTED 2794 */ 2795 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS (0x20800abf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID" */ 2796 2797 #define NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID (0xBFU) 2798 2799 typedef struct NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS { 2800 NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS timingParameters; 2801 } NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS; 2802 2803 /*! 2804 * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS 2805 * 2806 * Get displayIDs supported by the display. 2807 * 2808 * [out] displayIds 2809 * Associated display ID with head. 2810 * 2811 * Possible status values returned are: 2812 * NV_OK 2813 * NV_ERR_GENERIC 2814 * NV_ERR_NOT_SUPPORTED 2815 */ 2816 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS (0x20800ac0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID" */ 2817 2818 #define NV2080_MAX_NUM_HEADS 4 2819 2820 #define NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID (0xC0U) 2821 2822 typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS { 2823 NvU32 displayIds[NV2080_MAX_NUM_HEADS]; 2824 } NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS; 2825 2826 /*! 2827 * NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC 2828 * 2829 * Set the Stereo sync for Gsync 2830 * 2831 * [in] slave 2832 * Slave GPU head status. 2833 * [in] localSlave 2834 * Slave GPU head status but are not coupled. 2835 * [in] master 2836 * Master GPU head status. 2837 * [in] regstatus 2838 * Register status of status1 register. 2839 * 2840 * Possible status values returned are: 2841 * NV_OK 2842 * NV_ERR_GENERIC 2843 * NV_ERR_NOT_SUPPORTED 2844 */ 2845 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC (0x20800ac1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID" */ 2846 2847 #define NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID (0xC1U) 2848 2849 typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS { 2850 NvU32 slave[NV2080_MAX_NUM_HEADS]; 2851 NvU32 localSlave[NV2080_MAX_NUM_HEADS]; 2852 NvU32 master[NV2080_MAX_NUM_HEADS]; 2853 NvU32 regStatus; 2854 } NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS; 2855 2856 /*! 2857 * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES 2858 * 2859 * Get vertical active lines for given head. 2860 * 2861 * [in] head 2862 * For the headIdx which we need active. 2863 * [out] vActiveLines 2864 * Vertical active lines. 2865 * 2866 * Possible status values returned are: 2867 * NV_OK 2868 * NV_ERR_GENERIC 2869 * NV_ERR_NOT_SUPPORTED 2870 */ 2871 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES (0x20800ac4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID" */ 2872 2873 #define NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID (0xC4U) 2874 2875 typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS { 2876 NvU32 headIdx; 2877 NvU32 vActiveLines; 2878 } NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS; 2879 2880 /*! 2881 * NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID 2882 * 2883 * Verifies if this displayId is valid. 2884 * 2885 * [in] displays 2886 * Displays given by the client 2887 * 2888 * [out] displayId 2889 * DisplayId for the given display 2890 * 2891 * Possible status values returned are: 2892 * NV_OK 2893 * NV_ERR_GENERIC 2894 * NV_ERR_NOT_SUPPORTED 2895 */ 2896 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID (0x20800ac9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID" */ 2897 2898 #define NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID (0xC9U) 2899 2900 typedef struct NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS { 2901 NvU32 displays; 2902 NvU32 displayId; 2903 } NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS; 2904 2905 /*! 2906 * NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC 2907 * 2908 * Disable the raster sync gpio on the other P2060 GPU 2909 * that's connected to master over Video bridge. 2910 * 2911 * [in] bEnableMaster 2912 * If it is master gpu. 2913 * 2914 * [out] bRasterSyncGpioSaved 2915 * If raster sync GPIO direction is saved or not. 2916 * 2917 * [in/out] bRasterSyncGpioDirection 2918 * During save it gets the direction. 2919 * In restores it sets the direction. 2920 * 2921 * Possible status values returned are: 2922 * NV_OK 2923 * NV_ERR_NOT_SUPPORTED 2924 */ 2925 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC (0x20800aca) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID" */ 2926 2927 #define NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID (0xCAU) 2928 2929 typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS { 2930 NvBool bEnableMaster; 2931 NvBool bRasterSyncGpioSaved; 2932 NvU32 bRasterSyncGpioDirection; 2933 } NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS; 2934 2935 /*! 2936 * NV2080_CTRL_CMD_INTERNAL_FBSR_INIT 2937 * 2938 * Initialize FBSR on GSP to prepare for suspend-resume 2939 * 2940 * [in] hClient 2941 * Handle to client of SYSMEM memlist object 2942 * [in] hSysMem 2943 * Handle to SYSMEM memlist object 2944 * [in] bEnteringGcoffState 2945 * Value of PDB_PROP_GPU_GCOFF_STATE_ENTERING 2946 * 2947 * Possible status values returned are: 2948 * NV_OK 2949 * NV_ERR_GENERIC 2950 * NV_ERR_NOT_SUPPORTED 2951 */ 2952 2953 #define NV2080_CTRL_CMD_INTERNAL_FBSR_INIT (0x20800ac2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID" */ 2954 2955 #define NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID (0xC2U) 2956 2957 typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS { 2958 NvHandle hClient; 2959 NvHandle hSysMem; 2960 NvBool bEnteringGcoffState; 2961 } NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS; 2962 2963 /*! 2964 * NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING 2965 * 2966 * Disable all the active channels during suspend 2967 * Resume FIFO scheduling from GSP after resume on Kernel-RM 2968 * 2969 * Possible status values returned are: 2970 * NV_OK 2971 * NV_ERR_NOT_SUPPORTED 2972 */ 2973 2974 #define NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS_MESSAGE_ID" */ 2975 2976 #define NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS_MESSAGE_ID (0xC3U) 2977 2978 typedef struct NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS { 2979 NvBool bDisableActiveChannels; 2980 } NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS; 2981 2982 /* 2983 * NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB 2984 * 2985 * This command is used to get the amount of host reserved FB 2986 * 2987 * hostReservedFb [OUT] 2988 * Amount of FB reserved for the host 2989 * vgpuTypeId [IN] 2990 * The Type ID for VGPU profile 2991 * 2992 * Possible status values returned are: 2993 * NV_OK 2994 * NV_ERR_INVALID_ARGUMENT 2995 */ 2996 #define NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB (0x20800ac5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID" */ 2997 2998 #define NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID (0xC5U) 2999 3000 typedef struct NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS { 3001 NV_DECLARE_ALIGNED(NvU64 hostReservedFb, 8); 3002 NvU32 vgpuTypeId; 3003 } NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS; 3004 3005 /*! 3006 * NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD 3007 * 3008 * This command initiates brightc module state load. 3009 * 3010 * Possible status values returned are: 3011 * NV_OK 3012 * NV_ERR_INVALID_ARGUMENT 3013 * NV_ERR_NOT_SUPPORTED 3014 */ 3015 3016 #define NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD (0x20800ac6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID" */ 3017 3018 #define NV2080_CTRL_ACPI_DSM_READ_SIZE (0x1000) /* finn: Evaluated from "(4 * 1024)" */ 3019 3020 #define NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID (0xC6U) 3021 3022 typedef struct NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS { 3023 NvU32 status; 3024 NvU16 backLightDataSize; 3025 NvU8 backLightData[NV2080_CTRL_ACPI_DSM_READ_SIZE]; 3026 } NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS; 3027 3028 /* 3029 * NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL 3030 * 3031 * Returns number of active links allowed per IOCTRL 3032 * 3033 * [Out] numActiveLinksPerIoctrl 3034 */ 3035 #define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xC7U) 3036 3037 typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS { 3038 NvU32 numActiveLinksPerIoctrl; 3039 } NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS; 3040 #define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL (0x20800ac7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */ 3041 /* 3042 * NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL 3043 * 3044 * Returns number of links per IOCTRL 3045 * 3046 * [Out] numLinksPerIoctrl 3047 */ 3048 #define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xC8U) 3049 3050 typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS { 3051 NvU32 numLinksPerIoctrl; 3052 } NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS; 3053 #define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL (0x20800ac8U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */ 3054 3055 /*! 3056 * NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE 3057 * 3058 * Update the system control capability 3059 * 3060 * bIsSysCtrlSupported [IN] 3061 If the system control is supported 3062 * bIsPlatformLegacy [OUT] 3063 If the platform is legacy 3064 * 3065 * Possible status values returned are: 3066 * NV_OK 3067 * NV_ERR_NOT_SUPPORTED 3068 */ 3069 3070 #define NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE (0x20800acb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID" */ 3071 3072 #define NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID (0xCBU) 3073 3074 typedef struct NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS { 3075 NvBool bIsSysCtrlSupported; 3076 NvBool bIsPlatformLegacy; 3077 } NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS; 3078 3079 /*! 3080 * Macros for PFM_REQ_HNDLR_STATE_SYNC data types. 3081 */ 3082 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_PMGR 0x00U 3083 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_THERM 0x01U 3084 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI 0x02U 3085 3086 /*! 3087 * Structure representing static data for a PFM_REQ_HNDLR_STATE_SYNC_SMBPBI. 3088 */ 3089 typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI { 3090 /*! 3091 * PFM sensor ID 3092 */ 3093 NvU32 sensorId; 3094 3095 /*! 3096 * PFM sensor limit value if required 3097 */ 3098 NvU32 limit; 3099 } NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI; 3100 3101 /*! 3102 * Structure of static information describing PFM_REQ_HNDLR_STATE_SYNC data types. 3103 */ 3104 typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA { 3105 /*! 3106 * @ref NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_<xyz> 3107 */ 3108 NvU8 type; 3109 3110 /*! 3111 * Type-specific information. 3112 */ 3113 union { 3114 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI smbpbi; 3115 } data; 3116 } NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA; 3117 3118 /*! 3119 * Macros for PFM_REQ_HNDLR_STATE_SYNC flags for specific operation. 3120 */ 3121 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_PMGR_LOAD 0x00U 3122 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_THERM_INIT 0x01U 3123 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_CLEAR 0x02U 3124 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_SET 0x03U 3125 3126 /*! 3127 * Structure of static information describing PFM_REQ_HNDLR_STATE_SYNC params. 3128 */ 3129 typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS { 3130 /*! 3131 * @ref NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_<xyz> 3132 */ 3133 NvU8 flags; 3134 3135 /*! 3136 * Type-specific information. 3137 */ 3138 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA syncData; 3139 } NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS; 3140 3141 /*! 3142 * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC 3143 * 3144 * State sync with platform req handler and SMBPBI 3145 * 3146 * flags [IN] 3147 * Flags that needs sync operation between physical and kernel 3148 * 3149 * syncData [IN] 3150 * Sync payload data 3151 * 3152 */ 3153 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC (0x20800acc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID" */ 3154 3155 #define NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID (0xCCU) 3156 3157 typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS; 3158 3159 /*! 3160 * NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC 3161 * 3162 * State sync with platform req handler and SMBPBI 3163 * 3164 * flags [IN] 3165 * Flags that needs sync operation between physical and kernel 3166 * 3167 * syncData [IN] 3168 * Sync payload data 3169 * 3170 */ 3171 #define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC (0x20800acd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID" */ 3172 3173 #define NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID (0xCDU) 3174 3175 typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS; 3176 3177 /*! 3178 * Macros for NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE flag 3179 */ 3180 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_FORCED_OFF_STATUS 0x00U 3181 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_STATUS 0x01U 3182 3183 /*! 3184 * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE 3185 * 3186 * Queries PM1 Forced off / PM1 Available status 3187 * 3188 * flag [IN] 3189 * Fetch PM1 Forced off / PM1 Available status based on value. 3190 * bStatus [OUT] 3191 * PM1 Forced off / PM1 Available is true or false. 3192 * 3193 * Possible status values returned are: 3194 * NV_OK 3195 * NV_ERR_NOT_SUPPORTED 3196 * NV_ERR_INVALID_ARGUMETS 3197 */ 3198 3199 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE (0x20800ace) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID" */ 3200 3201 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID (0xCEU) 3202 3203 typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS { 3204 /*! 3205 * Fetch PM1 Forced off / PM1 Available status based on value. 3206 */ 3207 NvU8 flag; 3208 3209 /*! 3210 * PM1 Forced off / PM1 Available status 3211 */ 3212 NvBool bStatus; 3213 } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS; 3214 3215 /*! 3216 * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE 3217 * 3218 * Set PM1 state to enabled / disabled (boost clocks). 3219 * 3220 * bEnable [IN] 3221 * NV_TRUE means enable PM1, NV_FALSE means disable. 3222 * 3223 * Possible status values returned are: 3224 * NV_OK 3225 * NV_ERR_NOT_SUPPORTED 3226 */ 3227 3228 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE (0x20800acf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID" */ 3229 3230 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID (0xCFU) 3231 3232 typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS { 3233 3234 /*! 3235 * NV_TRUE means enable PM1, NV_FALSE means disable. 3236 */ 3237 NvBool bEnable; 3238 } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS; 3239 3240 /*! 3241 * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT 3242 * 3243 * Updates EDPpeak Limit of GPU 3244 * 3245 * bEnable [IN] 3246 * Enable or Reset the settings 3247 * clientLimit [IN] 3248 * Client requested limit 3249 * 3250 * Possible status values returned are: 3251 * NV_OK 3252 * NV_ERR_GENERIC 3253 * NV_ERR_NOT_SUPPORTED 3254 * NV_ERR_NOT_READY 3255 */ 3256 3257 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT (0x20800ad0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID" */ 3258 3259 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID (0xD0U) 3260 3261 typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS { 3262 NvBool bEnable; 3263 NvU32 clientLimit; 3264 } NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS; 3265 3266 /*! 3267 * NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT 3268 * 3269 * Updates Target Temperature of GPU 3270 * 3271 * targetTemp [IN] 3272 * Target Temperature Set from SBIOS 3273 * 3274 * Possible status values returned are: 3275 * NV_OK 3276 * NV_ERR_NOT_SUPPORTED 3277 */ 3278 3279 #define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT (0x20800ad1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID" */ 3280 3281 #define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID (0xD1U) 3282 3283 typedef struct NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS { 3284 NvS32 targetTemp; 3285 } NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS; 3286 3287 /*! 3288 * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE 3289 * 3290 * Enable / disable CTGP MODE 3291 * 3292 * bEnable [IN] 3293 * Enable or Reset the settings 3294 * 3295 * Possible status values returned are: 3296 * NV_OK 3297 * NV_ERR_NOT_SUPPORTED 3298 */ 3299 3300 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE (0x20800ad2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID" */ 3301 3302 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID (0xD2U) 3303 3304 typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS { 3305 NvBool bEnable; 3306 } NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS; 3307 3308 /*! 3309 * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 3310 * 3311 * Configuration of the turbo v2 parameters for NVPCF-Turbo arb control 3312 * 3313 * ctgpOffsetmW [IN] 3314 * TGP MODE Offset in mW 3315 * 3316 * Possible status values returned are: 3317 * NV_OK 3318 * NV_ERR_NOT_SUPPORTED 3319 */ 3320 3321 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 (0x20800ad3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID" */ 3322 3323 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID (0xD3U) 3324 3325 typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS { 3326 NvU32 ctgpOffsetmW; 3327 } NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS; 3328 3329 /*! 3330 * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO 3331 * 3332 * Query VPstatese info. Get VPS PS2.0 support / get highest VP State Idx and requested VP State Idx 3333 * 3334 * bVpsPs20Supported [OUT] 3335 * Reflects Vpstates PS20 support 3336 * vPstateIdxHighest [OUT} 3337 * Reflects Highest VPstate Idx 3338 * 3339 * Possible status values returned are: 3340 * NV_OK 3341 * NV_ERR_NOT_SUPPORTED 3342 */ 3343 3344 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO (0x20800ad4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID" */ 3345 3346 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID (0xD4U) 3347 3348 typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS { 3349 /*! 3350 * Reflects Vpstates PS20 support 3351 */ 3352 NvBool bVpsPs20Supported; 3353 3354 /*! 3355 * Get highest VPState Idx from VBIOS 3356 */ 3357 NvU32 vPstateIdxHighest; 3358 } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS; 3359 3360 /*! 3361 * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING 3362 * 3363 * Get vPstate mapping for requested pStateIdx 3364 * 3365 * pStateIdx [IN] 3366 * Requested PState Idx 3367 * vPstateIdx [OUT} 3368 * Mapped VPstate Idx 3369 * 3370 * Possible status values returned are: 3371 * NV_OK 3372 * NV_ERR_NOT_SUPPORTED 3373 */ 3374 3375 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING (0x20800ad5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID" */ 3376 3377 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID (0xD5U) 3378 3379 typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS { 3380 /*! 3381 * Requested PState Idx 3382 */ 3383 NvU32 pStateIdx; 3384 3385 /*! 3386 * Mapped VPstate Idx 3387 */ 3388 NvU32 vPstateIdxMapping; 3389 } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS; 3390 3391 /*! 3392 * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE 3393 * 3394 * Set requested VPstate 3395 * 3396 * vPstateIdx [IN] 3397 * VPstate Idx to be set 3398 * 3399 * Possible status values returned are: 3400 * NV_OK 3401 * NV_ERR_NOT_SUPPORTED 3402 */ 3403 3404 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE (0x20800ad6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID" */ 3405 3406 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID (0xD6U) 3407 3408 typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS { 3409 3410 /*! 3411 * NV_TRUE means enable PM1, NV_FALSE means disable. 3412 */ 3413 NvU32 vPstateIdx; 3414 } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS; 3415 3416 /* 3417 * NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE 3418 * 3419 * This command gets if GPU is in a proper state (P8 and engine idle) to be ready to enter RTD3 3420 * 3421 * Possible status return values are: 3422 * NV_OK Success 3423 */ 3424 #define NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE (0x2080a7d7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID" */ 3425 3426 #define NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID (0xD7U) 3427 3428 typedef struct NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS { 3429 NvBool bIsGC6Satisfied; 3430 NvBool bIsGCOFFSatisfied; 3431 } NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS; 3432 3433 /* 3434 * This command unsets Dynamic Boost limit when nvidia-powerd is terminated unexpectedly. 3435 */ 3436 #define NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT (0x20800a7b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7B" */ 3437 3438 /*! 3439 * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS 3440 * 3441 * This command is an internal command sent from Kernel RM to Physical RM 3442 * to get number of secure channels supported on SEC2 and CE 3443 * 3444 * maxSec2SecureChannels [OUT] 3445 * maxCeSecureChannels [OUT] 3446 */ 3447 #define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS (0x20800ad8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID" */ 3448 3449 #define NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID (0xD8U) 3450 3451 typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS { 3452 NvU32 maxSec2SecureChannels; 3453 NvU32 maxCeSecureChannels; 3454 } NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS; 3455 3456 /* 3457 * NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS 3458 * 3459 * This command is an internal command sent from Kernel RM to Physical RM 3460 * to disable the GPU system memory access after quiescing the GPU or 3461 * re-enable sysmem access. 3462 * 3463 * bDisable [IN] 3464 * If NV_TRUE the GPU is quiesced and system memory access is disabled . 3465 * If NV_FALSE the GPU system memory access is re-enabled and the GPU is resumed. 3466 * 3467 * Possible status values returned are: 3468 * NV_OK 3469 * NV_ERR_INVALID_PARAM_STRUCT 3470 * NV_ERR_INVALID_ARGUMENT 3471 * NV_ERR_NOT_SUPPORTED 3472 */ 3473 #define NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS (0x20800adb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID" */ 3474 3475 #define NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID (0xDBU) 3476 3477 typedef struct NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS { 3478 NvBool bDisable; 3479 } NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS; 3480 3481 #define NV2080_CTRL_CMD_INTERNAL_DISP_PINSETS_TO_LOCKPINS (0x20800adc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID" */ 3482 3483 #define NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID (0xDCU) 3484 3485 typedef struct NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS { 3486 NvU32 pinSetIn; // in 3487 NvU32 pinSetOut; // in 3488 NvBool bMasterScanLock; // out 3489 NvU32 masterScanLockPin; // out 3490 NvBool bSlaveScanLock; // out 3491 NvU32 slaveScanLockPin; // out 3492 } NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS; 3493 3494 #define NV2080_CTRL_CMD_INTERNAL_DETECT_HS_VIDEO_BRIDGE (0x20800add) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xDD" */ 3495 3496 #define NV2080_CTRL_CMD_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL (0x20800ade) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID" */ 3497 3498 #define NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID (0xDEU) 3499 3500 typedef struct NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS { 3501 NvU32 pinSet; // in 3502 NvU32 gpioFunction; // out 3503 NvU32 gpioPin; // out 3504 NvBool gpioDirection; // out 3505 } NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS; 3506 3507 /* NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA 3508 * 3509 * This command sets up ACPI DDC Edid data. 3510 * 3511 * Possible status values returned are: 3512 * NV_OK 3513 * NV_ERR_INVALID_ARGUMENT 3514 * NV_ERR_NOT_SUPPORTED 3515 */ 3516 #define NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA (0x20800adf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID" */ 3517 3518 /* From ACPI6.5 spec., the max size of EDID data from SBIOS(_DDC) is 512B */ 3519 #define MAX_EDID_SIZE_FROM_SBIOS 512U 3520 3521 typedef struct NV2080_CTRL_INTERNAL_EDID_DATA { 3522 NvU32 status; 3523 NvU32 acpiId; 3524 NvU32 bufferSize; 3525 NvU8 edidBuffer[MAX_EDID_SIZE_FROM_SBIOS]; 3526 } NV2080_CTRL_INTERNAL_EDID_DATA; 3527 3528 #define NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID (0xDFU) 3529 3530 typedef struct NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS { 3531 NvU32 tableLen; 3532 NV2080_CTRL_INTERNAL_EDID_DATA edidTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS]; 3533 } NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS; 3534 3535 /*! 3536 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED 3537 * 3538 * This command intializes display ACPI child devices. 3539 * This command accepts no parameters. 3540 * 3541 */ 3542 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED (0x20800af0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF0" */ 3543 3544 /* NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET */ 3545 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET (0x20800af1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF1" */ 3546 3547 /* NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET */ 3548 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET (0x20800af2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF2" */ 3549 3550 /*! 3551 * NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS 3552 * 3553 * This structure provides the params for getting GPU Fabric Probe Internal 3554 * Info from GSP to CPU RM 3555 * 3556 * numProbes[OUT] 3557 * - Number of probe requests sent 3558 */ 3559 #define NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF4U) 3560 3561 typedef struct NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS { 3562 NV_DECLARE_ALIGNED(NvU64 numProbes, 8); 3563 } NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS; 3564 3565 /*! 3566 * NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO 3567 * 3568 * This command is used to get NV2080_CTRL_CMD_INTERNAL_GPU_FABRIC_PROBE_INFO_PARAMS 3569 * from GSP to CPU RM. 3570 * This command accepts NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS 3571 * 3572 */ 3573 #define NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO (0x208001f4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ 3574 3575 /*! 3576 * NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS 3577 * 3578 * This structure provides the params for starting GPU Fabric Probe 3579 * 3580 * bwMode[IN] 3581 * - Nvlink Bandwidth mode 3582 * 3583 * bLocalEgmEnabled[IN] 3584 * - EGM Enablement Status that needs to be set in GSP-RM 3585 */ 3586 #define NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF5U) 3587 3588 typedef struct NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS { 3589 NvU8 bwMode; 3590 NvBool bLocalEgmEnabled; 3591 } NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS; 3592 3593 /*! 3594 * NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE 3595 * 3596 * This command is used to trigger start of GPU FABRIC PROBE PROCESS on GSP. 3597 * This command accepts NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS 3598 * 3599 */ 3600 #define NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE (0x208001f5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ 3601 3602 /*! 3603 * NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE 3604 * 3605 * This command is used to trigger stop of GPU FABRIC PROBE PROCESS on GSP. 3606 * This command accepts no parameters 3607 * 3608 */ 3609 #define NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE (0x208001f6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF6" */ 3610 3611 /*! 3612 * NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE 3613 * 3614 * This command is used to trigger suspend of GPU FABRIC PROBE PROCESS on GSP. 3615 * This command accepts no parameters 3616 * 3617 */ 3618 #define NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE (0x208001f7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF7" */ 3619 3620 3621 /*! 3622 * NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS 3623 * 3624 * This structure provides the params for resuming GPU Fabric Probe 3625 * 3626 * bwMode[IN] 3627 * - Nvlink Bandwidth mode 3628 */ 3629 #define NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF8U) 3630 3631 typedef struct NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS { 3632 NvU8 bwMode; 3633 } NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS; 3634 3635 /*! 3636 * NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE 3637 * 3638 * This command is used to trigger resume of GPU FABRIC PROBE PROCESS on GSP. 3639 * This command accepts NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS 3640 * 3641 */ 3642 #define NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE (0x208001f8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ 3643 3644 /*! 3645 * NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE 3646 * 3647 * This command is used to invalidate/reset GPU_FABRIC_PROBE_INFO on GSP. 3648 * This command accepts no parameters 3649 * 3650 */ 3651 #define NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE (0x208001f9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF9" */ 3652 3653 /*! 3654 * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO 3655 * 3656 * This command is an internal command sent from Kernel RM to Physical RM 3657 * to get static conf compute info 3658 * 3659 * bIsBar1Trusted: [OUT] 3660 * Is BAR1 trusted to access CPR 3661 * bIsPcieTrusted: [OUT] 3662 * Is PCIE trusted to access CPR 3663 */ 3664 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO (0x20800af3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ 3665 3666 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0xF3U) 3667 3668 typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS { 3669 NvBool bIsBar1Trusted; 3670 NvBool bIsPcieTrusted; 3671 } NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS; 3672 3673 /*! 3674 * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS 3675 * 3676 * This command is an internal command sent from Kernel RM to Physical RM 3677 * to derive SWL keys and IV masks for a given engine 3678 * 3679 * engineId: [IN] 3680 * NV2080_ENGINE_TYPE_* for engine for which keys and IV mask should be derived 3681 * ivMaskSet: [OUT] 3682 * Set of IV masks for given engine 3683 */ 3684 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS (0x20800ae1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID" */ 3685 3686 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE 3U 3687 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_KERNEL 0U 3688 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_USER 1U 3689 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_SCRUBBER 2U 3690 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT 3U 3691 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT 6U 3692 3693 typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK { 3694 NvU32 ivMask[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE]; 3695 } NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK; 3696 3697 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID (0xE1U) 3698 3699 typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS { 3700 NvU32 engineId; 3701 NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT]; 3702 } NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS; 3703 3704 /*! 3705 * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS 3706 * 3707 * This command is an internal command sent from Kernel RM to Physical RM 3708 * to derive LCE keys and IV masks for a given engine 3709 * 3710 * engineId: [IN] 3711 * NV2080_ENGINE_TYPE_* for engine for which keys and IV mask should be derived 3712 * ivMaskSet: [OUT] 3713 * Set of IV masks for given engine 3714 */ 3715 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS (0x20800ae2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID" */ 3716 3717 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID (0xE2U) 3718 3719 typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS { 3720 NvU32 engineId; 3721 NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT]; 3722 } NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS; 3723 3724 /*! 3725 * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEY 3726 * 3727 * This command handles key rotation for a given H2D key (and corresponding D2H key) 3728 * by deriving new key on GSP and updating the key on relevant SEC2 or LCE. 3729 * It also updates IVs for all channels using the key and conditionally re-enables them 3730 * and notifies clients of key rotation status at the end. 3731 * 3732 * globalH2DKey : [IN] 3733 * global h2d key to be rotated 3734 * updatedEncryptIVMask: [OUT] 3735 * Encrypt IV mask post IV key rotation for a given engine's kernel channel 3736 * updatedDecryptIVMask: [OUT] 3737 * Decrypt IV mask post IV key rotation for a given engine's kernel channel 3738 */ 3739 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEYS (0x20800ae5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS_MESSAGE_ID" */ 3740 3741 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS_MESSAGE_ID (0xE5U) 3742 3743 typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS { 3744 NvU32 globalH2DKey; 3745 NvU32 updatedEncryptIVMask[CC_AES_256_GCM_IV_SIZE_DWORD]; 3746 NvU32 updatedDecryptIVMask[CC_AES_256_GCM_IV_SIZE_DWORD]; 3747 } NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS; 3748 3749 /*! 3750 * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION 3751 * 3752 * This command RCs all channels that use the given key and have not reported 3753 * idle via NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION yet. 3754 * RM needs to RC such channels before going ahead with key rotation. 3755 * 3756 * globalH2DKey : [IN] 3757 * global h2d key whose channels will be RCed 3758 */ 3759 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION (0x20800ae6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID" */ 3760 3761 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID (0xE6U) 3762 3763 typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS { 3764 NvU32 exceptionType; 3765 NvU32 globalH2DKey; 3766 } NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS; 3767 3768 /*! 3769 * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE 3770 * 3771 * This control call can be used to set gpu state on GSP to accept client requests 3772 * or to block client requests. 3773 * This is a internal command sent from Kernel RM to Physical RM. 3774 * 3775 * bAcceptClientRequest:[IN] 3776 * NV_TRUE : set gpu state to accept client work requests 3777 * NV_FALSE: set gpu state to block client work requests 3778 * 3779 */ 3780 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE (0x20800ae7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID" */ 3781 3782 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID (0xE7U) 3783 3784 typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS { 3785 NvBool bAcceptClientRequest; 3786 } NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS; 3787 3788 /*! 3789 * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY 3790 * 3791 * This control call can be used to set CC security policy on GSP. 3792 * This is a internal command sent from Kernel RM to Physical RM. 3793 * 3794 * attackerAdvantage [IN] 3795 * The minimum and maximum values for attackerAdvantage. 3796 * The probability of an attacker successfully guessing the contents of 3797 * an encrypted packet go up ("attacker advantage"). 3798 * 3799 * Possible status values returned are: 3800 * NV_OK 3801 * NV_ERR_INVALID_OBJECT_HANDLE 3802 * NV_ERR_INVALID_STATE 3803 * NV_ERR_INVALID_ARGUMENT 3804 * NV_ERR_NOT_SUPPORTED 3805 */ 3806 3807 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY (0x20800ae8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID" */ 3808 3809 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID (0xE8U) 3810 3811 typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS { 3812 NV_DECLARE_ALIGNED(NvU64 attackerAdvantage, 8); 3813 } NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS; 3814 3815 3816 3817 /* 3818 * NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP 3819 * 3820 * This command is used by CPU-RM to perform memory operations using GSP 3821 * 3822 * 3823 * Possible status values returned are: 3824 * NV_OK 3825 * NVOS_STATUS_TIMEOUT_RETRY 3826 * NV_ERR_NOT_SUPPORTED 3827 */ 3828 3829 #define NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP (0x20800afa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID" */ 3830 3831 typedef enum NV2080_CTRL_MEMMGR_MEMORY_OP { 3832 NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY = 0, 3833 NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET = 1, 3834 } NV2080_CTRL_MEMMGR_MEMORY_OP; 3835 3836 typedef struct NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO { 3837 /*! 3838 * Base physical address of the surface 3839 */ 3840 NV_DECLARE_ALIGNED(NvU64 baseAddr, 8); 3841 3842 /*! 3843 * Size of the surface in bytes 3844 */ 3845 NV_DECLARE_ALIGNED(NvU64 size, 8); 3846 3847 /*! 3848 * Offset in bytes into the surface where read/write must happen 3849 */ 3850 NV_DECLARE_ALIGNED(NvU64 offset, 8); 3851 3852 /*! 3853 * Aperture where the surface is allocated 3854 */ 3855 NvU32 aperture; 3856 3857 /*! 3858 * CPU caching attribute of the surface 3859 */ 3860 NvU32 cpuCacheAttrib; 3861 } NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO; 3862 3863 #define CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES (0x10U) /* finn: Evaluated from "(128 / 8)" */ 3864 3865 #define NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID (0xFAU) 3866 3867 typedef struct NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS { 3868 3869 /*! 3870 * Source surface info 3871 */ 3872 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO src, 8); 3873 3874 /*! 3875 * Authentication tag if data is encrypted 3876 */ 3877 NvU8 authTag[CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES]; 3878 3879 /*! 3880 * Destination surface info 3881 */ 3882 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO dst, 8); 3883 3884 /*! 3885 * Size of the data to be transferred 3886 */ 3887 NV_DECLARE_ALIGNED(NvU64 transferSize, 8); 3888 3889 /*! 3890 * To be set in case of memset 3891 */ 3892 NvU32 value; 3893 3894 /*! 3895 * Memory op to be performed 3896 */ 3897 NV2080_CTRL_MEMMGR_MEMORY_OP memop; 3898 } NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS; 3899 3900 /*! 3901 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG 3902 * 3903 * This command is an internal command sent from Kernel RM to Physical RM 3904 * to get local GPU's ATS config 3905 * 3906 * addrSysPhys : [OUT] 3907 * System Physical Address 3908 * addrWidth : [OUT] 3909 * Address width value 3910 * mask : [OUT] 3911 * Mask value 3912 * maskWidth : [OUT] 3913 * Mask width value 3914 */ 3915 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG (0x20800afb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID" */ 3916 3917 #define NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID (0xFBU) 3918 3919 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS { 3920 NV_DECLARE_ALIGNED(NvU64 addrSysPhys, 8); 3921 NvU32 addrWidth; 3922 NvU32 mask; 3923 NvU32 maskWidth; 3924 } NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS; 3925 3926 /*! 3927 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG 3928 * 3929 * This command is an internal command sent from Kernel RM to Physical RM 3930 * to set peer ATS config using the parameters passed in. 3931 * 3932 * peerId : [IN] 3933 * Peer Id of the peer for which ATS config is to be programmed 3934 * addrSysPhys : [IN] 3935 * System Physical Address 3936 * addrWidth : [IN] 3937 * Address width value 3938 * mask : [IN] 3939 * Mask value 3940 * maskWidth : [IN] 3941 * Mask width value 3942 */ 3943 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG (0x20800afc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID" */ 3944 3945 #define NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID (0xFCU) 3946 3947 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS { 3948 NvU32 peerId; 3949 NV_DECLARE_ALIGNED(NvU64 addrSysPhys, 8); 3950 NvU32 addrWidth; 3951 NvU32 mask; 3952 NvU32 maskWidth; 3953 } NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS; 3954 3955 /*! 3956 * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO 3957 * 3958 * Get GPU EDPpeak Limit information 3959 * 3960 * limitMin [OUT] 3961 * Minimum allowed limit value on EDPp policy on both AC and DC 3962 * limitRated [OUT] 3963 * Rated/default allowed limit value on EDPp policy on AC 3964 * limitMax [OUT] 3965 * Maximum allowed limit value on EDPp policy on AC 3966 * limitCurr [OUT] 3967 * Current resultant limit effective on EDPp policy on AC and DC 3968 * limitBattRated [OUT] 3969 * Default/rated allowed limit on EDPp policy on DC 3970 * limitBattMax [OUT] 3971 * Maximum allowed limit on EDPp policy on DC 3972 * 3973 * Possible status values returned are: 3974 * NV_OK 3975 * NV_ERR_GENERIC 3976 */ 3977 3978 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO (0x20800afd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID" */ 3979 3980 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID (0xFDU) 3981 3982 typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS { 3983 NvU32 limitMin; 3984 NvU32 limitRated; 3985 NvU32 limitMax; 3986 NvU32 limitCurr; 3987 NvU32 limitBattRated; 3988 NvU32 limitBattMax; 3989 } NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS; 3990 3991 /* 3992 * NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA 3993 * 3994 * @brief Initialize RM User Shared Data memory mapping on physical RM 3995 * 3996 * @param[in] physAddr Physical address of memdesc to link physical to kernel 3997 * 0 to de-initialize 3998 * 3999 * @return NV_OK on success 4000 * @return NV_ERR_ otherwise 4001 */ 4002 #define NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID (0xFEU) 4003 4004 typedef struct NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS { 4005 NV_DECLARE_ALIGNED(NvU64 physAddr, 8); 4006 } NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS; 4007 #define NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA (0x20800afe) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID" */ 4008 4009 /* 4010 * NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL 4011 * 4012 * @brief Set mask of data to be polled on physical for RUSD 4013 * 4014 * @param[in] polledDataMask Bitmask of data requested, defined in cl00de 4015 * 4016 * @return NV_OK on success 4017 * @return NV_ERR_ otherwise 4018 */ 4019 #define NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID (0xFFU) 4020 4021 typedef struct NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS { 4022 NV_DECLARE_ALIGNED(NvU64 polledDataMask, 8); 4023 } NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS; 4024 #define NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL (0x20800aff) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID" */ 4025 4026 /*! 4027 * NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS 4028 * 4029 * This structure provides the params for starting GPU Fabric Probe 4030 * 4031 * tracepointMask[IN] 4032 * - tracepoint selection filter 4033 * bufferSize[IN] 4034 * - size of gsp side logging buffer 4035 * bufferWatermark[IN] 4036 * - entry threshold for GSP to issue RPC of logged entries to kernel RM 4037 * bStart[IN] 4038 * - if true, start tracing. if false, stop tracing. 4039 */ 4040 #define NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS_MESSAGE_ID (0xE3U) 4041 4042 typedef struct NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS { 4043 NV_DECLARE_ALIGNED(NvU64 tracepointMask, 8); 4044 NvU32 bufferSize; 4045 NvU32 bufferWatermark; 4046 NvBool bStart; 4047 } NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS; 4048 4049 /* 4050 * NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE 4051 * 4052 * This command is used to start GSP-RM trace tool. 4053 * This command accepts NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS 4054 * 4055 */ 4056 #define NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE (0x208001e3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS_MESSAGE_ID" */ 4057 4058 /* 4059 * NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES 4060 * 4061 * @brief get state (enabled/disabled) of SEC2 classes 4062 * 4063 * 4064 * @return NV_OK on success 4065 * @return NV_ERR_ otherwise 4066 */ 4067 #define NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID (0xAFU) 4068 4069 typedef struct NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS { 4070 NvBool bMaxwellSec2Enabled; 4071 NvBool bNv95A1TsecEnabled; 4072 NvBool bHopperSec2WorkLaunchAEnabled; 4073 } NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS; 4074 #define NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES (0x20800aaf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID" */ 4075 4076 4077 /*! 4078 * @ref NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND 4079 */ 4080 #define NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND (0x20800ae4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID" */ 4081 4082 #define NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID (0xE4U) 4083 4084 typedef NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS; 4085 4086 /*! 4087 * NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER 4088 * 4089 * @brief Notify the offloaded RM that CPU-RM enters the power management cycle. 4090 * 4091 * bInPMTransition : [IN] 4092 * newPMLevel : [IN] 4093 * New PM Level : NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_[0-7] 4094 * 4095 * @return NV_OK on success 4096 * @return NV_ERR_ otherwise 4097 */ 4098 #define NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS_MESSAGE_ID (0xE9U) 4099 4100 typedef struct NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS { 4101 NvBool bInPMTransition; 4102 NvU32 newPMLevel; 4103 } NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS; 4104 #define NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER (0x20800ae9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS_MESSAGE_ID" */ 4105 4106 /*! 4107 * NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_FATAL_RECOVERY 4108 * 4109 * This command is used to perform recovery actions after the fabric has been 4110 * idled due to a fatal nvlink error. 4111 * This command accepts no parameters. 4112 */ 4113 #define NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY (0x20800aea) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xEA" */ 4114 4115 /*! 4116 * NV2080_CTRL_CMD_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP 4117 * 4118 * @brief To get the free heap size of GSP-RM 4119 * 4120 * freeHeapSize : [OUT] 4121 * 4122 * @return NV_OK 4123 */ 4124 #define NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS_MESSAGE_ID (0xEBU) 4125 4126 typedef struct NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS { 4127 NV_DECLARE_ALIGNED(NvU64 freeHeapSize, 8); 4128 } NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS; 4129 #define NV2080_CTRL_CMD_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP (0x20800aeb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS_MESSAGE_ID" */ 4130 4131 /* 4132 * NV2080_CTRL_CMD_INTERNAL_GPU_SET_ILLUM 4133 * 4134 * This command sets a new value for the specified Illumination control attribute. 4135 * 4136 * Possible status return values are: 4137 * NV_OK 4138 * NV_ERR_NOT_SUPPORTED 4139 */ 4140 #define NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID (0xECU) 4141 4142 typedef struct NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS { 4143 NvU32 attribute; 4144 NvU32 value; 4145 } NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS; 4146 #define NV2080_CTRL_CMD_INTERNAL_GPU_SET_ILLUM (0x20800aecU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID" */ 4147 /*! 4148 * NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM 4149 * 4150 * Returns the maximum number of HSHUBs in a shim instance. 4151 * 4152 * maxHshubs[OUT] 4153 * The maximum number of HSHUBs in a shim instance. 4154 * 4155 * @return NV_OK 4156 */ 4157 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM (0x20800a79) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID" */ 4158 4159 #define NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID (0x79U) 4160 4161 typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS { 4162 NvU32 maxHshubs; 4163 } NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS; 4164 4165 /* ctrl2080internal_h */ 4166