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Searched refs:ADDI (Results 1 – 25 of 60) sorted by relevance

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/openbsd/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoXVentana.td48 (VT_MASKC GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)))>;
50 (VT_MASKCN GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)))>;
52 (VT_MASKCN GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)))>;
54 (VT_MASKC GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)))>;
90 (OR (VT_MASKC GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y))),
91 (VT_MASKCN GPR:$rs2, (ADDI GPR:$x, (NegImm simm12_plus1:$y))))>;
93 (OR (VT_MASKC GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y))),
94 (VT_MASKCN GPR:$rs2, (ADDI GPR:$x, (NegImm simm12_plus1:$y))))>;
H A DRISCVMergeBaseOffset.cpp108 if (Lo->getOpcode() != RISCV::ADDI) in INITIALIZE_PASS()
186 if (OffsetTail.getOpcode() == RISCV::ADDI || in foldLargeOffset()
258 if (OffsetTail.getOpcode() != RISCV::ADDI) in foldShiftedOffset()
301 case RISCV::ADDI: { in detectAndFoldOffset()
309 if (TailTail.getOpcode() == RISCV::ADDI) { in detectAndFoldOffset()
H A DRISCVAsmPrinter.cpp342 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI) in EmitHwasanMemaccessSymbols()
360 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI) in EmitHwasanMemaccessSymbols()
422 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI) in EmitHwasanMemaccessSymbols()
452 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI) in EmitHwasanMemaccessSymbols()
458 MCInstBuilder(RISCV::ADDI) in EmitHwasanMemaccessSymbols()
H A DRISCVRegisterInfo.cpp207 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg) in adjustReg()
225 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg) in adjustReg()
229 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg) in adjustReg()
421 if (MI.getOpcode() == RISCV::ADDI && !isInt<12>(Offset.getFixed())) { in eliminateFrameIndex()
442 if (MI.getOpcode() == RISCV::ADDI) in eliminateFrameIndex()
458 if (MI.getOpcode() == RISCV::ADDI && in eliminateFrameIndex()
586 BuildMI(*MBB, MBBI, DL, TII->get(RISCV::ADDI), BaseReg) in materializeFrameBaseRegister()
742 case RISCV::ADDI: in getRegAllocationHints()
H A DRISCVSExtWRemoval.cpp81 case RISCV::ADDI: in isSignExtendingOpW()
281 case RISCV::ADDI: in isSignExtendedW()
302 case RISCV::ADDI: in getWOp()
H A DRISCVMacroFusion.cpp27 if (SecondMI.getOpcode() != RISCV::ADDI && in isLUIADDI()
H A DRISCVExpandPseudoInsts.cpp152 BuildMI(TrueBB, DL, TII->get(RISCV::ADDI), DestReg) in expandCCOp()
352 RISCV::ADDI); in expandLoadLocalAddress()
386 RISCV::ADDI); in expandLoadTLSGDAddress()
H A DRISCVInstrInfo.td420 // Check if (add r, imm) can be optimized to (ADDI (ADDI r, imm0), imm1),
643 def ADDI : ALU_ri<0b000, "addi">;
1232 def : PatGprSimm12<add, ADDI>;
1251 def : PatGprSimm12<or_is_add, ADDI>;
1295 (ADDI GPR:$rs1, simm12:$imm12)>;
1305 (ADDI GPR:$hi, tglobaladdr:$lo)>;
1307 (ADDI GPR:$hi, tblockaddress:$lo)>;
1309 (ADDI GPR:$hi, tjumptable:$lo)>;
1311 (ADDI GPR:$hi, tconstpool:$lo)>;
1319 (ADDI GPR:$src, tglobaltlsaddr:$lo)>;
[all …]
H A DRISCVFrameLowering.cpp76 BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI)) in emitSCSPrologue()
126 BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI)) in emitSCSEpilogue()
600 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), BPReg) in emitPrologue()
1006 } else if (MI.getOpcode() == RISCV::ADDI && IsScalableVectorID) { in getScavSlotsNumForRVV()
H A DRISCVInstrInfoC.td760 def : CompressPat<(ADDI GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm),
806 def : CompressPat<(ADDI X0, X0, 0), (C_NOP)>;
807 def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs1, simm6nonzero:$imm),
822 def : CompressPat<(ADDI GPRNoX0:$rd, X0, simm6:$imm),
824 def : CompressPat<(ADDI X2, X2, simm10_lsb0000nonzero:$imm),
910 def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, 0),
H A DRISCVMakeCompressible.cpp359 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(RISCV::ADDI), NewReg) in runOnMachineFunction()
/openbsd/gnu/llvm/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp28 case RISCV::ADDI: in getInstSeqCost()
75 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI; in generateInstSeqImpl()
153 Res.emplace_back(RISCV::ADDI, Lo12); in generateInstSeqImpl()
348 TmpSeq.emplace_back(RISCV::ADDI, Lo12); in generateInstSeq()
362 TmpSeq.emplace_back(RISCV::ADDI, NegImm12); in generateInstSeq()
400 case RISCV::ADDI: in getOpndKind()
/openbsd/gnu/llvm/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVCInstructions.h166 return ADDI{rd, Rs{0}, uint32_t(imm)}; in DecodeC_LI()
167 return ADDI{rd, Rs{0}, uint32_t(int32_t(int8_t(imm | 0xc0)))}; in DecodeC_LI()
183 return ADDI{Rd{gpr_sp_riscv}, Rs{gpr_sp_riscv}, uint32_t(nzimm)}; in DecodeC_LUI_ADDI16SP()
184 return ADDI{Rd{gpr_sp_riscv}, Rs{gpr_sp_riscv}, in DecodeC_LUI_ADDI16SP()
200 return ADDI{rd, rd, uint32_t(imm)}; in DecodeC_ADDI()
201 return ADDI{rd, rd, uint32_t(int32_t(int8_t(imm | 0xc0)))}; in DecodeC_ADDI()
225 return ADDI{rd, Rs{gpr_sp_riscv}, uint32_t(nzuimm)}; in DecodeC_ADDI4SPN()
H A DRISCVInstructions.h121 I_TYPE_INST(ADDI);
276 LUI, AUIPC, JAL, JALR, B, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI,
/openbsd/gnu/usr.bin/gcc/gcc/testsuite/gcc.c-torture/compile/
H A D950612-1.c5 ADDI, enumerator
33 case ADDI:
/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCMacroFusion.def35 FUSION_OP_SET(ADDI, ADDI8, ADDItocL), \
138 FUSION_OP_SET(ADDI, ADDI8, ADDItocL))
142 FUSION_OP_SET(ADDI, ADDI8, ADDItocL),
H A DPPCBack2BackFusion.def21 ADDI,
506 ADDI,
H A DPPCMachineScheduler.cpp25 return Cand.SU->getInstr()->getOpcode() == PPC::ADDI || in isADDIInstr()
H A DPPCCTRLoops.cpp250 unsigned ADDIOpcode = Is64Bit ? PPC::ADDI8 : PPC::ADDI; in expandNormalLoops()
/openbsd/sys/lib/libkern/arch/hppa/
H A Dmilli.S616 ADDI 1,arg0,arg0
623 ADDI 3,arg0,arg0
630 ADDI 7,arg0,arg0
645 ADDI 1,arg0,arg0
660 ADDI 1,arg0,arg0
670 ADDI 3,arg0,t1
677 ADDI 1,arg0,arg0
685 ADDI 1,arg0,arg0
696 ADDI 5,arg0,t1
721 ADDI 3,arg0,t1
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/LoongArch/AsmParser/
H A DLoongArchAsmParser.cpp859 unsigned ADDI = is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W; in emitLoadAddressPcrel() local
864 LoongArchAsmParser::Inst(ADDI, LoongArchMCExpr::VK_LoongArch_PCALA_LO12)); in emitLoadAddressPcrel()
1015 unsigned ADDI = is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W; in emitLoadAddressTLSLD() local
1020 ADDI, LoongArchMCExpr::VK_LoongArch_GOT_PC_LO12)); in emitLoadAddressTLSLD()
1061 unsigned ADDI = is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W; in emitLoadAddressTLSGD() local
1066 ADDI, LoongArchMCExpr::VK_LoongArch_GOT_PC_LO12)); in emitLoadAddressTLSGD()
/openbsd/gnu/llvm/lld/ELF/Arch/
H A DRISCV.cpp54 ADDI = 0x13, enumerator
223 write32le(buf + 12, itype(ADDI, X_T1, X_T1, -target->pltHeaderSize - 12)); in writePltHeader()
224 write32le(buf + 16, itype(ADDI, X_T0, X_T2, lo12(offset))); in writePltHeader()
240 write32le(buf + 12, itype(ADDI, 0, 0, 0)); in writePlt()
/openbsd/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp393 MachineInstr &ADDI = in insertIndirectBranch() local
421 ADDI.getOperand(2).setMBB(&RestoreBB); in insertIndirectBranch()
/openbsd/gnu/usr.bin/binutils/gas/doc/
H A Dc-xtensa.texi400 @cindex @code{ADDI} instructions, relaxation
401 @cindex relaxation of @code{ADDI} instructions
402 The Xtensa @code{ADDI} instruction only allows immediate operands in the
404 sequences for the generic @code{ADDI} operation. First, if the
405 immediate is 0, the @code{ADDI} will be turned into a @code{MOV.N}
407 option is not available). If the @code{ADDI} immediate is outside of
409 @code{ADDMI} instruction or @code{ADDMI}/@code{ADDI} sequence will be
/openbsd/gnu/usr.bin/binutils-2.17/gas/doc/
H A Dc-xtensa.texi452 @cindex @code{ADDI} instructions, relaxation
453 @cindex relaxation of @code{ADDI} instructions
454 The Xtensa @code{ADDI} instruction only allows immediate operands in the
456 sequences for the @code{ADDI} operation. First, if the
457 immediate is 0, the @code{ADDI} will be turned into a @code{MOV.N}
459 option is not available). If the @code{ADDI} immediate is outside of
461 @code{ADDMI} instruction or @code{ADDMI}/@code{ADDI} sequence will be

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