1 /* $OpenBSD: agpreg.h,v 1.18 2014/03/17 22:01:56 kettenis Exp $ */ 2 /* $NetBSD: agpreg.h,v 1.1 2001/09/10 10:01:02 fvdl Exp $ */ 3 4 /*- 5 * Copyright (c) 2000 Doug Rabson 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/pci/agpreg.h,v 1.3 2000/07/12 10:13:04 dfr Exp $ 30 */ 31 32 #ifndef _PCI_AGPREG_H_ 33 #define _PCI_AGPREG_H_ 34 35 /* 36 * The AGP gatt uses 4k pages irrespective of the host page size. 37 */ 38 #define AGP_PAGE_SIZE 4096 39 #define AGP_PAGE_SHIFT 12 40 41 /* 42 * Offsets for various AGP configuration registers. 43 */ 44 #define AGP_APBASE 0x10 45 46 /* 47 * Offsets from the AGP Capability pointer. 48 */ 49 #define AGP_CAPID 0x02 50 #define AGP_CAPID_GET_MAJOR(x) (((x) & 0x00f00000U) >> 20) 51 #define AGP_CAPID_GET_MINOR(x) (((x) & 0x000f0000U) >> 16) 52 #define AGP_CAPID_GET_NEXT_PTR(x) (((x) & 0x0000ff00U) >> 8) 53 #define AGP_CAPID_GET_CAP_ID(x) (((x) & 0x000000ffU) >> 0) 54 55 #define AGP_STATUS 0x4 56 #define AGP_COMMAND 0x8 57 58 /* 59 * Macros to manipulate AGP mode words. 60 */ 61 #define AGP_MODE_GET_RQ(x) (((x) & 0xff000000U) >> 24) 62 #define AGP_MODE_GET_SBA(x) (((x) & 0x00000200U) >> 9) 63 #define AGP_MODE_GET_AGP(x) (((x) & 0x00000100U) >> 8) 64 #define AGP_MODE_GET_4G(x) (((x) & 0x00000020U) >> 5) 65 #define AGP_MODE_GET_FW(x) (((x) & 0x00000010U) >> 4) 66 #define AGP_MODE_GET_RATE(x) ((x) & 0x00000007U) 67 #define AGP_MODE_SET_RQ(x,v) (((x) & ~0xff000000U) | ((v) << 24)) 68 #define AGP_MODE_SET_SBA(x,v) (((x) & ~0x00000200U) | ((v) << 9)) 69 #define AGP_MODE_SET_AGP(x,v) (((x) & ~0x00000100U) | ((v) << 8)) 70 #define AGP_MODE_SET_4G(x,v) (((x) & ~0x00000020U) | ((v) << 5)) 71 #define AGP_MODE_SET_FW(x,v) (((x) & ~0x00000010U) | ((v) << 4)) 72 #define AGP_MODE_SET_RATE(x,v) (((x) & ~0x00000007U) | (v)) 73 #define AGP_MODE_RATE_1x 0x00000001 74 #define AGP_MODE_RATE_2x 0x00000002 75 #define AGP_MODE_RATE_4x 0x00000004 76 77 /* 78 * Config offsets for Intel AGP chipsets. 79 */ 80 /* i840/850/850E */ 81 #define AGP_I840_MCHCFG 0x50 82 #define MCHCFG_AAGN (1U << 9) /* Aperture AccessEN */ 83 84 /* i82443LX/BX/GX */ 85 #define AGP_INTEL_NBXCFG 0x50 86 #define AGP_INTEL_STS 0x90 87 #define NBXCFG_APAE (1U << 10) /* AGPtoPCI AccessDIS */ 88 #define NBXCFG_AAGN (1U << 9) /* Aperture AccessEN */ 89 90 /* Error Status for i8XX Chipset */ 91 #define AGP_INTEL_I8XX_ERRSTS 0xc8 92 93 /* Common register */ 94 #define AGP_INTEL_ERRCMD 0x90 /* Not i8XX, 8 bits 95 * ERRSTS is at + 1 and is 16 96 */ 97 #define AGP_INTEL_AGPCMD 0xa8 98 #define AGPCMD_SBA (1U << 9) 99 #define AGPCMD_AGPEN (1U << 8) 100 #define AGPCMD_FWEN (1U << 4) 101 #define AGPCMD_RATE_1X (1U << 1) 102 #define AGPCMD_RATE_2X (1U << 2) 103 #define AGPCMD_RATE_4X (1U << 3) 104 105 #define AGP_INTEL_AGPCTRL 0xb0 106 #define AGPCTRL_AGPRSE (1U << 13) /* AGPRSE (82443 only)*/ 107 #define AGPCTRL_GTLB (1U << 7) /* GTLB EN */ 108 109 #define AGP_INTEL_APSIZE 0xb4 110 #define APSIZE_MASK 0x3f 111 112 #define AGP_INTEL_ATTBASE 0xb8 113 114 /* 115 * Config offsets for VIA AGP 2.x chipsets. 116 */ 117 #define AGP_VIA_GARTCTRL 0x80 118 #define AGP_VIA_APSIZE 0x84 119 #define AGP_VIA_ATTBASE 0x88 120 121 /* 122 * Config offsets for VIA AGP 3.0 chipsets. 123 */ 124 #define AGP3_VIA_GARTCTRL 0x90 125 #define AGP3_VIA_APSIZE 0x94 126 #define AGP3_VIA_ATTBASE 0x98 127 #define AGP_VIA_AGPSEL_REG 0xfc 128 #define AGP_VIA_AGPSEL 0xfd 129 130 /* 131 * Config offsets for SiS AGP chipsets. 132 */ 133 #define AGP_SIS_ATTBASE 0x90 134 #define AGP_SIS_WINCTRL 0x94 135 #define AGP_SIS_TLBCTRL 0x97 136 #define AGP_SIS_TLBFLUSH 0x98 137 138 /* 139 * Config offsets for Apple UniNorth & U3 AGP chipsets. 140 */ 141 #define AGP_APPLE_ATTBASE 0x8c 142 #define AGP_APPLE_APBASE 0x90 143 #define AGP_APPLE_GARTCTRL 0x94 144 145 #define AGP_APPLE_GART_INVALIDATE 0x00001 146 #define AGP_APPLE_GART_ENABLE 0x00100 147 #define AGP_APPLE_GART_2XRESET 0x10000 148 #define AGP_APPLE_GART_PERFRD 0x80000 149 150 /* 151 * Config offsets for Ali AGP chipsets. 152 */ 153 #define AGP_ALI_AGPCTRL 0xb8 154 #define AGP_ALI_ATTBASE 0xbc 155 #define AGP_ALI_TLBCTRL 0xc0 156 157 /* 158 * Config offsets for the AMD 751 chipset. 159 */ 160 #define AGP_AMD751_REGISTERS 0x14 161 #define AGP_AMD751_APCTRL 0xac 162 #define AGP_AMD751_MODECTRL 0xb0 163 #define AGP_AMD751_MODECTRL_SYNEN 0x80 164 #define AGP_AMD751_MODECTRL2 0xb2 165 #define AGP_AMD751_MODECTRL2_G1LM 0x01 166 #define AGP_AMD751_MODECTRL2_GPDCE 0x02 167 #define AGP_AMD751_MODECTRL2_NGSE 0x08 168 169 /* 170 * Memory mapped register offsets for AMD 751 chipset. 171 */ 172 #define AGP_AMD751_CAPS 0x00 173 #define AGP_AMD751_CAPS_EHI 0x0800 174 #define AGP_AMD751_CAPS_P2P 0x0400 175 #define AGP_AMD751_CAPS_MPC 0x0200 176 #define AGP_AMD751_CAPS_VBE 0x0100 177 #define AGP_AMD751_CAPS_REV 0x00ff 178 #define AGP_AMD751_STATUS 0x02 179 #define AGP_AMD751_STATUS_P2PS 0x0800 180 #define AGP_AMD751_STATUS_GCS 0x0400 181 #define AGP_AMD751_STATUS_MPS 0x0200 182 #define AGP_AMD751_STATUS_VBES 0x0100 183 #define AGP_AMD751_STATUS_P2PE 0x0008 184 #define AGP_AMD751_STATUS_GCE 0x0004 185 #define AGP_AMD751_STATUS_VBEE 0x0001 186 #define AGP_AMD751_ATTBASE 0x04 187 #define AGP_AMD751_TLBCTRL 0x0c 188 189 /* 190 * Config registers for i810 device 0 191 */ 192 #define AGP_I810_SMRAM 0x70 193 #define AGP_I810_SMRAM_GMS 0xc0 194 #define AGP_I810_SMRAM_GMS_DISABLED 0x00 195 #define AGP_I810_SMRAM_GMS_ENABLED_0 0x40 196 #define AGP_I810_SMRAM_GMS_ENABLED_512 0x80 197 #define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0 198 #define AGP_I810_MISCC 0x72 199 #define AGP_I810_MISCC_WINSIZE 0x0001 200 #define AGP_I810_MISCC_WINSIZE_64 0x0000 201 #define AGP_I810_MISCC_WINSIZE_32 0x0001 202 #define AGP_I810_MISCC_PLCK 0x0008 203 #define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000 204 #define AGP_I810_MISCC_PLCK_LOCKED 0x0008 205 #define AGP_I810_MISCC_WPTC 0x0030 206 #define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000 207 #define AGP_I810_MISCC_WPTC_62 0x0010 208 #define AGP_I810_MISCC_WPTC_50 0x0020 209 #define AGP_I810_MISCC_WPTC_37 0x0030 210 #define AGP_I810_MISCC_RPTC 0x00c0 211 #define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000 212 #define AGP_I810_MISCC_RPTC_62 0x0040 213 #define AGP_I810_MISCC_RPTC_50 0x0080 214 #define AGP_I810_MISCC_RPTC_37 0x00c0 215 216 /* 217 * Config registers for i810 device 1 218 */ 219 #define AGP_I810_GMADR 0x10 220 #define AGP_I810_MMADR 0x14 221 222 /* 223 * Memory mapped register offsets for i810 chipset. 224 */ 225 #define AGP_I810_PGTBL_CTL 0x2020 226 #define AGP_I810_PGTBL_SIZE_MASK 0x0000000e 227 #define AGP_I810_PGTBL_SIZE_512KB (0 << 1) 228 #define AGP_I810_PGTBL_SIZE_256KB (1 << 1) 229 #define AGP_I810_PGTBL_SIZE_128KB (2 << 1) 230 #define AGP_I810_DRT 0x3000 231 #define AGP_I810_DRT_UNPOPULATED 0x00 232 #define AGP_I810_DRT_POPULATED 0x01 233 #define AGP_I810_GTT 0x10000 234 235 /* 236 * Config registers for i830MG device 0 237 */ 238 #define AGP_I830_GCC0 0x50 239 #define AGP_I830_GCC1 0x52 240 #define AGP_I830_GCC1_DEV2 0x08 241 #define AGP_I830_GCC1_DEV2_ENABLED 0x00 242 #define AGP_I830_GCC1_DEV2_DISABLED 0x08 243 #define AGP_I830_GCC1_GMS 0xf0 244 #define AGP_I830_GCC1_GMS_STOLEN_512 0x20 245 #define AGP_I830_GCC1_GMS_STOLEN_1024 0x30 246 #define AGP_I830_GCC1_GMS_STOLEN_8192 0x40 247 #define AGP_I830_GCC1_GMASIZE 0x01 248 #define AGP_I830_GCC1_GMASIZE_64 0x01 249 #define AGP_I830_GCC1_GMASIZE_128 0x00 250 251 252 /* 253 * Config registers for 852GM/855GM/865G device 0 254 */ 255 #define AGP_I855_GCC1 0x50 256 #define AGP_I855_GCC1_DEV2 0x08 257 #define AGP_I855_GCC1_DEV2_ENABLED 0x00 258 #define AGP_I855_GCC1_DEV2_DISABLED 0x08 259 #define AGP_I855_GCC1_GMS 0xf0 260 #define AGP_I855_GCC1_GMS_STOLEN_0M 0x00 261 #define AGP_I855_GCC1_GMS_STOLEN_1M 0x10 262 #define AGP_I855_GCC1_GMS_STOLEN_4M 0x20 263 #define AGP_I855_GCC1_GMS_STOLEN_8M 0x30 264 #define AGP_I855_GCC1_GMS_STOLEN_16M 0x40 265 #define AGP_I855_GCC1_GMS_STOLEN_32M 0x50 266 267 /* 268 * 915G registers 269 */ 270 #define AGP_I915_GMADR 0x18 271 #define AGP_I915_MMADR 0x10 272 #define AGP_I915_GTTADR 0x1C 273 #define AGP_I915_GCC1_GMS_STOLEN_48M 0x60 274 #define AGP_I915_GCC1_GMS_STOLEN_64M 0x70 275 #define AGP_I915_DEVEN 0x54 276 #define AGP_I915_DEVEN_D2F0 0x08 277 #define AGP_I915_DEVEN_D2F0_ENABLED 0x08 278 #define AGP_I915_DEVEN_D2F0_DISABLED 0x00 279 #define AGP_I915_MSAC 0x62 280 #define AGP_I915_MSAC_GMASIZE 0x02 281 #define AGP_I915_MSAC_GMASIZE_128 0x02 282 #define AGP_I915_MSAC_GMASIZE_256 0x00 283 284 /* 285 * G965 registers 286 */ 287 #define AGP_I965_GMADR 0x18 288 #define AGP_I965_MMADR 0x10 289 #define AGP_I965_MSAC 0x62 290 #define AGP_I965_MSAC_GMASIZE 0x06 291 #define AGP_I965_MSAC_GMASIZE_128 0x00 292 #define AGP_I965_MSAC_GMASIZE_256 0x02 293 #define AGP_I965_MSAC_GMASIZE_512 0x06 294 #define AGP_I965_GTT 0x80000 295 296 /* 297 * G33 registers 298 */ 299 #define AGP_G33_GCC1_GMS_STOLEN_128M 0x80 300 #define AGP_G33_GCC1_GMS_STOLEN_256M 0x90 301 #define AGP_G33_PGTBL_SIZE_MASK (3U << 8) 302 #define AGP_G33_PGTBL_SIZE_1M (1U << 8) 303 #define AGP_G33_PGTBL_SIZE_2M (2U << 8) 304 305 /* 306 * Intel 4-series registers and values 307 */ 308 #define AGP_INTEL_GMCH_GMS_STOLEN_96M 0xa0 309 #define AGP_INTEL_GMCH_GMS_STOLEN_160M 0xb0 310 #define AGP_INTEL_GMCH_GMS_STOLEN_224M 0xc0 311 #define AGP_INTEL_GMCH_GMS_STOLEN_352M 0xd0 312 #define AGP_G4X_GTT 0x200000 313 314 /* 315 * Intel Sandybridge registers and values 316 */ 317 #define AGP_INTEL_SNB_GMCH_CTRL 0x50 318 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_MASK 0xF8 319 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_32M (1 << 3) 320 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_64M (2 << 3) 321 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_96M (3 << 3) 322 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_128M (4 << 3) 323 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_160M (5 << 3) 324 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_192M (6 << 3) 325 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_224M (7 << 3) 326 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_256M (8 << 3) 327 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_288M (9 << 3) 328 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_320M (0xa << 3) 329 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_352M (0xb << 3) 330 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_384M (0xc << 3) 331 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_416M (0xd << 3) 332 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_448M (0xe << 3) 333 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_480M (0xf << 3) 334 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_512M (0x10 << 3) 335 336 #endif /* !_PCI_AGPREG_H_ */ 337