1 /* $OpenBSD: ahcireg.h,v 1.6 2024/04/23 13:09:21 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org> 5 * Copyright (c) 2010 Conformal Systems LLC <info@conformal.com> 6 * Copyright (c) 2010 Jonathan Matthew <jonathan@d14n.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #define AHCI_REG_CAP 0x000 /* HBA Capabilities */ 22 #define AHCI_REG_CAP_NP(_r) (((_r) & 0x1f)+1) /* Number of Ports */ 23 #define AHCI_REG_CAP_SXS (1<<5) /* External SATA */ 24 #define AHCI_REG_CAP_EMS (1<<6) /* Enclosure Mgmt */ 25 #define AHCI_REG_CAP_CCCS (1<<7) /* Cmd Coalescing */ 26 #define AHCI_REG_CAP_NCS(_r) ((((_r) & 0x1f00)>>8)+1) /* NCmds*/ 27 #define AHCI_REG_CAP_PSC (1<<13) /* Partial State Capable */ 28 #define AHCI_REG_CAP_SSC (1<<14) /* Slumber State Capable */ 29 #define AHCI_REG_CAP_PMD (1<<15) /* PIO Multiple DRQ Block */ 30 #define AHCI_REG_CAP_FBSS (1<<16) /* FIS-Based Switching */ 31 #define AHCI_REG_CAP_SPM (1<<17) /* Port Multiplier */ 32 #define AHCI_REG_CAP_SAM (1<<18) /* AHCI Only mode */ 33 #define AHCI_REG_CAP_SNZO (1<<19) /* Non Zero DMA Offsets */ 34 #define AHCI_REG_CAP_ISS (0xf<<20) /* Interface Speed Support */ 35 #define AHCI_REG_CAP_ISS_G1 (0x1<<20) /* Gen 1 (1.5 Gbps) */ 36 #define AHCI_REG_CAP_ISS_G2 (0x2<<20) /* Gen 2 (3 Gbps) */ 37 #define AHCI_REG_CAP_ISS_G3 (0x3<<20) /* Gen 3 (6 Gbps) */ 38 #define AHCI_REG_CAP_SCLO (1<<24) /* Cmd List Override */ 39 #define AHCI_REG_CAP_SAL (1<<25) /* Activity LED */ 40 #define AHCI_REG_CAP_SALP (1<<26) /* Aggressive Link Pwr Mgmt */ 41 #define AHCI_REG_CAP_SSS (1<<27) /* Staggered Spinup */ 42 #define AHCI_REG_CAP_SMPS (1<<28) /* Mech Presence Switch */ 43 #define AHCI_REG_CAP_SSNTF (1<<29) /* SNotification Register */ 44 #define AHCI_REG_CAP_SNCQ (1<<30) /* Native Cmd Queuing */ 45 #define AHCI_REG_CAP_S64A (1U<<31) /* 64bit Addressing */ 46 #define AHCI_FMT_CAP "\020" "\040S64A" "\037NCQ" "\036SSNTF" \ 47 "\035SMPS" "\034SSS" "\033SALP" "\032SAL" \ 48 "\031SCLO" "\024SNZO" "\023SAM" "\022SPM" \ 49 "\021FBSS" "\020PMD" "\017SSC" "\016PSC" \ 50 "\010CCCS" "\007EMS" "\006SXS" 51 #define AHCI_REG_GHC 0x004 /* Global HBA Control */ 52 #define AHCI_REG_GHC_HR (1<<0) /* HBA Reset */ 53 #define AHCI_REG_GHC_IE (1<<1) /* Interrupt Enable */ 54 #define AHCI_REG_GHC_MRSM (1<<2) /* MSI Revert to Single Msg */ 55 #define AHCI_REG_GHC_AE (1U<<31) /* AHCI Enable */ 56 #define AHCI_FMT_GHC "\020" "\040AE" "\003MRSM" "\002IE" "\001HR" 57 #define AHCI_REG_IS 0x008 /* Interrupt Status */ 58 #define AHCI_REG_PI 0x00c /* Ports Implemented */ 59 #define AHCI_REG_VS 0x010 /* AHCI Version */ 60 #define AHCI_REG_VS_0_95 0x00000905 /* 0.95 */ 61 #define AHCI_REG_VS_1_0 0x00010000 /* 1.0 */ 62 #define AHCI_REG_VS_1_1 0x00010100 /* 1.1 */ 63 #define AHCI_REG_VS_1_2 0x00010200 /* 1.2 */ 64 #define AHCI_REG_VS_1_3 0x00010300 /* 1.3 */ 65 #define AHCI_REG_VS_1_3_1 0x00010301 /* 1.3.1 */ 66 #define AHCI_REG_CCC_CTL 0x014 /* Coalescing Control */ 67 #define AHCI_REG_CCC_CTL_INT(_r) (((_r) & 0xf8) >> 3) /* CCC INT slot */ 68 #define AHCI_REG_CCC_PORTS 0x018 /* Coalescing Ports */ 69 #define AHCI_REG_EM_LOC 0x01c /* Enclosure Mgmt Location */ 70 #define AHCI_REG_EM_CTL 0x020 /* Enclosure Mgmt Control */ 71 72 #define AHCI_REG_CAP2 0x024 /* HBA Capabilities Extended */ 73 #define AHCI_REG_CAP2_DESO (1<<5) /* DevSlp from slumber only */ 74 #define AHCI_REG_CAP2_SADM (1<<4) /* Aggro DevSlp mgmt */ 75 #define AHCI_REG_CAP2_SDS (1<<3) /* Supports DevSlp */ 76 #define AHCI_REG_CAP2_APST (1<<2) /* Auto partial->slumber */ 77 #define AHCI_REG_CAP2_NVMP (1<<1) /* NVMHCI present */ 78 #define AHCI_REG_CAP2_BOH (1<<0) /* BIOS/OS handoff */ 79 #define AHCI_FMT_CAP2 "\020" "\006DESO" "\005SADM" "\004SDS" \ 80 "\003APST" "\002NVMP" "\001BOH" 81 82 #define AHCI_PORT_REGION(_p) (0x100 + ((_p) * 0x80)) 83 #define AHCI_PORT_SIZE 0x80 84 85 #define AHCI_PREG_CLB 0x00 /* Cmd List Base Addr */ 86 #define AHCI_PREG_CLBU 0x04 /* Cmd List Base Hi Addr */ 87 #define AHCI_PREG_FB 0x08 /* FIS Base Addr */ 88 #define AHCI_PREG_FBU 0x0c /* FIS Base Hi Addr */ 89 #define AHCI_PREG_IS 0x10 /* Interrupt Status */ 90 #define AHCI_PREG_IS_DHRS (1<<0) /* Device to Host FIS */ 91 #define AHCI_PREG_IS_PSS (1<<1) /* PIO Setup FIS */ 92 #define AHCI_PREG_IS_DSS (1<<2) /* DMA Setup FIS */ 93 #define AHCI_PREG_IS_SDBS (1<<3) /* Set Device Bits FIS */ 94 #define AHCI_PREG_IS_UFS (1<<4) /* Unknown FIS */ 95 #define AHCI_PREG_IS_DPS (1<<5) /* Descriptor Processed */ 96 #define AHCI_PREG_IS_PCS (1<<6) /* Port Change */ 97 #define AHCI_PREG_IS_DMPS (1<<7) /* Device Mechanical Presence */ 98 #define AHCI_PREG_IS_PRCS (1<<22) /* PhyRdy Change */ 99 #define AHCI_PREG_IS_IPMS (1<<23) /* Incorrect Port Multiplier */ 100 #define AHCI_PREG_IS_OFS (1<<24) /* Overflow */ 101 #define AHCI_PREG_IS_INFS (1<<26) /* Interface Non-fatal Error */ 102 #define AHCI_PREG_IS_IFS (1<<27) /* Interface Fatal Error */ 103 #define AHCI_PREG_IS_HBDS (1<<28) /* Host Bus Data Error */ 104 #define AHCI_PREG_IS_HBFS (1<<29) /* Host Bus Fatal Error */ 105 #define AHCI_PREG_IS_TFES (1<<30) /* Task File Error */ 106 #define AHCI_PREG_IS_CPDS (1U<<31) /* Cold Presence Detect */ 107 #define AHCI_PFMT_IS "\20" "\040CPDS" "\037TFES" "\036HBFS" \ 108 "\035HBDS" "\034IFS" "\033INFS" "\031OFS" \ 109 "\030IPMS" "\027PRCS" "\010DMPS" "\006DPS" \ 110 "\007PCS" "\005UFS" "\004SDBS" "\003DSS" \ 111 "\002PSS" "\001DHRS" 112 #define AHCI_PREG_IE 0x14 /* Interrupt Enable */ 113 #define AHCI_PREG_IE_DHRE (1<<0) /* Device to Host FIS */ 114 #define AHCI_PREG_IE_PSE (1<<1) /* PIO Setup FIS */ 115 #define AHCI_PREG_IE_DSE (1<<2) /* DMA Setup FIS */ 116 #define AHCI_PREG_IE_SDBE (1<<3) /* Set Device Bits FIS */ 117 #define AHCI_PREG_IE_UFE (1<<4) /* Unknown FIS */ 118 #define AHCI_PREG_IE_DPE (1<<5) /* Descriptor Processed */ 119 #define AHCI_PREG_IE_PCE (1<<6) /* Port Change */ 120 #define AHCI_PREG_IE_DMPE (1<<7) /* Device Mechanical Presence */ 121 #define AHCI_PREG_IE_PRCE (1<<22) /* PhyRdy Change */ 122 #define AHCI_PREG_IE_IPME (1<<23) /* Incorrect Port Multiplier */ 123 #define AHCI_PREG_IE_OFE (1<<24) /* Overflow */ 124 #define AHCI_PREG_IE_INFE (1<<26) /* Interface Non-fatal Error */ 125 #define AHCI_PREG_IE_IFE (1<<27) /* Interface Fatal Error */ 126 #define AHCI_PREG_IE_HBDE (1<<28) /* Host Bus Data Error */ 127 #define AHCI_PREG_IE_HBFE (1<<29) /* Host Bus Fatal Error */ 128 #define AHCI_PREG_IE_TFEE (1<<30) /* Task File Error */ 129 #define AHCI_PREG_IE_CPDE (1U<<31) /* Cold Presence Detect */ 130 #define AHCI_PFMT_IE "\20" "\040CPDE" "\037TFEE" "\036HBFE" \ 131 "\035HBDE" "\034IFE" "\033INFE" "\031OFE" \ 132 "\030IPME" "\027PRCE" "\010DMPE" "\007PCE" \ 133 "\006DPE" "\005UFE" "\004SDBE" "\003DSE" \ 134 "\002PSE" "\001DHRE" 135 #define AHCI_PREG_CMD 0x18 /* Command and Status */ 136 #define AHCI_PREG_CMD_ST (1<<0) /* Start */ 137 #define AHCI_PREG_CMD_SUD (1<<1) /* Spin Up Device */ 138 #define AHCI_PREG_CMD_POD (1<<2) /* Power On Device */ 139 #define AHCI_PREG_CMD_CLO (1<<3) /* Command List Override */ 140 #define AHCI_PREG_CMD_FRE (1<<4) /* FIS Receive Enable */ 141 #define AHCI_PREG_CMD_CCS(_r) (((_r) >> 8) & 0x1f) /* Curr CmdSlot# */ 142 #define AHCI_PREG_CMD_MPSS (1<<13) /* Mech Presence State */ 143 #define AHCI_PREG_CMD_FR (1<<14) /* FIS Receive Running */ 144 #define AHCI_PREG_CMD_CR (1<<15) /* Command List Running */ 145 #define AHCI_PREG_CMD_CPS (1<<16) /* Cold Presence State */ 146 #define AHCI_PREG_CMD_PMA (1<<17) /* Port Multiplier Attached */ 147 #define AHCI_PREG_CMD_HPCP (1<<18) /* Hot Plug Capable */ 148 #define AHCI_PREG_CMD_MPSP (1<<19) /* Mech Presence Switch */ 149 #define AHCI_PREG_CMD_CPD (1<<20) /* Cold Presence Detection */ 150 #define AHCI_PREG_CMD_ESP (1<<21) /* External SATA Port */ 151 #define AHCI_PREG_CMD_ATAPI (1<<24) /* Device is ATAPI */ 152 #define AHCI_PREG_CMD_DLAE (1<<25) /* Drv LED on ATAPI Enable */ 153 #define AHCI_PREG_CMD_ALPE (1<<26) /* Aggro Pwr Mgmt Enable */ 154 #define AHCI_PREG_CMD_ASP (1<<27) /* Aggro Slumber/Partial */ 155 #define AHCI_PREG_CMD_ICC 0xf0000000 /* Interface Comm Ctrl */ 156 #define AHCI_PREG_CMD_ICC_SLUMBER 0x60000000 157 #define AHCI_PREG_CMD_ICC_PARTIAL 0x20000000 158 #define AHCI_PREG_CMD_ICC_ACTIVE 0x10000000 159 #define AHCI_PREG_CMD_ICC_IDLE 0x00000000 160 #define AHCI_PFMT_CMD "\020" "\034ASP" "\033ALPE" "\032DLAE" \ 161 "\031ATAPI" "\026ESP" "\025CPD" "\024MPSP" \ 162 "\023HPCP" "\022PMA" "\021CPS" "\020CR" \ 163 "\017FR" "\016MPSS" "\005FRE" "\004CLO" \ 164 "\003POD" "\002SUD" "\001ST" 165 #define AHCI_PREG_TFD 0x20 /* Task File Data*/ 166 #define AHCI_PREG_TFD_STS 0xff 167 #define AHCI_PREG_TFD_STS_ERR (1<<0) 168 #define AHCI_PREG_TFD_STS_DRQ (1<<3) 169 #define AHCI_PREG_TFD_STS_BSY (1<<7) 170 #define AHCI_PREG_TFD_ERR 0xff00 171 #define AHCI_PFMT_TFD_STS "\20" "\010BSY" "\004DRQ" "\001ERR" 172 #define AHCI_PREG_SIG 0x24 /* Signature */ 173 #define AHCI_PREG_SSTS 0x28 /* SATA Status */ 174 #define AHCI_PREG_SSTS_DET 0xf /* Device Detection */ 175 #define AHCI_PREG_SSTS_DET_NONE 0x0 176 #define AHCI_PREG_SSTS_DET_DEV_NE 0x1 177 #define AHCI_PREG_SSTS_DET_DEV 0x3 178 #define AHCI_PREG_SSTS_DET_PHYOFFLINE 0x4 179 #define AHCI_PREG_SSTS_SPD 0xf0 /* Current Interface Speed */ 180 #define AHCI_PREG_SSTS_SPD_NONE 0x00 181 #define AHCI_PREG_SSTS_SPD_GEN1 0x10 182 #define AHCI_PREG_SSTS_SPD_GEN2 0x20 183 #define AHCI_PREG_SSTS_SPD_GEN3 0x30 184 #define AHCI_PREG_SSTS_IPM 0xf00 /* Interface Power Management */ 185 #define AHCI_PREG_SSTS_IPM_NONE 0x000 186 #define AHCI_PREG_SSTS_IPM_ACTIVE 0x100 187 #define AHCI_PREG_SSTS_IPM_PARTIAL 0x200 188 #define AHCI_PREG_SSTS_IPM_SLUMBER 0x600 189 #define AHCI_PREG_SCTL 0x2c /* SATA Control */ 190 #define AHCI_PREG_SCTL_DET 0xf /* Device Detection */ 191 #define AHCI_PREG_SCTL_DET_NONE 0x0 192 #define AHCI_PREG_SCTL_DET_INIT 0x1 193 #define AHCI_PREG_SCTL_DET_DISABLE 0x4 194 #define AHCI_PREG_SCTL_SPD 0xf0 /* Speed Allowed */ 195 #define AHCI_PREG_SCTL_SPD_ANY 0x00 196 #define AHCI_PREG_SCTL_SPD_GEN1 0x10 197 #define AHCI_PREG_SCTL_SPD_GEN2 0x20 198 #define AHCI_PREG_SCTL_SPD_GEN3 0x30 199 #define AHCI_PREG_SCTL_IPM 0xf00 /* Interface Power Management */ 200 #define AHCI_PREG_SCTL_IPM_NONE 0x000 201 #define AHCI_PREG_SCTL_IPM_NOPARTIAL 0x100 202 #define AHCI_PREG_SCTL_IPM_NOSLUMBER 0x200 203 #define AHCI_PREG_SCTL_IPM_DISABLED 0x300 204 #define AHCI_PREG_SERR 0x30 /* SATA Error */ 205 #define AHCI_PREG_SERR_ERR(_r) ((_r) & 0xffff) 206 #define AHCI_PREG_SERR_ERR_I (1<<0) /* Recovered Data Integrity */ 207 #define AHCI_PREG_SERR_ERR_M (1<<1) /* Recovered Communications */ 208 #define AHCI_PREG_SERR_ERR_T (1<<8) /* Transient Data Integrity */ 209 #define AHCI_PREG_SERR_ERR_C (1<<9) /* Persistent Comm/Data */ 210 #define AHCI_PREG_SERR_ERR_P (1<<10) /* Protocol */ 211 #define AHCI_PREG_SERR_ERR_E (1<<11) /* Internal */ 212 #define AHCI_PFMT_SERR_ERR "\020" "\014E" "\013P" "\012C" "\011T" "\002M" \ 213 "\001I" 214 #define AHCI_PREG_SERR_DIAG(_r) (((_r) >> 16) & 0xffff) 215 #define AHCI_PREG_SERR_DIAG_N (1<<0) /* PhyRdy Change */ 216 #define AHCI_PREG_SERR_DIAG_I (1<<1) /* Phy Internal Error */ 217 #define AHCI_PREG_SERR_DIAG_W (1<<2) /* Comm Wake */ 218 #define AHCI_PREG_SERR_DIAG_B (1<<3) /* 10B to 8B Decode Error */ 219 #define AHCI_PREG_SERR_DIAG_D (1<<4) /* Disparity Error */ 220 #define AHCI_PREG_SERR_DIAG_C (1<<5) /* CRC Error */ 221 #define AHCI_PREG_SERR_DIAG_H (1<<6) /* Handshake Error */ 222 #define AHCI_PREG_SERR_DIAG_S (1<<7) /* Link Sequence Error */ 223 #define AHCI_PREG_SERR_DIAG_T (1<<8) /* Transport State Trans Err */ 224 #define AHCI_PREG_SERR_DIAG_F (1<<9) /* Unknown FIS Type */ 225 #define AHCI_PREG_SERR_DIAG_X (1<<10) /* Exchanged */ 226 #define AHCI_PFMT_SERR_DIAG "\020" "\013X" "\012F" "\011T" "\010S" "\007H" \ 227 "\006C" "\005D" "\004B" "\003W" "\002I" \ 228 "\001N" 229 #define AHCI_PREG_SACT 0x34 /* SATA Active */ 230 #define AHCI_PREG_CI 0x38 /* Command Issue */ 231 #define AHCI_PREG_CI_ALL_SLOTS 0xffffffff 232 #define AHCI_PREG_SNTF 0x3c /* SNotification */ 233 234 #define AHCI_PREG_FBS 0x40 /* FIS-based Switching Control */ 235 #define AHCI_PREG_FBS_DWE 0xf0000 /* Device With Error */ 236 #define AHCI_PREG_FBS_ADO 0xf000 /* Active Device Optimization */ 237 #define AHCI_PREG_FBS_DEV 0xf00 /* Device To Issue */ 238 #define AHCI_PREG_FBS_SDE (1<<2) /* Single Device Error */ 239 #define AHCI_PREG_FBS_DEC (1<<1) /* Device Error Clear */ 240 #define AHCI_PREG_FBS_EN (1<<0) /* Enable */ 241 242 struct ahci_cmd_hdr { 243 u_int16_t flags; 244 #define AHCI_CMD_LIST_FLAG_CFL 0x001f /* Command FIS Length */ 245 #define AHCI_CMD_LIST_FLAG_A (1<<5) /* ATAPI */ 246 #define AHCI_CMD_LIST_FLAG_W (1<<6) /* Write */ 247 #define AHCI_CMD_LIST_FLAG_P (1<<7) /* Prefetchable */ 248 #define AHCI_CMD_LIST_FLAG_R (1<<8) /* Reset */ 249 #define AHCI_CMD_LIST_FLAG_B (1<<9) /* BIST */ 250 #define AHCI_CMD_LIST_FLAG_C (1<<10) /* Clear Busy upon R_OK */ 251 #define AHCI_CMD_LIST_FLAG_PMP 0xf000 /* Port Multiplier Port */ 252 #define AHCI_CMD_LIST_FLAG_PMP_SHIFT 12 253 u_int16_t prdtl; /* sgl len */ 254 255 u_int32_t prdbc; /* transferred byte count */ 256 257 u_int64_t ctba; 258 259 u_int32_t reserved[4]; 260 } __packed __aligned(8); 261 262 struct ahci_rfis { 263 u_int8_t dsfis[28]; 264 u_int8_t reserved1[4]; 265 u_int8_t psfis[24]; 266 u_int8_t reserved2[8]; 267 u_int8_t rfis[24]; 268 u_int8_t reserved3[4]; 269 u_int8_t sdbfis[4]; 270 u_int8_t ufis[64]; 271 u_int8_t reserved4[96]; 272 } __packed; 273 274 struct ahci_prdt { 275 u_int64_t dba; 276 u_int32_t reserved; 277 u_int32_t flags; 278 #define AHCI_PRDT_FLAG_INTR (1U<<31) /* interrupt on completion */ 279 } __packed __aligned(8); 280 281 /* this makes ahci_cmd_table 512 bytes, supporting 128-byte alignment */ 282 #define AHCI_MAX_PRDT 24 283 284 struct ahci_cmd_table { 285 u_int8_t cfis[64]; /* Command FIS */ 286 u_int8_t acmd[16]; /* ATAPI Command */ 287 u_int8_t reserved[48]; 288 289 struct ahci_prdt prdt[AHCI_MAX_PRDT]; 290 } __packed __aligned(128); 291 292 #define AHCI_MAX_PORTS 32 293