1 /* 2 * THIS FILE IS AUTOMATICALLY GENERATED 3 * DONT EDIT THIS FILE 4 */ 5 6 /* $OpenBSD: cn30xxasxreg.h,v 1.3 2022/12/28 01:39:21 yasuoka Exp $ */ 7 8 /* 9 * Copyright (c) 2007 Internet Initiative Japan, Inc. 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* 35 * Cavium Networks OCTEON CN30XX Hardware Reference Manual 36 * CN30XX-HM-1.0 37 * 13.9 ASX Registers 38 */ 39 40 #ifndef _CN30XXASXREG_H_ 41 #define _CN30XXASXREG_H_ 42 43 #define ASX0_RX_PRT_EN 0x00011800b0000000ULL 44 #define ASX0_TX_PRT_EN 0x00011800b0000008ULL 45 #define ASX0_INT_REG 0x00011800b0000010ULL 46 #define ASX0_INT_EN 0x00011800b0000018ULL 47 #define ASX0_RX_CLK_SET0 0x00011800b0000020ULL 48 #define ASX0_RX_CLK_SET1 0x00011800b0000028ULL 49 #define ASX0_RX_CLK_SET2 0x00011800b0000030ULL 50 #define ASX0_PRT_LOOP 0x00011800b0000040ULL 51 #define ASX0_TX_CLK_SET0 0x00011800b0000048ULL 52 #define ASX0_TX_CLK_SET1 0x00011800b0000050ULL 53 #define ASX0_TX_CLK_SET2 0x00011800b0000058ULL 54 #define ASX0_COMP_BYP 0x00011800b0000068ULL 55 #define ASX0_TX_HI_WATER000 0x00011800b0000080ULL 56 #define ASX0_TX_HI_WATER001 0x00011800b0000088ULL 57 #define ASX0_TX_HI_WATER002 0x00011800b0000090ULL 58 #define ASX0_GMII_RX_CLK_SET 0x00011800b0000180ULL 59 #define ASX0_GMII_RX_DAT_SET 0x00011800b0000188ULL 60 #define ASX0_MII_RX_DAT_SET 0x00011800b0000190ULL 61 62 #define ASX0_BASE 0x00011800b0000000ULL 63 #define ASX0_SIZE 0x0198ULL 64 65 #define ASX0_RX_PRT_EN_OFFSET 0x0000 66 #define ASX0_TX_PRT_EN_OFFSET 0x0008 67 #define ASX0_INT_REG_OFFSET 0x0010 68 #define ASX0_INT_EN_OFFSET 0x0018 69 #define ASX0_RX_CLK_SET0_OFFSET 0x0020 70 #define ASX0_RX_CLK_SET1_OFFSET 0x0028 71 #define ASX0_RX_CLK_SET2_OFFSET 0x0030 72 #define ASX0_PRT_LOOP_OFFSET 0x0040 73 #define ASX0_TX_CLK_SET0_OFFSET 0x0048 74 #define ASX0_TX_CLK_SET1_OFFSET 0x0050 75 #define ASX0_TX_CLK_SET2_OFFSET 0x0058 76 #define ASX0_COMP_BYP_OFFSET 0x0068 77 #define ASX0_TX_HI_WATER000_OFFSET 0x0080 78 #define ASX0_TX_HI_WATER001_OFFSET 0x0088 79 #define ASX0_TX_HI_WATER002_OFFSET 0x0090 80 #define ASX0_GMII_RX_CLK_SET_OFFSET 0x0180 81 #define ASX0_GMII_RX_DAT_SET_OFFSET 0x0188 82 #define ASX0_MII_RX_DAT_SET_OFFSET 0x0190 83 84 /* XXX */ 85 86 87 /* 88 * ASX_RX_PRT_EN 89 */ 90 #define ASX0_RX_PRT_EN_63_3 0xfffffff8 91 #define ASX0_RX_PRT_EN_PRT_EN 0x00000007 92 93 /* 94 * ASX0_TX_PRT_EN 95 */ 96 #define ASX0_TX_PRT_EN_63_3 0xfffffff8 97 #define ASX0_TX_PRT_EN_PRT_EN 0x00000007 98 99 /* 100 * ASX0_INT_REG 101 */ 102 #define ASX0_INT_REG_63_11 0xfffff800 103 #define ASX0_INT_REG_TXPSH 0x00000700 104 #define ASX0_INT_REG_7 0x00000080 105 #define ASX0_INT_REG_TXPOP 0x00000070 106 #define ASX0_INT_REG_3 0x00000008 107 #define ASX0_INT_REG_OVRFLW 0x00000007 108 109 /* 110 * ASX0_INT_EN 111 */ 112 #define ASX0_INT_EN_63_11 0xfffff800 113 #define ASX0_INT_EN_TXPSH 0x00000700 114 #define ASX0_INT_EN_7 0x00000080 115 #define ASX0_INT_EN_TXPOP 0x00000070 116 #define ASX0_INT_EN_3 0x00000008 117 #define ASX0_INT_EN_OVRFLW 0x00000007 118 119 /* 120 * ASX0_RX_CLK_SET 121 */ 122 #define ASX0_RX_CLK_SET_63_5 0xffffffe0 123 #define ASX0_RX_CLK_SET_SETTING 0x0000001f 124 125 /* 126 * ASX0_RRT_LOOP 127 */ 128 #define ASX0_PRT_LOOP_63_7 0xffffff80 129 #define ASX0_PRT_LOOP_EXT_LOOP 0x00000070 130 #define ASX0_PRT_LOOP_3 0x00000008 131 #define ASX0_PRT_LOOP_PRT_LOOP 0x00000007 132 133 /* 134 * ASX0_TX_CLK_SET 135 */ 136 #define ASX0_TX_CLK_SET_63_5 0xffffffe0 137 #define ASX0_TX_CLK_SET_SETTING 0x0000001f 138 139 /* 140 * ASX0_TX_COMP_BYP 141 */ 142 #define ASX0_TX_COMP_BYP_63_9 0xfffffe00 143 #define ASX0_TX_COMP_BYP_BYPASS 0x00000100 144 #define ASX0_TX_COMP_BYP_PCTL 0x000000f0 145 #define ASX0_TX_COMP_BYP_NCTL 0x0000000f 146 147 /* 148 * ASX0_TX_HI_WATER 149 */ 150 #define ASX0_TX_HI_WATER_63_3 0xfffffff8 151 #define ASX0_TX_HI_WATER_MARK 0x00000007 152 153 /* 154 * ASX0_GMXII_RX_CLK_SET 155 */ 156 #define ASX0_GMII_RX_CLK_SET_63_5 0xffffffe0 157 #define ASX0_GMII_RX_CLK_SET_SETTING 0x0000001f 158 159 /* 160 * ASX0_GMXII_RX_DAT_SET 161 */ 162 #define ASX0_GMII_RX_DAT_SET_63_5 0xffffffe0 163 #define ASX0_GMII_RX_DAT_SET_SETTING 0x0000001f 164 165 #endif /* _CN30XXASXREG_H_ */ 166