1 /* $OpenBSD: if_qwz_pci.c,v 1.6 2024/12/09 09:35:33 patrick Exp $ */
2
3 /*
4 * Copyright 2023 Stefan Sperling <stsp@openbsd.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 /*
20 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc.
21 * Copyright (c) 2018-2021 The Linux Foundation.
22 * All rights reserved.
23 *
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted (subject to the limitations in the disclaimer
26 * below) provided that the following conditions are met:
27 *
28 * * Redistributions of source code must retain the above copyright notice,
29 * this list of conditions and the following disclaimer.
30 *
31 * * Redistributions in binary form must reproduce the above copyright
32 * notice, this list of conditions and the following disclaimer in the
33 * documentation and/or other materials provided with the distribution.
34 *
35 * * Neither the name of [Owner Organization] nor the names of its
36 * contributors may be used to endorse or promote products derived from
37 * this software without specific prior written permission.
38 *
39 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY
40 * THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
41 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
42 * NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
43 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
44 * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
45 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
46 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
47 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
48 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
49 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
50 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 */
52
53 #include "bpfilter.h"
54
55 #include <sys/param.h>
56 #include <sys/mbuf.h>
57 #include <sys/lock.h>
58 #include <sys/socket.h>
59 #include <sys/systm.h>
60 #include <sys/malloc.h>
61 #include <sys/device.h>
62 #include <sys/endian.h>
63
64 #include <machine/bus.h>
65 #include <machine/intr.h>
66
67 #include <net/if.h>
68 #include <net/if_media.h>
69
70 #include <netinet/in.h>
71 #include <netinet/if_ether.h>
72
73 #include <net80211/ieee80211_var.h>
74 #include <net80211/ieee80211_radiotap.h>
75
76 #include <dev/pci/pcireg.h>
77 #include <dev/pci/pcivar.h>
78 #include <dev/pci/pcidevs.h>
79
80 /* XXX linux porting goo */
81 #ifdef __LP64__
82 #define BITS_PER_LONG 64
83 #else
84 #define BITS_PER_LONG 32
85 #endif
86 #define GENMASK(h, l) (((~0UL) >> (BITS_PER_LONG - (h) - 1)) & ((~0UL) << (l)))
87 #define __bf_shf(x) (__builtin_ffsll(x) - 1)
88 #define FIELD_GET(_m, _v) ((typeof(_m))(((_v) & (_m)) >> __bf_shf(_m)))
89 #define BIT(x) (1UL << (x))
90 #define test_bit(i, a) ((a) & (1 << (i)))
91 #define clear_bit(i, a) ((a)) &= ~(1 << (i))
92 #define set_bit(i, a) ((a)) |= (1 << (i))
93
94 /* #define QWZ_DEBUG */
95
96 #include <dev/ic/qwzreg.h>
97 #include <dev/ic/qwzvar.h>
98
99 #ifdef QWZ_DEBUG
100 /* Headers needed for RDDM dump */
101 #include <sys/namei.h>
102 #include <sys/pledge.h>
103 #include <sys/vnode.h>
104 #include <sys/fcntl.h>
105 #include <sys/stat.h>
106 #include <sys/proc.h>
107 #endif
108
109 #define ATH12K_PCI_IRQ_CE0_OFFSET 3
110 #define ATH12K_PCI_IRQ_DP_OFFSET 14
111
112 #define ATH12K_PCI_CE_WAKE_IRQ 2
113
114 #define ATH12K_PCI_WINDOW_ENABLE_BIT 0x40000000
115 #define ATH12K_PCI_WINDOW_REG_ADDRESS 0x310c
116 #define ATH12K_PCI_WINDOW_VALUE_MASK GENMASK(24, 19)
117 #define ATH12K_PCI_WINDOW_START 0x80000
118 #define ATH12K_PCI_WINDOW_RANGE_MASK GENMASK(18, 0)
119 #define ATH12K_PCI_WINDOW_STATIC_MASK GENMASK(31, 6)
120
121 /* BAR0 + 4k is always accessible, and no need to force wakeup. */
122 #define ATH12K_PCI_ACCESS_ALWAYS_OFF 0xFE0 /* 4K - 32 = 0xFE0 */
123
124 #define TCSR_SOC_HW_VERSION 0x1b00000
125 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)
126 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0)
127
128 /*
129 * pci.h
130 */
131 #define PCIE_SOC_GLOBAL_RESET 0x3008
132 #define PCIE_SOC_GLOBAL_RESET_V 1
133
134 #define WLAON_WARM_SW_ENTRY 0x1f80504
135 #define WLAON_SOC_RESET_CAUSE_REG 0x01f8060c
136
137 #define PCIE_Q6_COOKIE_ADDR 0x01f80500
138 #define PCIE_Q6_COOKIE_DATA 0xc0000000
139
140 /* register to wake the UMAC from power collapse */
141 #define PCIE_SCRATCH_0_SOC_PCIE_REG 0x4040
142
143 /* register used for handshake mechanism to validate UMAC is awake */
144 #define PCIE_SOC_WAKE_PCIE_LOCAL_REG 0x3004
145
146 #define PCIE_PCIE_PARF_LTSSM 0x1e081b0
147 #define PARM_LTSSM_VALUE 0x111
148
149 #define GCC_GCC_PCIE_HOT_RST 0x1e38338
150 #define GCC_GCC_PCIE_HOT_RST_VAL 0x10
151
152 #define PCIE_PCIE_INT_ALL_CLEAR 0x1e08228
153 #define PCIE_SMLH_REQ_RST_LINK_DOWN 0x2
154 #define PCIE_INT_CLEAR_ALL 0xffffffff
155
156 #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(sc) \
157 (sc->hw_params.regs->pcie_qserdes_sysclk_en_sel)
158 #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL 0x10
159 #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK 0xffffffff
160 #define PCIE_PCS_OSC_DTCT_CONFIG1_REG(sc) \
161 (sc->hw_params.regs->pcie_pcs_osc_dtct_config_base)
162 #define PCIE_PCS_OSC_DTCT_CONFIG1_VAL 0x02
163 #define PCIE_PCS_OSC_DTCT_CONFIG2_REG(sc) \
164 (sc->hw_params.regs->pcie_pcs_osc_dtct_config_base + 0x4)
165 #define PCIE_PCS_OSC_DTCT_CONFIG2_VAL 0x52
166 #define PCIE_PCS_OSC_DTCT_CONFIG4_REG(sc) \
167 (sc->hw_params.regs->pcie_pcs_osc_dtct_config_base + 0xc)
168 #define PCIE_PCS_OSC_DTCT_CONFIG4_VAL 0xff
169 #define PCIE_PCS_OSC_DTCT_CONFIG_MSK 0x000000ff
170
171 #define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c
172 #define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4
173
174 #define PCI_MHIREGLEN_REG 0x1e0e100
175 #define PCI_MHI_REGION_END 0x1e0effc
176
177 /*
178 * mhi.h
179 */
180 #define PCIE_TXVECDB 0x360
181 #define PCIE_TXVECSTATUS 0x368
182 #define PCIE_RXVECDB 0x394
183 #define PCIE_RXVECSTATUS 0x39C
184
185 #define MHI_CHAN_CTX_CHSTATE_MASK GENMASK(7, 0)
186 #define MHI_CHAN_CTX_CHSTATE_DISABLED 0
187 #define MHI_CHAN_CTX_CHSTATE_ENABLED 1
188 #define MHI_CHAN_CTX_CHSTATE_RUNNING 2
189 #define MHI_CHAN_CTX_CHSTATE_SUSPENDED 3
190 #define MHI_CHAN_CTX_CHSTATE_STOP 4
191 #define MHI_CHAN_CTX_CHSTATE_ERROR 5
192 #define MHI_CHAN_CTX_BRSTMODE_MASK GENMASK(9, 8)
193 #define MHI_CHAN_CTX_BRSTMODE_SHFT 8
194 #define MHI_CHAN_CTX_BRSTMODE_DISABLE 2
195 #define MHI_CHAN_CTX_BRSTMODE_ENABLE 3
196 #define MHI_CHAN_CTX_POLLCFG_MASK GENMASK(15, 10)
197 #define MHI_CHAN_CTX_RESERVED_MASK GENMASK(31, 16)
198
199 #define QWZ_MHI_CONFIG_WCN7850_MAX_CHANNELS 128
200 #define QWZ_MHI_CONFIG_WCN7850_TIMEOUT_MS 2000
201
202 #define MHI_CHAN_TYPE_INVALID 0
203 #define MHI_CHAN_TYPE_OUTBOUND 1 /* to device */
204 #define MHI_CHAN_TYPE_INBOUND 2 /* from device */
205 #define MHI_CHAN_TYPE_INBOUND_COALESCED 3
206
207 #define MHI_EV_CTX_RESERVED_MASK GENMASK(7, 0)
208 #define MHI_EV_CTX_INTMODC_MASK GENMASK(15, 8)
209 #define MHI_EV_CTX_INTMODT_MASK GENMASK(31, 16)
210 #define MHI_EV_CTX_INTMODT_SHFT 16
211
212 #define MHI_ER_TYPE_INVALID 0
213 #define MHI_ER_TYPE_VALID 1
214
215 #define MHI_ER_DATA 0
216 #define MHI_ER_CTRL 1
217
218 #define MHI_CH_STATE_DISABLED 0
219 #define MHI_CH_STATE_ENABLED 1
220 #define MHI_CH_STATE_RUNNING 2
221 #define MHI_CH_STATE_SUSPENDED 3
222 #define MHI_CH_STATE_STOP 4
223 #define MHI_CH_STATE_ERROR 5
224
225 #define QWZ_NUM_EVENT_CTX 2
226
227 /* Event context. Shared with device. */
228 struct qwz_mhi_event_ctxt {
229 uint32_t intmod;
230 uint32_t ertype;
231 uint32_t msivec;
232
233 uint64_t rbase;
234 uint64_t rlen;
235 uint64_t rp;
236 uint64_t wp;
237 } __packed;
238
239 /* Channel context. Shared with device. */
240 struct qwz_mhi_chan_ctxt {
241 uint32_t chcfg;
242 uint32_t chtype;
243 uint32_t erindex;
244
245 uint64_t rbase;
246 uint64_t rlen;
247 uint64_t rp;
248 uint64_t wp;
249 } __packed;
250
251 /* Command context. Shared with device. */
252 struct qwz_mhi_cmd_ctxt {
253 uint32_t reserved0;
254 uint32_t reserved1;
255 uint32_t reserved2;
256
257 uint64_t rbase;
258 uint64_t rlen;
259 uint64_t rp;
260 uint64_t wp;
261 } __packed;
262
263 struct qwz_mhi_ring_element {
264 uint64_t ptr;
265 uint32_t dword[2];
266 };
267
268 struct qwz_xfer_data {
269 bus_dmamap_t map;
270 struct mbuf *m;
271 };
272
273 #define QWZ_PCI_XFER_MAX_DATA_SIZE 0xffff
274 #define QWZ_PCI_XFER_RING_MAX_ELEMENTS 64
275
276 struct qwz_pci_xfer_ring {
277 struct qwz_dmamem *dmamem;
278 bus_size_t size;
279 uint32_t mhi_chan_id;
280 uint32_t mhi_chan_state;
281 uint32_t mhi_chan_direction;
282 uint32_t mhi_chan_event_ring_index;
283 uint32_t db_addr;
284 uint32_t cmd_status;
285 int num_elements;
286 int queued;
287 struct qwz_xfer_data data[QWZ_PCI_XFER_RING_MAX_ELEMENTS];
288 uint64_t rp;
289 uint64_t wp;
290 struct qwz_mhi_chan_ctxt *chan_ctxt;
291 };
292
293
294 #define QWZ_PCI_EVENT_RING_MAX_ELEMENTS 256
295
296 struct qwz_pci_event_ring {
297 struct qwz_dmamem *dmamem;
298 bus_size_t size;
299 uint32_t mhi_er_type;
300 uint32_t mhi_er_irq;
301 uint32_t mhi_er_irq_moderation_ms;
302 uint32_t db_addr;
303 int num_elements;
304 uint64_t rp;
305 uint64_t wp;
306 struct qwz_mhi_event_ctxt *event_ctxt;
307 };
308
309 struct qwz_cmd_data {
310 bus_dmamap_t map;
311 struct mbuf *m;
312 };
313
314 #define QWZ_PCI_CMD_RING_MAX_ELEMENTS 128
315
316 struct qwz_pci_cmd_ring {
317 struct qwz_dmamem *dmamem;
318 bus_size_t size;
319 uint64_t rp;
320 uint64_t wp;
321 int num_elements;
322 int queued;
323 };
324
325 struct qwz_pci_ops;
326 struct qwz_msi_config;
327
328 #define QWZ_NUM_MSI_VEC 32
329
330 struct qwz_pci_softc {
331 struct qwz_softc sc_sc;
332 pci_chipset_tag_t sc_pc;
333 pcitag_t sc_tag;
334 int sc_cap_off;
335 int sc_msi_off;
336 pcireg_t sc_msi_cap;
337 void *sc_ih[QWZ_NUM_MSI_VEC];
338 char sc_ivname[QWZ_NUM_MSI_VEC][16];
339 struct qwz_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX];
340 int mhi_irq[2];
341 bus_space_tag_t sc_st;
342 bus_space_handle_t sc_sh;
343 bus_addr_t sc_map;
344 bus_size_t sc_mapsize;
345
346 pcireg_t sc_lcsr;
347 uint32_t sc_flags;
348 #define ATH12K_PCI_ASPM_RESTORE 1
349
350 uint32_t register_window;
351 const struct qwz_pci_ops *sc_pci_ops;
352
353 uint32_t bhi_off;
354 uint32_t bhi_ee;
355 uint32_t bhie_off;
356 uint32_t mhi_state;
357 uint32_t max_chan;
358
359 uint64_t wake_db;
360
361 /*
362 * DMA memory for AMSS.bin firmware image.
363 * This memory must remain available to the device until
364 * the device is powered down.
365 */
366 struct qwz_dmamem *amss_data;
367 struct qwz_dmamem *amss_vec;
368
369 struct qwz_dmamem *rddm_vec;
370 struct qwz_dmamem *rddm_data;
371 int rddm_triggered;
372 struct task rddm_task;
373 #define QWZ_RDDM_DUMP_SIZE 0x420000
374
375 struct qwz_dmamem *chan_ctxt;
376 struct qwz_dmamem *event_ctxt;
377 struct qwz_dmamem *cmd_ctxt;
378
379
380 struct qwz_pci_xfer_ring xfer_rings[2];
381 #define QWZ_PCI_XFER_RING_IPCR_OUTBOUND 0
382 #define QWZ_PCI_XFER_RING_IPCR_INBOUND 1
383 struct qwz_pci_event_ring event_rings[QWZ_NUM_EVENT_CTX];
384 struct qwz_pci_cmd_ring cmd_ring;
385 };
386
387 int qwz_pci_match(struct device *, void *, void *);
388 void qwz_pci_attach(struct device *, struct device *, void *);
389 int qwz_pci_detach(struct device *, int);
390 void qwz_pci_attach_hook(struct device *);
391 void qwz_pci_free_xfer_rings(struct qwz_pci_softc *);
392 int qwz_pci_alloc_xfer_ring(struct qwz_softc *, struct qwz_pci_xfer_ring *,
393 uint32_t, uint32_t, uint32_t, size_t);
394 int qwz_pci_alloc_xfer_rings_wcn7850(struct qwz_pci_softc *);
395 void qwz_pci_free_event_rings(struct qwz_pci_softc *);
396 int qwz_pci_alloc_event_ring(struct qwz_softc *,
397 struct qwz_pci_event_ring *, uint32_t, uint32_t, uint32_t, size_t);
398 int qwz_pci_alloc_event_rings(struct qwz_pci_softc *);
399 void qwz_pci_free_cmd_ring(struct qwz_pci_softc *);
400 int qwz_pci_init_cmd_ring(struct qwz_softc *, struct qwz_pci_cmd_ring *);
401 uint32_t qwz_pci_read(struct qwz_softc *, uint32_t);
402 void qwz_pci_write(struct qwz_softc *, uint32_t, uint32_t);
403
404 void qwz_pci_read_hw_version(struct qwz_softc *, uint32_t *, uint32_t *);
405 uint32_t qwz_pcic_read32(struct qwz_softc *, uint32_t);
406 void qwz_pcic_write32(struct qwz_softc *, uint32_t, uint32_t);
407
408 void qwz_pcic_ext_irq_enable(struct qwz_softc *);
409 void qwz_pcic_ext_irq_disable(struct qwz_softc *);
410 int qwz_pcic_config_irq(struct qwz_softc *, struct pci_attach_args *);
411
412 int qwz_pci_start(struct qwz_softc *);
413 void qwz_pci_stop(struct qwz_softc *);
414 void qwz_pci_aspm_disable(struct qwz_softc *);
415 void qwz_pci_aspm_restore(struct qwz_softc *);
416 int qwz_pci_power_up(struct qwz_softc *);
417 void qwz_pci_power_down(struct qwz_softc *);
418
419 int qwz_pci_bus_wake_up(struct qwz_softc *);
420 void qwz_pci_bus_release(struct qwz_softc *);
421 void qwz_pci_window_write32(struct qwz_softc *, uint32_t, uint32_t);
422 uint32_t qwz_pci_window_read32(struct qwz_softc *, uint32_t);
423
424 int qwz_mhi_register(struct qwz_softc *);
425 void qwz_mhi_unregister(struct qwz_softc *);
426 void qwz_mhi_ring_doorbell(struct qwz_softc *sc, uint64_t, uint64_t);
427 void qwz_mhi_device_wake(struct qwz_softc *);
428 void qwz_mhi_device_zzz(struct qwz_softc *);
429 int qwz_mhi_wake_db_clear_valid(struct qwz_softc *);
430 void qwz_mhi_init_xfer_rings(struct qwz_pci_softc *);
431 void qwz_mhi_init_event_rings(struct qwz_pci_softc *);
432 void qwz_mhi_init_cmd_ring(struct qwz_pci_softc *);
433 void qwz_mhi_init_dev_ctxt(struct qwz_pci_softc *);
434 int qwz_mhi_send_cmd(struct qwz_pci_softc *psc, uint32_t, uint32_t);
435 void * qwz_pci_xfer_ring_get_elem(struct qwz_pci_xfer_ring *, uint64_t);
436 struct qwz_xfer_data *qwz_pci_xfer_ring_get_data(struct qwz_pci_xfer_ring *,
437 uint64_t);
438 int qwz_mhi_submit_xfer(struct qwz_softc *sc, struct mbuf *m);
439 int qwz_mhi_start_channel(struct qwz_pci_softc *,
440 struct qwz_pci_xfer_ring *);
441 int qwz_mhi_start_channels(struct qwz_pci_softc *);
442 int qwz_mhi_start(struct qwz_pci_softc *);
443 void qwz_mhi_stop(struct qwz_softc *);
444 int qwz_mhi_reset_device(struct qwz_softc *, int);
445 void qwz_mhi_clear_vector(struct qwz_softc *);
446 int qwz_mhi_fw_load_handler(struct qwz_pci_softc *);
447 int qwz_mhi_await_device_reset(struct qwz_softc *);
448 int qwz_mhi_await_device_ready(struct qwz_softc *);
449 void qwz_mhi_ready_state_transition(struct qwz_pci_softc *);
450 void qwz_mhi_mission_mode_state_transition(struct qwz_pci_softc *);
451 void qwz_mhi_low_power_mode_state_transition(struct qwz_pci_softc *);
452 void qwz_mhi_set_state(struct qwz_softc *, uint32_t);
453 void qwz_mhi_init_mmio(struct qwz_pci_softc *);
454 int qwz_mhi_fw_load_bhi(struct qwz_pci_softc *, uint8_t *, size_t);
455 int qwz_mhi_fw_load_bhie(struct qwz_pci_softc *, uint8_t *, size_t);
456 void qwz_rddm_prepare(struct qwz_pci_softc *);
457 #ifdef QWZ_DEBUG
458 void qwz_rddm_task(void *);
459 #endif
460 void * qwz_pci_event_ring_get_elem(struct qwz_pci_event_ring *, uint64_t);
461 void qwz_pci_intr_ctrl_event_mhi(struct qwz_pci_softc *, uint32_t);
462 void qwz_pci_intr_ctrl_event_ee(struct qwz_pci_softc *, uint32_t);
463 void qwz_pci_intr_ctrl_event_cmd_complete(struct qwz_pci_softc *,
464 uint64_t, uint32_t);
465 int qwz_pci_intr_ctrl_event(struct qwz_pci_softc *,
466 struct qwz_pci_event_ring *);
467 void qwz_pci_intr_data_event_tx(struct qwz_pci_softc *,
468 struct qwz_mhi_ring_element *);
469 int qwz_pci_intr_data_event(struct qwz_pci_softc *,
470 struct qwz_pci_event_ring *);
471 int qwz_pci_intr_mhi_ctrl(void *);
472 int qwz_pci_intr_mhi_data(void *);
473 int qwz_pci_intr(void *);
474
475 struct qwz_pci_ops {
476 int (*wakeup)(struct qwz_softc *);
477 void (*release)(struct qwz_softc *);
478 int (*get_msi_irq)(struct qwz_softc *, unsigned int);
479 void (*window_write32)(struct qwz_softc *, uint32_t, uint32_t);
480 uint32_t (*window_read32)(struct qwz_softc *, uint32_t);
481 int (*alloc_xfer_rings)(struct qwz_pci_softc *);
482 };
483
484
485 static const struct qwz_pci_ops qwz_pci_ops_wcn7850 = {
486 .wakeup = qwz_pci_bus_wake_up,
487 .release = qwz_pci_bus_release,
488 .window_write32 = qwz_pci_window_write32,
489 .window_read32 = qwz_pci_window_read32,
490 .alloc_xfer_rings = qwz_pci_alloc_xfer_rings_wcn7850,
491 };
492
493 const struct cfattach qwz_pci_ca = {
494 sizeof(struct qwz_pci_softc),
495 qwz_pci_match,
496 qwz_pci_attach,
497 qwz_pci_detach,
498 qwz_activate
499 };
500
501 static const struct pci_matchid qwz_pci_devices[] = {
502 { PCI_VENDOR_QUALCOMM, PCI_PRODUCT_QUALCOMM_WCN7850 }
503 };
504
505 int
qwz_pci_match(struct device * parent,void * match,void * aux)506 qwz_pci_match(struct device *parent, void *match, void *aux)
507 {
508 return pci_matchbyid(aux, qwz_pci_devices, nitems(qwz_pci_devices));
509 }
510
511 void
qwz_pci_init_qmi_ce_config(struct qwz_softc * sc)512 qwz_pci_init_qmi_ce_config(struct qwz_softc *sc)
513 {
514 struct qwz_qmi_ce_cfg *cfg = &sc->qmi_ce_cfg;
515
516 qwz_ce_get_shadow_config(sc, &cfg->shadow_reg_v3,
517 &cfg->shadow_reg_v3_len);
518 }
519
520 const struct qwz_msi_config qwz_msi_config_one_msi = {
521 .total_vectors = 1,
522 .total_users = 4,
523 .users = (struct qwz_msi_user[]) {
524 { .name = "MHI", .num_vectors = 1, .base_vector = 0 },
525 { .name = "CE", .num_vectors = 1, .base_vector = 0 },
526 { .name = "WAKE", .num_vectors = 1, .base_vector = 0 },
527 { .name = "DP", .num_vectors = 1, .base_vector = 0 },
528 },
529 };
530
531 const struct qwz_msi_config qwz_msi_config[] = {
532 {
533 .total_vectors = 16,
534 .total_users = 3,
535 .users = (struct qwz_msi_user[]) {
536 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
537 { .name = "CE", .num_vectors = 5, .base_vector = 3 },
538 { .name = "DP", .num_vectors = 8, .base_vector = 8 },
539 },
540 .hw_rev = ATH12K_HW_WCN7850_HW20,
541 },
542 };
543
544 int
qwz_pcic_init_msi_config(struct qwz_softc * sc)545 qwz_pcic_init_msi_config(struct qwz_softc *sc)
546 {
547 const struct qwz_msi_config *msi_config;
548 int i;
549
550 if (!test_bit(ATH12K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags)) {
551 sc->msi_cfg = &qwz_msi_config_one_msi;
552 return 0;
553 }
554 for (i = 0; i < nitems(qwz_msi_config); i++) {
555 msi_config = &qwz_msi_config[i];
556
557 if (msi_config->hw_rev == sc->sc_hw_rev)
558 break;
559 }
560
561 if (i == nitems(qwz_msi_config)) {
562 printf("%s: failed to fetch msi config, "
563 "unsupported hw version: 0x%x\n",
564 sc->sc_dev.dv_xname, sc->sc_hw_rev);
565 return EINVAL;
566 }
567
568 sc->msi_cfg = msi_config;
569 return 0;
570 }
571
572 int
qwz_pci_alloc_msi(struct qwz_softc * sc)573 qwz_pci_alloc_msi(struct qwz_softc *sc)
574 {
575 struct qwz_pci_softc *psc = (struct qwz_pci_softc *)sc;
576 uint64_t addr;
577 pcireg_t data;
578
579 if (psc->sc_msi_cap & PCI_MSI_MC_C64) {
580 uint64_t addr_hi;
581 pcireg_t addr_lo;
582
583 addr_lo = pci_conf_read(psc->sc_pc, psc->sc_tag,
584 psc->sc_msi_off + PCI_MSI_MA);
585 addr_hi = pci_conf_read(psc->sc_pc, psc->sc_tag,
586 psc->sc_msi_off + PCI_MSI_MAU32);
587 addr = addr_hi << 32 | addr_lo;
588 data = pci_conf_read(psc->sc_pc, psc->sc_tag,
589 psc->sc_msi_off + PCI_MSI_MD64);
590 } else {
591 addr = pci_conf_read(psc->sc_pc, psc->sc_tag,
592 psc->sc_msi_off + PCI_MSI_MA);
593 data = pci_conf_read(psc->sc_pc, psc->sc_tag,
594 psc->sc_msi_off + PCI_MSI_MD32);
595 }
596
597 sc->msi_addr_lo = addr & 0xffffffff;
598 sc->msi_addr_hi = ((uint64_t)addr) >> 32;
599 sc->msi_data_start = data;
600
601 DPRINTF("%s: MSI addr: 0x%llx MSI data: 0x%x\n", sc->sc_dev.dv_xname,
602 addr, data);
603
604 return 0;
605 }
606
607 int
qwz_pcic_map_service_to_pipe(struct qwz_softc * sc,uint16_t service_id,uint8_t * ul_pipe,uint8_t * dl_pipe)608 qwz_pcic_map_service_to_pipe(struct qwz_softc *sc, uint16_t service_id,
609 uint8_t *ul_pipe, uint8_t *dl_pipe)
610 {
611 const struct service_to_pipe *entry;
612 int ul_set = 0, dl_set = 0;
613 int i;
614
615 for (i = 0; i < sc->hw_params.svc_to_ce_map_len; i++) {
616 entry = &sc->hw_params.svc_to_ce_map[i];
617
618 if (le32toh(entry->service_id) != service_id)
619 continue;
620
621 switch (le32toh(entry->pipedir)) {
622 case PIPEDIR_NONE:
623 break;
624 case PIPEDIR_IN:
625 *dl_pipe = le32toh(entry->pipenum);
626 dl_set = 1;
627 break;
628 case PIPEDIR_OUT:
629 *ul_pipe = le32toh(entry->pipenum);
630 ul_set = 1;
631 break;
632 case PIPEDIR_INOUT:
633 *dl_pipe = le32toh(entry->pipenum);
634 *ul_pipe = le32toh(entry->pipenum);
635 dl_set = 1;
636 ul_set = 1;
637 break;
638 }
639 }
640
641 if (!ul_set || !dl_set) {
642 DPRINTF("%s: found no uplink and no downlink\n", __func__);
643 return ENOENT;
644 }
645
646 return 0;
647 }
648
649 int
qwz_pcic_get_user_msi_vector(struct qwz_softc * sc,char * user_name,int * num_vectors,uint32_t * user_base_data,uint32_t * base_vector)650 qwz_pcic_get_user_msi_vector(struct qwz_softc *sc, char *user_name,
651 int *num_vectors, uint32_t *user_base_data, uint32_t *base_vector)
652 {
653 const struct qwz_msi_config *msi_config = sc->msi_cfg;
654 int idx;
655
656 for (idx = 0; idx < msi_config->total_users; idx++) {
657 if (strcmp(user_name, msi_config->users[idx].name) == 0) {
658 *num_vectors = msi_config->users[idx].num_vectors;
659 *base_vector = msi_config->users[idx].base_vector;
660 *user_base_data = *base_vector + sc->msi_data_start;
661
662 DPRINTF("%s: MSI assignment %s num_vectors %d "
663 "user_base_data %u base_vector %u\n", __func__,
664 user_name, *num_vectors, *user_base_data,
665 *base_vector);
666 return 0;
667 }
668 }
669
670 DPRINTF("%s: Failed to find MSI assignment for %s\n",
671 sc->sc_dev.dv_xname, user_name);
672
673 return EINVAL;
674 }
675
676 void
qwz_pci_attach(struct device * parent,struct device * self,void * aux)677 qwz_pci_attach(struct device *parent, struct device *self, void *aux)
678 {
679 struct qwz_pci_softc *psc = (struct qwz_pci_softc *)self;
680 struct qwz_softc *sc = &psc->sc_sc;
681 struct ieee80211com *ic = &sc->sc_ic;
682 struct ifnet *ifp = &ic->ic_if;
683 uint32_t soc_hw_version_major, soc_hw_version_minor;
684 struct pci_attach_args *pa = aux;
685 pci_intr_handle_t ih;
686 pcireg_t memtype, reg;
687 const char *intrstr;
688 int error;
689 pcireg_t sreg;
690
691 sc->sc_dmat = pa->pa_dmat;
692 psc->sc_pc = pa->pa_pc;
693 psc->sc_tag = pa->pa_tag;
694
695 #ifdef __HAVE_FDT
696 sc->sc_node = PCITAG_NODE(pa->pa_tag);
697 #endif
698
699 rw_init(&sc->ioctl_rwl, "qwzioctl");
700
701 sreg = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_SUBSYS_ID_REG);
702 sc->id.bdf_search = ATH12K_BDF_SEARCH_DEFAULT;
703 sc->id.vendor = PCI_VENDOR(pa->pa_id);
704 sc->id.device = PCI_PRODUCT(pa->pa_id);
705 sc->id.subsystem_vendor = PCI_VENDOR(sreg);
706 sc->id.subsystem_device = PCI_PRODUCT(sreg);
707
708 strlcpy(sc->sc_bus_str, "pci", sizeof(sc->sc_bus_str));
709
710 sc->ops.read32 = qwz_pcic_read32;
711 sc->ops.write32 = qwz_pcic_write32;
712 sc->ops.start = qwz_pci_start;
713 sc->ops.stop = qwz_pci_stop;
714 sc->ops.power_up = qwz_pci_power_up;
715 sc->ops.power_down = qwz_pci_power_down;
716 sc->ops.submit_xfer = qwz_mhi_submit_xfer;
717 sc->ops.irq_enable = qwz_pcic_ext_irq_enable;
718 sc->ops.irq_disable = qwz_pcic_ext_irq_disable;
719 sc->ops.map_service_to_pipe = qwz_pcic_map_service_to_pipe;
720 sc->ops.get_user_msi_vector = qwz_pcic_get_user_msi_vector;
721
722 if (pci_get_capability(psc->sc_pc, psc->sc_tag, PCI_CAP_PCIEXPRESS,
723 &psc->sc_cap_off, NULL) == 0) {
724 printf(": can't find PCIe capability structure\n");
725 return;
726 }
727
728 if (pci_get_capability(psc->sc_pc, psc->sc_tag, PCI_CAP_MSI,
729 &psc->sc_msi_off, &psc->sc_msi_cap) == 0) {
730 printf(": can't find MSI capability structure\n");
731 return;
732 }
733
734 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
735 reg |= PCI_COMMAND_MASTER_ENABLE;
736 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg);
737
738 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START);
739 if (pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0,
740 &psc->sc_st, &psc->sc_sh, &psc->sc_map, &psc->sc_mapsize, 0)) {
741 printf(": can't map mem space\n");
742 return;
743 }
744
745 sc->mem = psc->sc_map;
746
747 sc->num_msivec = 32;
748 if (pci_intr_enable_msivec(pa, sc->num_msivec) != 0) {
749 sc->num_msivec = 1;
750 if (pci_intr_map_msi(pa, &ih) != 0) {
751 printf(": can't map interrupt\n");
752 return;
753 }
754 clear_bit(ATH12K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags);
755 } else {
756 if (pci_intr_map_msivec(pa, 0, &ih) != 0 &&
757 pci_intr_map_msi(pa, &ih) != 0) {
758 printf(": can't map interrupt\n");
759 return;
760 }
761 set_bit(ATH12K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags);
762 psc->mhi_irq[MHI_ER_CTRL] = 1;
763 psc->mhi_irq[MHI_ER_DATA] = 2;
764 }
765
766 intrstr = pci_intr_string(psc->sc_pc, ih);
767 snprintf(psc->sc_ivname[0], sizeof(psc->sc_ivname[0]), "%s:bhi",
768 sc->sc_dev.dv_xname);
769 psc->sc_ih[0] = pci_intr_establish(psc->sc_pc, ih, IPL_NET,
770 qwz_pci_intr, psc, psc->sc_ivname[0]);
771 if (psc->sc_ih[0] == NULL) {
772 printf(": can't establish interrupt");
773 if (intrstr != NULL)
774 printf(" at %s", intrstr);
775 printf("\n");
776 return;
777 }
778 printf(": %s\n", intrstr);
779
780 if (test_bit(ATH12K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags)) {
781 int msivec;
782
783 msivec = psc->mhi_irq[MHI_ER_CTRL];
784 if (pci_intr_map_msivec(pa, msivec, &ih) != 0 &&
785 pci_intr_map_msi(pa, &ih) != 0) {
786 printf(": can't map interrupt\n");
787 return;
788 }
789 snprintf(psc->sc_ivname[msivec],
790 sizeof(psc->sc_ivname[msivec]),
791 "%s:mhic", sc->sc_dev.dv_xname);
792 psc->sc_ih[msivec] = pci_intr_establish(psc->sc_pc, ih,
793 IPL_NET, qwz_pci_intr_mhi_ctrl, psc,
794 psc->sc_ivname[msivec]);
795 if (psc->sc_ih[msivec] == NULL) {
796 printf("%s: can't establish interrupt\n",
797 sc->sc_dev.dv_xname);
798 return;
799 }
800
801 msivec = psc->mhi_irq[MHI_ER_DATA];
802 if (pci_intr_map_msivec(pa, msivec, &ih) != 0 &&
803 pci_intr_map_msi(pa, &ih) != 0) {
804 printf(": can't map interrupt\n");
805 return;
806 }
807 snprintf(psc->sc_ivname[msivec],
808 sizeof(psc->sc_ivname[msivec]),
809 "%s:mhid", sc->sc_dev.dv_xname);
810 psc->sc_ih[msivec] = pci_intr_establish(psc->sc_pc, ih,
811 IPL_NET, qwz_pci_intr_mhi_data, psc,
812 psc->sc_ivname[msivec]);
813 if (psc->sc_ih[msivec] == NULL) {
814 printf("%s: can't establish interrupt\n",
815 sc->sc_dev.dv_xname);
816 return;
817 }
818 }
819
820 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
821
822 switch (PCI_PRODUCT(pa->pa_id)) {
823 case PCI_PRODUCT_QUALCOMM_WCN7850:
824 sc->static_window_map = 0;
825 psc->sc_pci_ops = &qwz_pci_ops_wcn7850;
826 sc->hal_rx_ops = &hal_rx_wcn7850_ops;
827 sc->id.bdf_search = ATH12K_BDF_SEARCH_BUS_AND_BOARD;
828 qwz_pci_read_hw_version(sc, &soc_hw_version_major,
829 &soc_hw_version_minor);
830 switch (soc_hw_version_major) {
831 case 2:
832 sc->sc_hw_rev = ATH12K_HW_WCN7850_HW20;
833 break;
834 default:
835 printf(": unknown hardware version found for WCN7850: "
836 "%d\n", soc_hw_version_major);
837 return;
838 }
839
840 psc->max_chan = QWZ_MHI_CONFIG_WCN7850_MAX_CHANNELS;
841 break;
842 default:
843 printf(": unsupported chip\n");
844 return;
845 }
846
847 error = qwz_pcic_init_msi_config(sc);
848 if (error)
849 goto err_pci_free_region;
850
851 error = qwz_pci_alloc_msi(sc);
852 if (error) {
853 printf("%s: failed to enable msi: %d\n", sc->sc_dev.dv_xname,
854 error);
855 goto err_pci_free_region;
856 }
857
858 error = qwz_init_hw_params(sc);
859 if (error)
860 goto err_pci_disable_msi;
861
862 psc->chan_ctxt = qwz_dmamem_alloc(sc->sc_dmat,
863 sizeof(struct qwz_mhi_chan_ctxt) * psc->max_chan, 0);
864 if (psc->chan_ctxt == NULL) {
865 printf("%s: could not allocate channel context array\n",
866 sc->sc_dev.dv_xname);
867 goto err_pci_disable_msi;
868 }
869
870 if (psc->sc_pci_ops->alloc_xfer_rings(psc)) {
871 printf("%s: could not allocate transfer rings\n",
872 sc->sc_dev.dv_xname);
873 goto err_pci_free_chan_ctxt;
874 }
875
876 psc->event_ctxt = qwz_dmamem_alloc(sc->sc_dmat,
877 sizeof(struct qwz_mhi_event_ctxt) * QWZ_NUM_EVENT_CTX, 0);
878 if (psc->event_ctxt == NULL) {
879 printf("%s: could not allocate event context array\n",
880 sc->sc_dev.dv_xname);
881 goto err_pci_free_xfer_rings;
882 }
883
884 if (qwz_pci_alloc_event_rings(psc)) {
885 printf("%s: could not allocate event rings\n",
886 sc->sc_dev.dv_xname);
887 goto err_pci_free_event_ctxt;
888 }
889
890 psc->cmd_ctxt = qwz_dmamem_alloc(sc->sc_dmat,
891 sizeof(struct qwz_mhi_cmd_ctxt), 0);
892 if (psc->cmd_ctxt == NULL) {
893 printf("%s: could not allocate command context array\n",
894 sc->sc_dev.dv_xname);
895 goto err_pci_free_event_rings;
896 }
897
898 if (qwz_pci_init_cmd_ring(sc, &psc->cmd_ring)) {
899 printf("%s: could not allocate command ring\n",
900 sc->sc_dev.dv_xname);
901 goto err_pci_free_cmd_ctxt;
902 }
903
904 error = qwz_mhi_register(sc);
905 if (error) {
906 printf(": failed to register mhi: %d\n", error);
907 goto err_pci_free_cmd_ring;
908 }
909
910 error = qwz_hal_srng_init(sc);
911 if (error)
912 goto err_mhi_unregister;
913
914 error = qwz_ce_alloc_pipes(sc);
915 if (error) {
916 printf(": failed to allocate ce pipes: %d\n", error);
917 goto err_hal_srng_deinit;
918 }
919
920 sc->sc_nswq = taskq_create("qwzns", 1, IPL_NET, 0);
921 if (sc->sc_nswq == NULL)
922 goto err_ce_free;
923
924 error = qwz_pcic_config_irq(sc, pa);
925 if (error) {
926 printf("%s: failed to config irq: %d\n",
927 sc->sc_dev.dv_xname, error);
928 goto err_ce_free;
929 }
930 #if notyet
931 ret = ath12k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0));
932 if (ret) {
933 ath12k_err(ab, "failed to set irq affinity %d\n", ret);
934 goto err_free_irq;
935 }
936
937 /* kernel may allocate a dummy vector before request_irq and
938 * then allocate a real vector when request_irq is called.
939 * So get msi_data here again to avoid spurious interrupt
940 * as msi_data will configured to srngs.
941 */
942 ret = ath12k_pci_config_msi_data(ab_pci);
943 if (ret) {
944 ath12k_err(ab, "failed to config msi_data: %d\n", ret);
945 goto err_irq_affinity_cleanup;
946 }
947 #endif
948 #ifdef QWZ_DEBUG
949 task_set(&psc->rddm_task, qwz_rddm_task, psc);
950 #endif
951 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
952 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
953 ic->ic_state = IEEE80211_S_INIT;
954
955 /* Set device capabilities. */
956 ic->ic_caps =
957 #if 0
958 IEEE80211_C_QOS | IEEE80211_C_TX_AMPDU | /* A-MPDU */
959 #endif
960 IEEE80211_C_ADDBA_OFFLOAD | /* device sends ADDBA/DELBA frames */
961 IEEE80211_C_WEP | /* WEP */
962 IEEE80211_C_RSN | /* WPA/RSN */
963 IEEE80211_C_SCANALL | /* device scans all channels at once */
964 IEEE80211_C_SCANALLBAND | /* device scans all bands at once */
965 #if 0
966 IEEE80211_C_MONITOR | /* monitor mode supported */
967 #endif
968 IEEE80211_C_SHSLOT | /* short slot time supported */
969 IEEE80211_C_SHPREAMBLE; /* short preamble supported */
970
971 ic->ic_sup_rates[IEEE80211_MODE_11A] = ieee80211_std_rateset_11a;
972 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b;
973 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g;
974
975 /* IBSS channel undefined for now. */
976 ic->ic_ibss_chan = &ic->ic_channels[1];
977
978 ifp->if_softc = sc;
979 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
980 ifp->if_ioctl = qwz_ioctl;
981 ifp->if_start = qwz_start;
982 ifp->if_watchdog = qwz_watchdog;
983 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ);
984 if_attach(ifp);
985 ieee80211_ifattach(ifp);
986 ieee80211_media_init(ifp, qwz_media_change, ieee80211_media_status);
987
988 ic->ic_node_alloc = qwz_node_alloc;
989
990 /* Override 802.11 state transition machine. */
991 sc->sc_newstate = ic->ic_newstate;
992 ic->ic_newstate = qwz_newstate;
993 ic->ic_set_key = qwz_set_key;
994 ic->ic_delete_key = qwz_delete_key;
995 #if 0
996 ic->ic_updatechan = qwz_updatechan;
997 ic->ic_updateprot = qwz_updateprot;
998 ic->ic_updateslot = qwz_updateslot;
999 ic->ic_updateedca = qwz_updateedca;
1000 ic->ic_updatedtim = qwz_updatedtim;
1001 #endif
1002 /*
1003 * We cannot read the MAC address without loading the
1004 * firmware from disk. Postpone until mountroot is done.
1005 */
1006 config_mountroot(self, qwz_pci_attach_hook);
1007 return;
1008
1009 err_ce_free:
1010 qwz_ce_free_pipes(sc);
1011 err_hal_srng_deinit:
1012 err_mhi_unregister:
1013 err_pci_free_cmd_ring:
1014 qwz_pci_free_cmd_ring(psc);
1015 err_pci_free_cmd_ctxt:
1016 qwz_dmamem_free(sc->sc_dmat, psc->cmd_ctxt);
1017 psc->cmd_ctxt = NULL;
1018 err_pci_free_event_rings:
1019 qwz_pci_free_event_rings(psc);
1020 err_pci_free_event_ctxt:
1021 qwz_dmamem_free(sc->sc_dmat, psc->event_ctxt);
1022 psc->event_ctxt = NULL;
1023 err_pci_free_xfer_rings:
1024 qwz_pci_free_xfer_rings(psc);
1025 err_pci_free_chan_ctxt:
1026 qwz_dmamem_free(sc->sc_dmat, psc->chan_ctxt);
1027 psc->chan_ctxt = NULL;
1028 err_pci_disable_msi:
1029 err_pci_free_region:
1030 pci_intr_disestablish(psc->sc_pc, psc->sc_ih[0]);
1031 return;
1032 }
1033
1034 int
qwz_pci_detach(struct device * self,int flags)1035 qwz_pci_detach(struct device *self, int flags)
1036 {
1037 struct qwz_pci_softc *psc = (struct qwz_pci_softc *)self;
1038 struct qwz_softc *sc = &psc->sc_sc;
1039
1040 if (psc->sc_ih[0]) {
1041 pci_intr_disestablish(psc->sc_pc, psc->sc_ih[0]);
1042 psc->sc_ih[0] = NULL;
1043 }
1044
1045 qwz_detach(sc);
1046
1047 qwz_pci_free_event_rings(psc);
1048 qwz_pci_free_xfer_rings(psc);
1049 qwz_pci_free_cmd_ring(psc);
1050
1051 if (psc->event_ctxt) {
1052 qwz_dmamem_free(sc->sc_dmat, psc->event_ctxt);
1053 psc->event_ctxt = NULL;
1054 }
1055 if (psc->chan_ctxt) {
1056 qwz_dmamem_free(sc->sc_dmat, psc->chan_ctxt);
1057 psc->chan_ctxt = NULL;
1058 }
1059 if (psc->cmd_ctxt) {
1060 qwz_dmamem_free(sc->sc_dmat, psc->cmd_ctxt);
1061 psc->cmd_ctxt = NULL;
1062 }
1063
1064 if (psc->amss_data) {
1065 qwz_dmamem_free(sc->sc_dmat, psc->amss_data);
1066 psc->amss_data = NULL;
1067 }
1068 if (psc->amss_vec) {
1069 qwz_dmamem_free(sc->sc_dmat, psc->amss_vec);
1070 psc->amss_vec = NULL;
1071 }
1072
1073 return 0;
1074 }
1075
1076 void
qwz_pci_attach_hook(struct device * self)1077 qwz_pci_attach_hook(struct device *self)
1078 {
1079 struct qwz_softc *sc = (void *)self;
1080 int s = splnet();
1081
1082 qwz_attach(sc);
1083
1084 splx(s);
1085 }
1086
1087 void
qwz_pci_free_xfer_rings(struct qwz_pci_softc * psc)1088 qwz_pci_free_xfer_rings(struct qwz_pci_softc *psc)
1089 {
1090 struct qwz_softc *sc = &psc->sc_sc;
1091 int i;
1092
1093 for (i = 0; i < nitems(psc->xfer_rings); i++) {
1094 struct qwz_pci_xfer_ring *ring = &psc->xfer_rings[i];
1095 if (ring->dmamem) {
1096 qwz_dmamem_free(sc->sc_dmat, ring->dmamem);
1097 ring->dmamem = NULL;
1098 }
1099 memset(ring, 0, sizeof(*ring));
1100 }
1101 }
1102
1103 int
qwz_pci_alloc_xfer_ring(struct qwz_softc * sc,struct qwz_pci_xfer_ring * ring,uint32_t id,uint32_t direction,uint32_t event_ring_index,size_t num_elements)1104 qwz_pci_alloc_xfer_ring(struct qwz_softc *sc, struct qwz_pci_xfer_ring *ring,
1105 uint32_t id, uint32_t direction, uint32_t event_ring_index,
1106 size_t num_elements)
1107 {
1108 bus_size_t size;
1109 int i, err;
1110
1111 memset(ring, 0, sizeof(*ring));
1112
1113 size = sizeof(struct qwz_mhi_ring_element) * num_elements;
1114 /* Hardware requires that rings are aligned to ring size. */
1115 ring->dmamem = qwz_dmamem_alloc(sc->sc_dmat, size, size);
1116 if (ring->dmamem == NULL)
1117 return ENOMEM;
1118
1119 ring->size = size;
1120 ring->mhi_chan_id = id;
1121 ring->mhi_chan_state = MHI_CH_STATE_DISABLED;
1122 ring->mhi_chan_direction = direction;
1123 ring->mhi_chan_event_ring_index = event_ring_index;
1124 ring->num_elements = num_elements;
1125
1126 memset(ring->data, 0, sizeof(ring->data));
1127 for (i = 0; i < ring->num_elements; i++) {
1128 struct qwz_xfer_data *xfer = &ring->data[i];
1129
1130 err = bus_dmamap_create(sc->sc_dmat, QWZ_PCI_XFER_MAX_DATA_SIZE,
1131 1, QWZ_PCI_XFER_MAX_DATA_SIZE, 0, BUS_DMA_NOWAIT,
1132 &xfer->map);
1133 if (err) {
1134 printf("%s: could not create xfer DMA map\n",
1135 sc->sc_dev.dv_xname);
1136 goto fail;
1137 }
1138
1139 if (direction == MHI_CHAN_TYPE_INBOUND) {
1140 struct mbuf *m;
1141
1142 m = m_gethdr(M_DONTWAIT, MT_DATA);
1143 if (m == NULL) {
1144 err = ENOBUFS;
1145 goto fail;
1146 }
1147
1148 MCLGETL(m, M_DONTWAIT, QWZ_PCI_XFER_MAX_DATA_SIZE);
1149 if ((m->m_flags & M_EXT) == 0) {
1150 m_freem(m);
1151 err = ENOBUFS;
1152 goto fail;
1153 }
1154
1155 m->m_len = m->m_pkthdr.len = QWZ_PCI_XFER_MAX_DATA_SIZE;
1156 err = bus_dmamap_load_mbuf(sc->sc_dmat, xfer->map,
1157 m, BUS_DMA_READ | BUS_DMA_NOWAIT);
1158 if (err) {
1159 printf("%s: can't map mbuf (error %d)\n",
1160 sc->sc_dev.dv_xname, err);
1161 m_freem(m);
1162 goto fail;
1163 }
1164
1165 bus_dmamap_sync(sc->sc_dmat, xfer->map, 0,
1166 QWZ_PCI_XFER_MAX_DATA_SIZE, BUS_DMASYNC_PREREAD);
1167 xfer->m = m;
1168 }
1169 }
1170
1171 return 0;
1172 fail:
1173 for (i = 0; i < ring->num_elements; i++) {
1174 struct qwz_xfer_data *xfer = &ring->data[i];
1175
1176 if (xfer->map) {
1177 bus_dmamap_sync(sc->sc_dmat, xfer->map, 0,
1178 xfer->map->dm_mapsize, BUS_DMASYNC_POSTREAD);
1179 bus_dmamap_unload(sc->sc_dmat, xfer->map);
1180 bus_dmamap_destroy(sc->sc_dmat, xfer->map);
1181 xfer->map = NULL;
1182 }
1183
1184 if (xfer->m) {
1185 m_freem(xfer->m);
1186 xfer->m = NULL;
1187 }
1188 }
1189 return 1;
1190 }
1191
1192 int
qwz_pci_alloc_xfer_rings_wcn7850(struct qwz_pci_softc * psc)1193 qwz_pci_alloc_xfer_rings_wcn7850(struct qwz_pci_softc *psc)
1194 {
1195 struct qwz_softc *sc = &psc->sc_sc;
1196 int ret;
1197
1198 ret = qwz_pci_alloc_xfer_ring(sc,
1199 &psc->xfer_rings[QWZ_PCI_XFER_RING_IPCR_OUTBOUND],
1200 20, MHI_CHAN_TYPE_OUTBOUND, 1, 64);
1201 if (ret)
1202 goto fail;
1203
1204 ret = qwz_pci_alloc_xfer_ring(sc,
1205 &psc->xfer_rings[QWZ_PCI_XFER_RING_IPCR_INBOUND],
1206 21, MHI_CHAN_TYPE_INBOUND, 1, 64);
1207 if (ret)
1208 goto fail;
1209
1210 return 0;
1211 fail:
1212 qwz_pci_free_xfer_rings(psc);
1213 return ret;
1214 }
1215
1216 void
qwz_pci_free_event_rings(struct qwz_pci_softc * psc)1217 qwz_pci_free_event_rings(struct qwz_pci_softc *psc)
1218 {
1219 struct qwz_softc *sc = &psc->sc_sc;
1220 int i;
1221
1222 for (i = 0; i < nitems(psc->event_rings); i++) {
1223 struct qwz_pci_event_ring *ring = &psc->event_rings[i];
1224 if (ring->dmamem) {
1225 qwz_dmamem_free(sc->sc_dmat, ring->dmamem);
1226 ring->dmamem = NULL;
1227 }
1228 memset(ring, 0, sizeof(*ring));
1229 }
1230 }
1231
1232 int
qwz_pci_alloc_event_ring(struct qwz_softc * sc,struct qwz_pci_event_ring * ring,uint32_t type,uint32_t irq,uint32_t intmod,size_t num_elements)1233 qwz_pci_alloc_event_ring(struct qwz_softc *sc, struct qwz_pci_event_ring *ring,
1234 uint32_t type, uint32_t irq, uint32_t intmod, size_t num_elements)
1235 {
1236 bus_size_t size;
1237
1238 memset(ring, 0, sizeof(*ring));
1239
1240 size = sizeof(struct qwz_mhi_ring_element) * num_elements;
1241 /* Hardware requires that rings are aligned to ring size. */
1242 ring->dmamem = qwz_dmamem_alloc(sc->sc_dmat, size, size);
1243 if (ring->dmamem == NULL)
1244 return ENOMEM;
1245
1246 ring->size = size;
1247 ring->mhi_er_type = type;
1248 ring->mhi_er_irq = irq;
1249 ring->mhi_er_irq_moderation_ms = intmod;
1250 ring->num_elements = num_elements;
1251 return 0;
1252 }
1253
1254 int
qwz_pci_alloc_event_rings(struct qwz_pci_softc * psc)1255 qwz_pci_alloc_event_rings(struct qwz_pci_softc *psc)
1256 {
1257 struct qwz_softc *sc = &psc->sc_sc;
1258 int ret;
1259
1260 ret = qwz_pci_alloc_event_ring(sc, &psc->event_rings[0],
1261 MHI_ER_CTRL, psc->mhi_irq[MHI_ER_CTRL], 0, 32);
1262 if (ret)
1263 goto fail;
1264
1265 ret = qwz_pci_alloc_event_ring(sc, &psc->event_rings[1],
1266 MHI_ER_DATA, psc->mhi_irq[MHI_ER_DATA], 1, 256);
1267 if (ret)
1268 goto fail;
1269
1270 return 0;
1271 fail:
1272 qwz_pci_free_event_rings(psc);
1273 return ret;
1274 }
1275
1276 void
qwz_pci_free_cmd_ring(struct qwz_pci_softc * psc)1277 qwz_pci_free_cmd_ring(struct qwz_pci_softc *psc)
1278 {
1279 struct qwz_softc *sc = &psc->sc_sc;
1280 struct qwz_pci_cmd_ring *ring = &psc->cmd_ring;
1281
1282 if (ring->dmamem)
1283 qwz_dmamem_free(sc->sc_dmat, ring->dmamem);
1284
1285 memset(ring, 0, sizeof(*ring));
1286 }
1287
1288 int
qwz_pci_init_cmd_ring(struct qwz_softc * sc,struct qwz_pci_cmd_ring * ring)1289 qwz_pci_init_cmd_ring(struct qwz_softc *sc, struct qwz_pci_cmd_ring *ring)
1290 {
1291 memset(ring, 0, sizeof(*ring));
1292
1293 ring->num_elements = QWZ_PCI_CMD_RING_MAX_ELEMENTS;
1294 ring->size = sizeof(struct qwz_mhi_ring_element) * ring->num_elements;
1295
1296 /* Hardware requires that rings are aligned to ring size. */
1297 ring->dmamem = qwz_dmamem_alloc(sc->sc_dmat, ring->size, ring->size);
1298 if (ring->dmamem == NULL)
1299 return ENOMEM;
1300
1301 return 0;
1302 }
1303
1304 uint32_t
qwz_pci_read(struct qwz_softc * sc,uint32_t addr)1305 qwz_pci_read(struct qwz_softc *sc, uint32_t addr)
1306 {
1307 struct qwz_pci_softc *psc = (struct qwz_pci_softc *)sc;
1308
1309 return (bus_space_read_4(psc->sc_st, psc->sc_sh, addr));
1310 }
1311
1312 void
qwz_pci_write(struct qwz_softc * sc,uint32_t addr,uint32_t val)1313 qwz_pci_write(struct qwz_softc *sc, uint32_t addr, uint32_t val)
1314 {
1315 struct qwz_pci_softc *psc = (struct qwz_pci_softc *)sc;
1316
1317 bus_space_write_4(psc->sc_st, psc->sc_sh, addr, val);
1318 }
1319
1320 void
qwz_pci_read_hw_version(struct qwz_softc * sc,uint32_t * major,uint32_t * minor)1321 qwz_pci_read_hw_version(struct qwz_softc *sc, uint32_t *major,
1322 uint32_t *minor)
1323 {
1324 uint32_t soc_hw_version;
1325
1326 soc_hw_version = qwz_pcic_read32(sc, TCSR_SOC_HW_VERSION);
1327 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK, soc_hw_version);
1328 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK, soc_hw_version);
1329 DPRINTF("%s: pci tcsr_soc_hw_version major %d minor %d\n",
1330 sc->sc_dev.dv_xname, *major, *minor);
1331 }
1332
1333 uint32_t
qwz_pcic_read32(struct qwz_softc * sc,uint32_t offset)1334 qwz_pcic_read32(struct qwz_softc *sc, uint32_t offset)
1335 {
1336 struct qwz_pci_softc *psc = (struct qwz_pci_softc *)sc;
1337 int ret = 0;
1338 uint32_t val;
1339 bool wakeup_required;
1340
1341 /* for offset beyond BAR + 4K - 32, may
1342 * need to wakeup the device to access.
1343 */
1344 wakeup_required = test_bit(ATH12K_FLAG_DEVICE_INIT_DONE, sc->sc_flags)
1345 && offset >= ATH12K_PCI_ACCESS_ALWAYS_OFF;
1346 if (wakeup_required && psc->sc_pci_ops->wakeup)
1347 ret = psc->sc_pci_ops->wakeup(sc);
1348
1349 if (offset < ATH12K_PCI_WINDOW_START)
1350 val = qwz_pci_read(sc, offset);
1351 else
1352 val = psc->sc_pci_ops->window_read32(sc, offset);
1353
1354 if (wakeup_required && !ret && psc->sc_pci_ops->release)
1355 psc->sc_pci_ops->release(sc);
1356
1357 return val;
1358 }
1359
1360 void
qwz_pcic_write32(struct qwz_softc * sc,uint32_t offset,uint32_t value)1361 qwz_pcic_write32(struct qwz_softc *sc, uint32_t offset, uint32_t value)
1362 {
1363 struct qwz_pci_softc *psc = (struct qwz_pci_softc *)sc;
1364 int ret = 0;
1365 bool wakeup_required;
1366
1367 /* for offset beyond BAR + 4K - 32, may
1368 * need to wakeup the device to access.
1369 */
1370 wakeup_required = test_bit(ATH12K_FLAG_DEVICE_INIT_DONE, sc->sc_flags)
1371 && offset >= ATH12K_PCI_ACCESS_ALWAYS_OFF;
1372 if (wakeup_required && psc->sc_pci_ops->wakeup)
1373 ret = psc->sc_pci_ops->wakeup(sc);
1374
1375 if (offset < ATH12K_PCI_WINDOW_START)
1376 qwz_pci_write(sc, offset, value);
1377 else
1378 psc->sc_pci_ops->window_write32(sc, offset, value);
1379
1380 if (wakeup_required && !ret && psc->sc_pci_ops->release)
1381 psc->sc_pci_ops->release(sc);
1382 }
1383
1384 void
qwz_pcic_ext_irq_disable(struct qwz_softc * sc)1385 qwz_pcic_ext_irq_disable(struct qwz_softc *sc)
1386 {
1387 clear_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, sc->sc_flags);
1388
1389 /* In case of one MSI vector, we handle irq enable/disable in a
1390 * uniform way since we only have one irq
1391 */
1392 if (!test_bit(ATH12K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags))
1393 return;
1394
1395 DPRINTF("%s not implemented\n", __func__);
1396 }
1397
1398 void
qwz_pcic_ext_irq_enable(struct qwz_softc * sc)1399 qwz_pcic_ext_irq_enable(struct qwz_softc *sc)
1400 {
1401 set_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, sc->sc_flags);
1402
1403 /* In case of one MSI vector, we handle irq enable/disable in a
1404 * uniform way since we only have one irq
1405 */
1406 if (!test_bit(ATH12K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags))
1407 return;
1408
1409 DPRINTF("%s not implemented\n", __func__);
1410 }
1411
1412 void
qwz_pcic_ce_irq_enable(struct qwz_softc * sc,uint16_t ce_id)1413 qwz_pcic_ce_irq_enable(struct qwz_softc *sc, uint16_t ce_id)
1414 {
1415 /* In case of one MSI vector, we handle irq enable/disable in a
1416 * uniform way since we only have one irq
1417 */
1418 if (!test_bit(ATH12K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags))
1419 return;
1420
1421 /* OpenBSD PCI stack does not yet implement MSI interrupt masking. */
1422 sc->msi_ce_irqmask |= (1U << ce_id);
1423 }
1424
1425 void
qwz_pcic_ce_irq_disable(struct qwz_softc * sc,uint16_t ce_id)1426 qwz_pcic_ce_irq_disable(struct qwz_softc *sc, uint16_t ce_id)
1427 {
1428 /* In case of one MSI vector, we handle irq enable/disable in a
1429 * uniform way since we only have one irq
1430 */
1431 if (!test_bit(ATH12K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags))
1432 return;
1433
1434 /* OpenBSD PCI stack does not yet implement MSI interrupt masking. */
1435 sc->msi_ce_irqmask &= ~(1U << ce_id);
1436 }
1437
1438 void
qwz_pcic_ext_grp_disable(struct qwz_ext_irq_grp * irq_grp)1439 qwz_pcic_ext_grp_disable(struct qwz_ext_irq_grp *irq_grp)
1440 {
1441 struct qwz_softc *sc = irq_grp->sc;
1442
1443 /* In case of one MSI vector, we handle irq enable/disable
1444 * in a uniform way since we only have one irq
1445 */
1446 if (!test_bit(ATH12K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags))
1447 return;
1448 }
1449
1450 int
qwz_pcic_ext_irq_config(struct qwz_softc * sc,struct pci_attach_args * pa)1451 qwz_pcic_ext_irq_config(struct qwz_softc *sc, struct pci_attach_args *pa)
1452 {
1453 struct qwz_pci_softc *psc = (struct qwz_pci_softc *)sc;
1454 int i, ret, num_vectors = 0;
1455 uint32_t msi_data_start = 0;
1456 uint32_t base_idx, base_vector = 0;
1457
1458 if (!test_bit(ATH12K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags))
1459 return 0;
1460
1461 base_idx = ATH12K_PCI_IRQ_CE0_OFFSET + CE_COUNT_MAX;
1462
1463 ret = qwz_pcic_get_user_msi_vector(sc, "DP", &num_vectors,
1464 &msi_data_start, &base_vector);
1465 if (ret < 0)
1466 return ret;
1467
1468 for (i = 0; i < nitems(sc->ext_irq_grp); i++) {
1469 struct qwz_ext_irq_grp *irq_grp = &sc->ext_irq_grp[i];
1470 uint32_t num_irq = 0;
1471
1472 irq_grp->sc = sc;
1473 irq_grp->grp_id = i;
1474 #if 0
1475 init_dummy_netdev(&irq_grp->napi_ndev);
1476 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi,
1477 ath12k_pcic_ext_grp_napi_poll);
1478 #endif
1479 if (sc->hw_params.ring_mask->tx[i] ||
1480 sc->hw_params.ring_mask->rx[i] ||
1481 sc->hw_params.ring_mask->rx_err[i] ||
1482 sc->hw_params.ring_mask->rx_wbm_rel[i] ||
1483 sc->hw_params.ring_mask->reo_status[i] ||
1484 sc->hw_params.ring_mask->host2rxdma[i] ||
1485 sc->hw_params.ring_mask->rx_mon_dest[i]) {
1486 num_irq = 1;
1487 }
1488
1489 irq_grp->num_irq = num_irq;
1490 irq_grp->irqs[0] = base_idx + i;
1491
1492 if (num_irq) {
1493 int irq_idx = irq_grp->irqs[0];
1494 pci_intr_handle_t ih;
1495
1496 if (pci_intr_map_msivec(pa, irq_idx, &ih) != 0 &&
1497 pci_intr_map(pa, &ih) != 0) {
1498 printf("%s: can't map interrupt\n",
1499 sc->sc_dev.dv_xname);
1500 return EIO;
1501 }
1502
1503 snprintf(psc->sc_ivname[irq_idx], sizeof(psc->sc_ivname[0]),
1504 "%s:ex%d", sc->sc_dev.dv_xname, i);
1505 psc->sc_ih[irq_idx] = pci_intr_establish(psc->sc_pc, ih,
1506 IPL_NET, qwz_ext_intr, irq_grp, psc->sc_ivname[irq_idx]);
1507 if (psc->sc_ih[irq_idx] == NULL) {
1508 printf("%s: failed to request irq %d\n",
1509 sc->sc_dev.dv_xname, irq_idx);
1510 return EIO;
1511 }
1512 }
1513
1514 qwz_pcic_ext_grp_disable(irq_grp);
1515 }
1516
1517 return 0;
1518 }
1519
1520 int
qwz_pcic_config_irq(struct qwz_softc * sc,struct pci_attach_args * pa)1521 qwz_pcic_config_irq(struct qwz_softc *sc, struct pci_attach_args *pa)
1522 {
1523 struct qwz_pci_softc *psc = (struct qwz_pci_softc *)sc;
1524 struct qwz_ce_pipe *ce_pipe;
1525 uint32_t msi_data_start;
1526 uint32_t msi_data_count, msi_data_idx;
1527 uint32_t msi_irq_start;
1528 int i, ret, irq_idx;
1529 pci_intr_handle_t ih;
1530
1531 if (!test_bit(ATH12K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags))
1532 return 0;
1533
1534 ret = qwz_pcic_get_user_msi_vector(sc, "CE", &msi_data_count,
1535 &msi_data_start, &msi_irq_start);
1536 if (ret)
1537 return ret;
1538
1539 /* Configure CE irqs */
1540 for (i = 0, msi_data_idx = 0; i < sc->hw_params.ce_count; i++) {
1541 if (qwz_ce_get_attr_flags(sc, i) & CE_ATTR_DIS_INTR)
1542 continue;
1543
1544 ce_pipe = &sc->ce.ce_pipe[i];
1545 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i;
1546
1547 if (pci_intr_map_msivec(pa, irq_idx, &ih) != 0 &&
1548 pci_intr_map(pa, &ih) != 0) {
1549 printf("%s: can't map interrupt\n",
1550 sc->sc_dev.dv_xname);
1551 return EIO;
1552 }
1553
1554 snprintf(psc->sc_ivname[irq_idx], sizeof(psc->sc_ivname[0]),
1555 "%s:ce%d", sc->sc_dev.dv_xname, ce_pipe->pipe_num);
1556 psc->sc_ih[irq_idx] = pci_intr_establish(psc->sc_pc, ih,
1557 IPL_NET, qwz_ce_intr, ce_pipe, psc->sc_ivname[irq_idx]);
1558 if (psc->sc_ih[irq_idx] == NULL) {
1559 printf("%s: failed to request irq %d\n",
1560 sc->sc_dev.dv_xname, irq_idx);
1561 return EIO;
1562 }
1563
1564 msi_data_idx++;
1565
1566 qwz_pcic_ce_irq_disable(sc, i);
1567 }
1568
1569 ret = qwz_pcic_ext_irq_config(sc, pa);
1570 if (ret)
1571 return ret;
1572
1573 return 0;
1574 }
1575
1576 void
qwz_pcic_ce_irqs_enable(struct qwz_softc * sc)1577 qwz_pcic_ce_irqs_enable(struct qwz_softc *sc)
1578 {
1579 int i;
1580
1581 set_bit(ATH12K_FLAG_CE_IRQ_ENABLED, sc->sc_flags);
1582
1583 for (i = 0; i < sc->hw_params.ce_count; i++) {
1584 if (qwz_ce_get_attr_flags(sc, i) & CE_ATTR_DIS_INTR)
1585 continue;
1586 qwz_pcic_ce_irq_enable(sc, i);
1587 }
1588 }
1589
1590 void
qwz_pcic_ce_irqs_disable(struct qwz_softc * sc)1591 qwz_pcic_ce_irqs_disable(struct qwz_softc *sc)
1592 {
1593 int i;
1594
1595 clear_bit(ATH12K_FLAG_CE_IRQ_ENABLED, sc->sc_flags);
1596
1597 for (i = 0; i < sc->hw_params.ce_count; i++) {
1598 if (qwz_ce_get_attr_flags(sc, i) & CE_ATTR_DIS_INTR)
1599 continue;
1600 qwz_pcic_ce_irq_disable(sc, i);
1601 }
1602 }
1603
1604 int
qwz_pci_start(struct qwz_softc * sc)1605 qwz_pci_start(struct qwz_softc *sc)
1606 {
1607 /* TODO: for now don't restore ASPM in case of single MSI
1608 * vector as MHI register reading in M2 causes system hang.
1609 */
1610 if (test_bit(ATH12K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags))
1611 qwz_pci_aspm_restore(sc);
1612 else
1613 DPRINTF("%s: leaving PCI ASPM disabled to avoid MHI M2 problems"
1614 "\n", sc->sc_dev.dv_xname);
1615
1616 set_bit(ATH12K_FLAG_DEVICE_INIT_DONE, sc->sc_flags);
1617
1618 qwz_ce_rx_post_buf(sc);
1619 qwz_pcic_ce_irqs_enable(sc);
1620
1621 return 0;
1622 }
1623
1624 void
qwz_pcic_ce_irq_disable_sync(struct qwz_softc * sc)1625 qwz_pcic_ce_irq_disable_sync(struct qwz_softc *sc)
1626 {
1627 qwz_pcic_ce_irqs_disable(sc);
1628 #if 0
1629 ath12k_pcic_sync_ce_irqs(ab);
1630 ath12k_pcic_kill_tasklets(ab);
1631 #endif
1632 }
1633
1634 void
qwz_pci_stop(struct qwz_softc * sc)1635 qwz_pci_stop(struct qwz_softc *sc)
1636 {
1637 qwz_pcic_ce_irq_disable_sync(sc);
1638 qwz_ce_cleanup_pipes(sc);
1639 }
1640
1641 int
qwz_pci_bus_wake_up(struct qwz_softc * sc)1642 qwz_pci_bus_wake_up(struct qwz_softc *sc)
1643 {
1644 if (qwz_mhi_wake_db_clear_valid(sc))
1645 qwz_mhi_device_wake(sc);
1646
1647 return 0;
1648 }
1649
1650 void
qwz_pci_bus_release(struct qwz_softc * sc)1651 qwz_pci_bus_release(struct qwz_softc *sc)
1652 {
1653 if (qwz_mhi_wake_db_clear_valid(sc))
1654 qwz_mhi_device_zzz(sc);
1655 }
1656
1657 uint32_t
qwz_pci_get_window_start(struct qwz_softc * sc,uint32_t offset)1658 qwz_pci_get_window_start(struct qwz_softc *sc, uint32_t offset)
1659 {
1660 if (!sc->static_window_map)
1661 return ATH12K_PCI_WINDOW_START;
1662
1663 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH12K_PCI_WINDOW_RANGE_MASK)
1664 /* if offset lies within DP register range, use 3rd window */
1665 return 3 * ATH12K_PCI_WINDOW_START;
1666 else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG) <
1667 ATH12K_PCI_WINDOW_RANGE_MASK)
1668 /* if offset lies within CE register range, use 2nd window */
1669 return 2 * ATH12K_PCI_WINDOW_START;
1670 else
1671 return ATH12K_PCI_WINDOW_START;
1672 }
1673
1674 void
qwz_pci_select_window(struct qwz_softc * sc,uint32_t offset)1675 qwz_pci_select_window(struct qwz_softc *sc, uint32_t offset)
1676 {
1677 struct qwz_pci_softc *psc = (struct qwz_pci_softc *)sc;
1678 uint32_t window = FIELD_GET(ATH12K_PCI_WINDOW_VALUE_MASK, offset);
1679
1680 #if notyet
1681 lockdep_assert_held(&ab_pci->window_lock);
1682 #endif
1683
1684 /*
1685 * Preserve the static window configuration and reset only
1686 * dynamic window.
1687 */
1688 window |= psc->register_window & ATH12K_PCI_WINDOW_STATIC_MASK;
1689
1690 if (window != psc->register_window) {
1691 qwz_pci_write(sc, ATH12K_PCI_WINDOW_REG_ADDRESS,
1692 ATH12K_PCI_WINDOW_ENABLE_BIT | window);
1693 (void) qwz_pci_read(sc, ATH12K_PCI_WINDOW_REG_ADDRESS);
1694 psc->register_window = window;
1695 }
1696 }
1697
1698 static inline bool
qwz_pci_is_offset_within_mhi_region(uint32_t offset)1699 qwz_pci_is_offset_within_mhi_region(uint32_t offset)
1700 {
1701 return (offset >= PCI_MHIREGLEN_REG && offset <= PCI_MHI_REGION_END);
1702 }
1703
1704 void
qwz_pci_window_write32(struct qwz_softc * sc,uint32_t offset,uint32_t value)1705 qwz_pci_window_write32(struct qwz_softc *sc, uint32_t offset, uint32_t value)
1706 {
1707 uint32_t window_start;
1708
1709 window_start = qwz_pci_get_window_start(sc, offset);
1710
1711 if (window_start == ATH12K_PCI_WINDOW_START) {
1712 #if notyet
1713 spin_lock_bh(&ab_pci->window_lock);
1714 #endif
1715 qwz_pci_select_window(sc, offset);
1716
1717 if (qwz_pci_is_offset_within_mhi_region(offset)) {
1718 offset = offset - PCI_MHIREGLEN_REG;
1719 qwz_pci_write(sc, offset & ATH12K_PCI_WINDOW_RANGE_MASK,
1720 value);
1721 } else {
1722 qwz_pci_write(sc, window_start +
1723 (offset & ATH12K_PCI_WINDOW_RANGE_MASK), value);
1724 }
1725 #if notyet
1726 spin_unlock_bh(&ab_pci->window_lock);
1727 #endif
1728 } else {
1729 qwz_pci_write(sc, window_start +
1730 (offset & ATH12K_PCI_WINDOW_RANGE_MASK), value);
1731 }
1732 }
1733
1734 uint32_t
qwz_pci_window_read32(struct qwz_softc * sc,uint32_t offset)1735 qwz_pci_window_read32(struct qwz_softc *sc, uint32_t offset)
1736 {
1737 uint32_t window_start, val;
1738
1739 window_start = qwz_pci_get_window_start(sc, offset);
1740
1741 if (window_start == ATH12K_PCI_WINDOW_START) {
1742 #if notyet
1743 spin_lock_bh(&ab_pci->window_lock);
1744 #endif
1745 qwz_pci_select_window(sc, offset);
1746
1747 if (qwz_pci_is_offset_within_mhi_region(offset)) {
1748 offset = offset - PCI_MHIREGLEN_REG;
1749 val = qwz_pci_read(sc,
1750 offset & ATH12K_PCI_WINDOW_RANGE_MASK);
1751 } else {
1752 val = qwz_pci_read(sc, window_start +
1753 (offset & ATH12K_PCI_WINDOW_RANGE_MASK));
1754 }
1755 #if notyet
1756 spin_unlock_bh(&ab_pci->window_lock);
1757 #endif
1758 } else {
1759 val = qwz_pci_read(sc, window_start +
1760 (offset & ATH12K_PCI_WINDOW_RANGE_MASK));
1761 }
1762
1763 return val;
1764 }
1765
1766 void
qwz_pci_select_static_window(struct qwz_softc * sc)1767 qwz_pci_select_static_window(struct qwz_softc *sc)
1768 {
1769 uint32_t umac_window;
1770 uint32_t ce_window;
1771 uint32_t window;
1772
1773 umac_window = FIELD_GET(ATH12K_PCI_WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET);
1774 ce_window = FIELD_GET(ATH12K_PCI_WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE);
1775 window = (umac_window << 12) | (ce_window << 6);
1776
1777 qwz_pci_write(sc, ATH12K_PCI_WINDOW_REG_ADDRESS,
1778 ATH12K_PCI_WINDOW_ENABLE_BIT | window);
1779 }
1780
1781 void
qwz_pci_soc_global_reset(struct qwz_softc * sc)1782 qwz_pci_soc_global_reset(struct qwz_softc *sc)
1783 {
1784 uint32_t val, msecs;
1785
1786 val = qwz_pcic_read32(sc, PCIE_SOC_GLOBAL_RESET);
1787
1788 val |= PCIE_SOC_GLOBAL_RESET_V;
1789
1790 qwz_pcic_write32(sc, PCIE_SOC_GLOBAL_RESET, val);
1791
1792 /* TODO: exact time to sleep is uncertain */
1793 msecs = 10;
1794 DELAY(msecs * 1000);
1795
1796 /* Need to toggle V bit back otherwise stuck in reset status */
1797 val &= ~PCIE_SOC_GLOBAL_RESET_V;
1798
1799 qwz_pcic_write32(sc, PCIE_SOC_GLOBAL_RESET, val);
1800
1801 DELAY(msecs * 1000);
1802
1803 val = qwz_pcic_read32(sc, PCIE_SOC_GLOBAL_RESET);
1804 if (val == 0xffffffff)
1805 printf("%s: link down error during global reset\n",
1806 sc->sc_dev.dv_xname);
1807 }
1808
1809 void
qwz_pci_clear_dbg_registers(struct qwz_softc * sc)1810 qwz_pci_clear_dbg_registers(struct qwz_softc *sc)
1811 {
1812 uint32_t val;
1813
1814 /* read cookie */
1815 val = qwz_pcic_read32(sc, PCIE_Q6_COOKIE_ADDR);
1816 DPRINTF("%s: cookie:0x%x\n", sc->sc_dev.dv_xname, val);
1817
1818 val = qwz_pcic_read32(sc, WLAON_WARM_SW_ENTRY);
1819 DPRINTF("%s: WLAON_WARM_SW_ENTRY 0x%x\n", sc->sc_dev.dv_xname, val);
1820
1821 /* TODO: exact time to sleep is uncertain */
1822 DELAY(10 * 1000);
1823
1824 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from
1825 * continuing warm path and entering dead loop.
1826 */
1827 qwz_pcic_write32(sc, WLAON_WARM_SW_ENTRY, 0);
1828 DELAY(10 * 1000);
1829
1830 val = qwz_pcic_read32(sc, WLAON_WARM_SW_ENTRY);
1831 DPRINTF("%s: WLAON_WARM_SW_ENTRY 0x%x\n", sc->sc_dev.dv_xname, val);
1832
1833 /* A read clear register. clear the register to prevent
1834 * Q6 from entering wrong code path.
1835 */
1836 val = qwz_pcic_read32(sc, WLAON_SOC_RESET_CAUSE_REG);
1837 DPRINTF("%s: soc reset cause:%d\n", sc->sc_dev.dv_xname, val);
1838 }
1839
1840 int
qwz_pci_set_link_reg(struct qwz_softc * sc,uint32_t offset,uint32_t value,uint32_t mask)1841 qwz_pci_set_link_reg(struct qwz_softc *sc, uint32_t offset, uint32_t value,
1842 uint32_t mask)
1843 {
1844 uint32_t v;
1845 int i;
1846
1847 v = qwz_pcic_read32(sc, offset);
1848 if ((v & mask) == value)
1849 return 0;
1850
1851 for (i = 0; i < 10; i++) {
1852 qwz_pcic_write32(sc, offset, (v & ~mask) | value);
1853
1854 v = qwz_pcic_read32(sc, offset);
1855 if ((v & mask) == value)
1856 return 0;
1857
1858 delay((2 * 1000));
1859 }
1860
1861 DPRINTF("failed to set pcie link register 0x%08x: 0x%08x != 0x%08x\n",
1862 offset, v & mask, value);
1863
1864 return ETIMEDOUT;
1865 }
1866
1867 int
qwz_pci_fix_l1ss(struct qwz_softc * sc)1868 qwz_pci_fix_l1ss(struct qwz_softc *sc)
1869 {
1870 int ret;
1871
1872 ret = qwz_pci_set_link_reg(sc,
1873 PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(sc),
1874 PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL,
1875 PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK);
1876 if (ret) {
1877 DPRINTF("failed to set sysclk: %d\n", ret);
1878 return ret;
1879 }
1880
1881 ret = qwz_pci_set_link_reg(sc,
1882 PCIE_PCS_OSC_DTCT_CONFIG1_REG(sc),
1883 PCIE_PCS_OSC_DTCT_CONFIG1_VAL,
1884 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
1885 if (ret) {
1886 DPRINTF("failed to set dtct config1 error: %d\n", ret);
1887 return ret;
1888 }
1889
1890 ret = qwz_pci_set_link_reg(sc,
1891 PCIE_PCS_OSC_DTCT_CONFIG2_REG(sc),
1892 PCIE_PCS_OSC_DTCT_CONFIG2_VAL,
1893 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
1894 if (ret) {
1895 DPRINTF("failed to set dtct config2: %d\n", ret);
1896 return ret;
1897 }
1898
1899 ret = qwz_pci_set_link_reg(sc,
1900 PCIE_PCS_OSC_DTCT_CONFIG4_REG(sc),
1901 PCIE_PCS_OSC_DTCT_CONFIG4_VAL,
1902 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
1903 if (ret) {
1904 DPRINTF("failed to set dtct config4: %d\n", ret);
1905 return ret;
1906 }
1907
1908 return 0;
1909 }
1910
1911 void
qwz_pci_enable_ltssm(struct qwz_softc * sc)1912 qwz_pci_enable_ltssm(struct qwz_softc *sc)
1913 {
1914 uint32_t val;
1915 int i;
1916
1917 val = qwz_pcic_read32(sc, PCIE_PCIE_PARF_LTSSM);
1918
1919 /* PCIE link seems very unstable after the Hot Reset*/
1920 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) {
1921 if (val == 0xffffffff)
1922 DELAY(5 * 1000);
1923
1924 qwz_pcic_write32(sc, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE);
1925 val = qwz_pcic_read32(sc, PCIE_PCIE_PARF_LTSSM);
1926 }
1927
1928 DPRINTF("%s: pci ltssm 0x%x\n", sc->sc_dev.dv_xname, val);
1929
1930 val = qwz_pcic_read32(sc, GCC_GCC_PCIE_HOT_RST);
1931 val |= GCC_GCC_PCIE_HOT_RST_VAL;
1932 qwz_pcic_write32(sc, GCC_GCC_PCIE_HOT_RST, val);
1933 val = qwz_pcic_read32(sc, GCC_GCC_PCIE_HOT_RST);
1934
1935 DPRINTF("%s: pci pcie_hot_rst 0x%x\n", sc->sc_dev.dv_xname, val);
1936
1937 DELAY(5 * 1000);
1938 }
1939
1940 void
qwz_pci_clear_all_intrs(struct qwz_softc * sc)1941 qwz_pci_clear_all_intrs(struct qwz_softc *sc)
1942 {
1943 /* This is a WAR for PCIE Hotreset.
1944 * When target receive Hotreset, but will set the interrupt.
1945 * So when download SBL again, SBL will open Interrupt and
1946 * receive it, and crash immediately.
1947 */
1948 qwz_pcic_write32(sc, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL);
1949 }
1950
1951 void
qwz_pci_set_wlaon_pwr_ctrl(struct qwz_softc * sc)1952 qwz_pci_set_wlaon_pwr_ctrl(struct qwz_softc *sc)
1953 {
1954 uint32_t val;
1955
1956 val = qwz_pcic_read32(sc, WLAON_QFPROM_PWR_CTRL_REG);
1957 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK;
1958 qwz_pcic_write32(sc, WLAON_QFPROM_PWR_CTRL_REG, val);
1959 }
1960
1961 void
qwz_pci_force_wake(struct qwz_softc * sc)1962 qwz_pci_force_wake(struct qwz_softc *sc)
1963 {
1964 qwz_pcic_write32(sc, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1);
1965 DELAY(5 * 1000);
1966 }
1967
1968 void
qwz_pci_sw_reset(struct qwz_softc * sc,bool power_on)1969 qwz_pci_sw_reset(struct qwz_softc *sc, bool power_on)
1970 {
1971 DELAY(100 * 1000); /* msecs */
1972
1973 if (power_on) {
1974 qwz_pci_enable_ltssm(sc);
1975 qwz_pci_clear_all_intrs(sc);
1976 qwz_pci_set_wlaon_pwr_ctrl(sc);
1977 if (sc->hw_params.fix_l1ss)
1978 qwz_pci_fix_l1ss(sc);
1979 }
1980
1981 qwz_mhi_clear_vector(sc);
1982 qwz_pci_clear_dbg_registers(sc);
1983 qwz_pci_soc_global_reset(sc);
1984 qwz_mhi_reset_device(sc, 0);
1985 }
1986
1987 void
qwz_pci_msi_config(struct qwz_softc * sc,bool enable)1988 qwz_pci_msi_config(struct qwz_softc *sc, bool enable)
1989 {
1990 struct qwz_pci_softc *psc = (struct qwz_pci_softc *)sc;
1991 uint32_t val;
1992
1993 val = pci_conf_read(psc->sc_pc, psc->sc_tag,
1994 psc->sc_msi_off + PCI_MSI_MC);
1995
1996 if (enable)
1997 val |= PCI_MSI_MC_MSIE;
1998 else
1999 val &= ~PCI_MSI_MC_MSIE;
2000
2001 pci_conf_write(psc->sc_pc, psc->sc_tag, psc->sc_msi_off + PCI_MSI_MC,
2002 val);
2003 }
2004
2005 void
qwz_pci_msi_enable(struct qwz_softc * sc)2006 qwz_pci_msi_enable(struct qwz_softc *sc)
2007 {
2008 qwz_pci_msi_config(sc, true);
2009 }
2010
2011 void
qwz_pci_msi_disable(struct qwz_softc * sc)2012 qwz_pci_msi_disable(struct qwz_softc *sc)
2013 {
2014 qwz_pci_msi_config(sc, false);
2015 }
2016
2017 void
qwz_pci_aspm_disable(struct qwz_softc * sc)2018 qwz_pci_aspm_disable(struct qwz_softc *sc)
2019 {
2020 struct qwz_pci_softc *psc = (struct qwz_pci_softc *)sc;
2021
2022 psc->sc_lcsr = pci_conf_read(psc->sc_pc, psc->sc_tag,
2023 psc->sc_cap_off + PCI_PCIE_LCSR);
2024
2025 DPRINTF("%s: pci link_ctl 0x%04x L0s %d L1 %d\n", sc->sc_dev.dv_xname,
2026 (uint16_t)psc->sc_lcsr, (psc->sc_lcsr & PCI_PCIE_LCSR_ASPM_L0S),
2027 (psc->sc_lcsr & PCI_PCIE_LCSR_ASPM_L1));
2028
2029 /* disable L0s and L1 */
2030 pci_conf_write(psc->sc_pc, psc->sc_tag, psc->sc_cap_off + PCI_PCIE_LCSR,
2031 psc->sc_lcsr & ~(PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1));
2032
2033 psc->sc_flags |= ATH12K_PCI_ASPM_RESTORE;
2034 }
2035
2036 void
qwz_pci_aspm_restore(struct qwz_softc * sc)2037 qwz_pci_aspm_restore(struct qwz_softc *sc)
2038 {
2039 struct qwz_pci_softc *psc = (struct qwz_pci_softc *)sc;
2040
2041 if (psc->sc_flags & ATH12K_PCI_ASPM_RESTORE) {
2042 pci_conf_write(psc->sc_pc, psc->sc_tag,
2043 psc->sc_cap_off + PCI_PCIE_LCSR, psc->sc_lcsr);
2044 psc->sc_flags &= ~ATH12K_PCI_ASPM_RESTORE;
2045 }
2046 }
2047
2048 int
qwz_pci_power_up(struct qwz_softc * sc)2049 qwz_pci_power_up(struct qwz_softc *sc)
2050 {
2051 struct qwz_pci_softc *psc = (struct qwz_pci_softc *)sc;
2052 int error;
2053
2054 psc->register_window = 0;
2055 clear_bit(ATH12K_FLAG_DEVICE_INIT_DONE, sc->sc_flags);
2056
2057 qwz_pci_sw_reset(sc, true);
2058
2059 /* Disable ASPM during firmware download due to problems switching
2060 * to AMSS state.
2061 */
2062 qwz_pci_aspm_disable(sc);
2063
2064 qwz_pci_msi_enable(sc);
2065
2066 error = qwz_mhi_start(psc);
2067 if (error)
2068 return error;
2069
2070 if (sc->static_window_map)
2071 qwz_pci_select_static_window(sc);
2072
2073 return 0;
2074 }
2075
2076 void
qwz_pci_power_down(struct qwz_softc * sc)2077 qwz_pci_power_down(struct qwz_softc *sc)
2078 {
2079 /* restore aspm in case firmware bootup fails */
2080 qwz_pci_aspm_restore(sc);
2081
2082 qwz_pci_force_wake(sc);
2083
2084 qwz_pci_msi_disable(sc);
2085
2086 qwz_mhi_stop(sc);
2087 clear_bit(ATH12K_FLAG_DEVICE_INIT_DONE, sc->sc_flags);
2088 qwz_pci_sw_reset(sc, false);
2089 }
2090
2091 /*
2092 * MHI
2093 */
2094 int
qwz_mhi_register(struct qwz_softc * sc)2095 qwz_mhi_register(struct qwz_softc *sc)
2096 {
2097 DNPRINTF(QWZ_D_MHI, "%s: STUB %s()\n", sc->sc_dev.dv_xname, __func__);
2098 return 0;
2099 }
2100
2101 void
qwz_mhi_unregister(struct qwz_softc * sc)2102 qwz_mhi_unregister(struct qwz_softc *sc)
2103 {
2104 DNPRINTF(QWZ_D_MHI, "%s: STUB %s()\n", sc->sc_dev.dv_xname, __func__);
2105 }
2106
2107 // XXX MHI is GPLd - we provide a compatible bare-bones implementation
2108 #define MHI_CFG 0x10
2109 #define MHI_CFG_NHWER_MASK GENMASK(31, 24)
2110 #define MHI_CFG_NHWER_SHFT 24
2111 #define MHI_CFG_NER_MASK GENMASK(23, 16)
2112 #define MHI_CFG_NER_SHFT 16
2113 #define MHI_CFG_NHWCH_MASK GENMASK(15, 8)
2114 #define MHI_CFG_NHWCH_SHFT 8
2115 #define MHI_CFG_NCH_MASK GENMASK(7, 0)
2116 #define MHI_CHDBOFF 0x18
2117 #define MHI_DEV_WAKE_DB 127
2118 #define MHI_ERDBOFF 0x20
2119 #define MHI_BHI_OFFSET 0x28
2120 #define MHI_BHI_IMGADDR_LOW 0x08
2121 #define MHI_BHI_IMGADDR_HIGH 0x0c
2122 #define MHI_BHI_IMGSIZE 0x10
2123 #define MHI_BHI_IMGTXDB 0x18
2124 #define MHI_BHI_INTVEC 0x20
2125 #define MHI_BHI_EXECENV 0x28
2126 #define MHI_BHI_STATUS 0x2c
2127 #define MHI_BHI_SERIALNU 0x40
2128 #define MHI_BHIE_OFFSET 0x2c
2129 #define MHI_BHIE_TXVECADDR_LOW_OFFS 0x2c
2130 #define MHI_BHIE_TXVECADDR_HIGH_OFFS 0x30
2131 #define MHI_BHIE_TXVECSIZE_OFFS 0x34
2132 #define MHI_BHIE_TXVECDB_OFFS 0x3c
2133 #define MHI_BHIE_TXVECSTATUS_OFFS 0x44
2134 #define MHI_BHIE_RXVECADDR_LOW_OFFS 0x60
2135 #define MHI_BHIE_RXVECSTATUS_OFFS 0x78
2136 #define MHI_CTRL 0x38
2137 #define MHI_CTRL_READY_MASK 0x1
2138 #define MHI_CTRL_RESET_MASK 0x2
2139 #define MHI_CTRL_MHISTATE_MASK GENMASK(15, 8)
2140 #define MHI_CTRL_MHISTATE_SHFT 8
2141 #define MHI_STATUS 0x48
2142 #define MHI_STATUS_MHISTATE_MASK GENMASK(15, 8)
2143 #define MHI_STATUS_MHISTATE_SHFT 8
2144 #define MHI_STATE_RESET 0x0
2145 #define MHI_STATE_READY 0x1
2146 #define MHI_STATE_M0 0x2
2147 #define MHI_STATE_M1 0x3
2148 #define MHI_STATE_M2 0x4
2149 #define MHI_STATE_M3 0x5
2150 #define MHI_STATE_M3_FAST 0x6
2151 #define MHI_STATE_BHI 0x7
2152 #define MHI_STATE_SYS_ERR 0xff
2153 #define MHI_STATUS_READY_MASK 0x1
2154 #define MHI_STATUS_SYSERR_MASK 0x4
2155 #define MHI_CCABAP_LOWER 0x58
2156 #define MHI_CCABAP_HIGHER 0x5c
2157 #define MHI_ECABAP_LOWER 0x60
2158 #define MHI_ECABAP_HIGHER 0x64
2159 #define MHI_CRCBAP_LOWER 0x68
2160 #define MHI_CRCBAP_HIGHER 0x6c
2161 #define MHI_CRDB_LOWER 0x70
2162 #define MHI_CRDB_HIGHER 0x74
2163 #define MHI_CTRLBASE_LOWER 0x80
2164 #define MHI_CTRLBASE_HIGHER 0x84
2165 #define MHI_CTRLLIMIT_LOWER 0x88
2166 #define MHI_CTRLLIMIT_HIGHER 0x8c
2167 #define MHI_DATABASE_LOWER 0x98
2168 #define MHI_DATABASE_HIGHER 0x9c
2169 #define MHI_DATALIMIT_LOWER 0xa0
2170 #define MHI_DATALIMIT_HIGHER 0xa4
2171
2172 #define MHI_EE_PBL 0x0 /* Primary Bootloader */
2173 #define MHI_EE_SBL 0x1 /* Secondary Bootloader */
2174 #define MHI_EE_AMSS 0x2 /* Modem, aka the primary runtime EE */
2175 #define MHI_EE_RDDM 0x3 /* Ram dump download mode */
2176 #define MHI_EE_WFW 0x4 /* WLAN firmware mode */
2177 #define MHI_EE_PTHRU 0x5 /* Passthrough */
2178 #define MHI_EE_EDL 0x6 /* Embedded downloader */
2179 #define MHI_EE_FP 0x7 /* Flash Programmer Environment */
2180
2181 #define MHI_IN_PBL(e) (e == MHI_EE_PBL || e == MHI_EE_PTHRU || e == MHI_EE_EDL)
2182 #define MHI_POWER_UP_CAPABLE(e) (MHI_IN_PBL(e) || e == MHI_EE_AMSS)
2183 #define MHI_IN_MISSION_MODE(e) \
2184 (e == MHI_EE_AMSS || e == MHI_EE_WFW || e == MHI_EE_FP)
2185
2186 /* BHI register bits */
2187 #define MHI_BHI_TXDB_SEQNUM_BMSK GENMASK(29, 0)
2188 #define MHI_BHI_TXDB_SEQNUM_SHFT 0
2189 #define MHI_BHI_STATUS_MASK GENMASK(31, 30)
2190 #define MHI_BHI_STATUS_SHFT 30
2191 #define MHI_BHI_STATUS_ERROR 0x03
2192 #define MHI_BHI_STATUS_SUCCESS 0x02
2193 #define MHI_BHI_STATUS_RESET 0x00
2194
2195 /* MHI BHIE registers */
2196 #define MHI_BHIE_MSMSOCID_OFFS 0x00
2197 #define MHI_BHIE_RXVECADDR_LOW_OFFS 0x60
2198 #define MHI_BHIE_RXVECADDR_HIGH_OFFS 0x64
2199 #define MHI_BHIE_RXVECSIZE_OFFS 0x68
2200 #define MHI_BHIE_RXVECDB_OFFS 0x70
2201 #define MHI_BHIE_RXVECSTATUS_OFFS 0x78
2202
2203 /* BHIE register bits */
2204 #define MHI_BHIE_TXVECDB_SEQNUM_BMSK GENMASK(29, 0)
2205 #define MHI_BHIE_TXVECDB_SEQNUM_SHFT 0
2206 #define MHI_BHIE_TXVECSTATUS_SEQNUM_BMSK GENMASK(29, 0)
2207 #define MHI_BHIE_TXVECSTATUS_SEQNUM_SHFT 0
2208 #define MHI_BHIE_TXVECSTATUS_STATUS_BMSK GENMASK(31, 30)
2209 #define MHI_BHIE_TXVECSTATUS_STATUS_SHFT 30
2210 #define MHI_BHIE_TXVECSTATUS_STATUS_RESET 0x00
2211 #define MHI_BHIE_TXVECSTATUS_STATUS_XFER_COMPL 0x02
2212 #define MHI_BHIE_TXVECSTATUS_STATUS_ERROR 0x03
2213 #define MHI_BHIE_RXVECDB_SEQNUM_BMSK GENMASK(29, 0)
2214 #define MHI_BHIE_RXVECDB_SEQNUM_SHFT 0
2215 #define MHI_BHIE_RXVECSTATUS_SEQNUM_BMSK GENMASK(29, 0)
2216 #define MHI_BHIE_RXVECSTATUS_SEQNUM_SHFT 0
2217 #define MHI_BHIE_RXVECSTATUS_STATUS_BMSK GENMASK(31, 30)
2218 #define MHI_BHIE_RXVECSTATUS_STATUS_SHFT 30
2219 #define MHI_BHIE_RXVECSTATUS_STATUS_RESET 0x00
2220 #define MHI_BHIE_RXVECSTATUS_STATUS_XFER_COMPL 0x02
2221 #define MHI_BHIE_RXVECSTATUS_STATUS_ERROR 0x03
2222
2223 #define MHI_EV_CC_INVALID 0x0
2224 #define MHI_EV_CC_SUCCESS 0x1
2225 #define MHI_EV_CC_EOT 0x2
2226 #define MHI_EV_CC_OVERFLOW 0x3
2227 #define MHI_EV_CC_EOB 0x4
2228 #define MHI_EV_CC_OOB 0x5
2229 #define MHI_EV_CC_DB_MODE 0x6
2230 #define MHI_EV_CC_UNDEFINED_ERR 0x10
2231 #define MHI_EV_CC_BAD_TRE 0x11
2232
2233 #define MHI_CMD_NOP 01
2234 #define MHI_CMD_RESET_CHAN 16
2235 #define MHI_CMD_STOP_CHAN 17
2236 #define MHI_CMD_START_CHAN 18
2237
2238 #define MHI_TRE_CMD_CHID_MASK GENMASK(31, 24)
2239 #define MHI_TRE_CMD_CHID_SHFT 24
2240 #define MHI_TRE_CMD_CMDID_MASK GENMASK(23, 16)
2241 #define MHI_TRE_CMD_CMDID_SHFT 16
2242
2243 #define MHI_TRE0_EV_LEN_MASK GENMASK(15, 0)
2244 #define MHI_TRE0_EV_LEN_SHFT 0
2245 #define MHI_TRE0_EV_CODE_MASK GENMASK(31, 24)
2246 #define MHI_TRE0_EV_CODE_SHFT 24
2247 #define MHI_TRE1_EV_TYPE_MASK GENMASK(23, 16)
2248 #define MHI_TRE1_EV_TYPE_SHFT 16
2249 #define MHI_TRE1_EV_CHID_MASK GENMASK(31, 24)
2250 #define MHI_TRE1_EV_CHID_SHFT 24
2251
2252 #define MHI_TRE0_DATA_LEN_MASK GENMASK(15, 0)
2253 #define MHI_TRE0_DATA_LEN_SHFT 0
2254 #define MHI_TRE1_DATA_CHAIN (1 << 0)
2255 #define MHI_TRE1_DATA_IEOB (1 << 8)
2256 #define MHI_TRE1_DATA_IEOT (1 << 9)
2257 #define MHI_TRE1_DATA_BEI (1 << 10)
2258 #define MHI_TRE1_DATA_TYPE_MASK GENMASK(23, 16)
2259 #define MHI_TRE1_DATA_TYPE_SHIFT 16
2260 #define MHI_TRE1_DATA_TYPE_TRANSFER 0x2
2261
2262 #define MHI_PKT_TYPE_INVALID 0x00
2263 #define MHI_PKT_TYPE_NOOP_CMD 0x01
2264 #define MHI_PKT_TYPE_TRANSFER 0x02
2265 #define MHI_PKT_TYPE_COALESCING 0x08
2266 #define MHI_PKT_TYPE_RESET_CHAN_CMD 0x10
2267 #define MHI_PKT_TYPE_STOP_CHAN_CMD 0x11
2268 #define MHI_PKT_TYPE_START_CHAN_CMD 0x12
2269 #define MHI_PKT_TYPE_STATE_CHANGE_EVENT 0x20
2270 #define MHI_PKT_TYPE_CMD_COMPLETION_EVENT 0x21
2271 #define MHI_PKT_TYPE_TX_EVENT 0x22
2272 #define MHI_PKT_TYPE_RSC_TX_EVENT 0x28
2273 #define MHI_PKT_TYPE_EE_EVENT 0x40
2274 #define MHI_PKT_TYPE_TSYNC_EVENT 0x48
2275 #define MHI_PKT_TYPE_BW_REQ_EVENT 0x50
2276
2277
2278 #define MHI_DMA_VEC_CHUNK_SIZE 524288 /* 512 KB */
2279 struct qwz_dma_vec_entry {
2280 uint64_t paddr;
2281 uint64_t size;
2282 };
2283
2284 void
qwz_mhi_ring_doorbell(struct qwz_softc * sc,uint64_t db_addr,uint64_t val)2285 qwz_mhi_ring_doorbell(struct qwz_softc *sc, uint64_t db_addr, uint64_t val)
2286 {
2287 qwz_pci_write(sc, db_addr + 4, val >> 32);
2288 qwz_pci_write(sc, db_addr, val & 0xffffffff);
2289 }
2290
2291 void
qwz_mhi_device_wake(struct qwz_softc * sc)2292 qwz_mhi_device_wake(struct qwz_softc *sc)
2293 {
2294 struct qwz_pci_softc *psc = (struct qwz_pci_softc *)sc;
2295
2296 /*
2297 * Device wake is async only for now because we do not
2298 * keep track of PM state in software.
2299 */
2300 qwz_mhi_ring_doorbell(sc, psc->wake_db, 1);
2301 }
2302
2303 void
qwz_mhi_device_zzz(struct qwz_softc * sc)2304 qwz_mhi_device_zzz(struct qwz_softc *sc)
2305 {
2306 struct qwz_pci_softc *psc = (struct qwz_pci_softc *)sc;
2307
2308 qwz_mhi_ring_doorbell(sc, psc->wake_db, 0);
2309 }
2310
2311 int
qwz_mhi_wake_db_clear_valid(struct qwz_softc * sc)2312 qwz_mhi_wake_db_clear_valid(struct qwz_softc *sc)
2313 {
2314 struct qwz_pci_softc *psc = (struct qwz_pci_softc *)sc;
2315
2316 return (psc->mhi_state == MHI_STATE_M0); /* TODO other states? */
2317 }
2318
2319 void
qwz_mhi_init_xfer_rings(struct qwz_pci_softc * psc)2320 qwz_mhi_init_xfer_rings(struct qwz_pci_softc *psc)
2321 {
2322 struct qwz_softc *sc = &psc->sc_sc;
2323 int i;
2324 uint32_t chcfg;
2325 struct qwz_pci_xfer_ring *ring;
2326 struct qwz_mhi_chan_ctxt *cbase, *c;
2327
2328 cbase = (struct qwz_mhi_chan_ctxt *)QWZ_DMA_KVA(psc->chan_ctxt);
2329 for (i = 0; i < psc->max_chan; i++) {
2330 c = &cbase[i];
2331 chcfg = le32toh(c->chcfg);
2332 chcfg &= ~(MHI_CHAN_CTX_CHSTATE_MASK |
2333 MHI_CHAN_CTX_BRSTMODE_MASK |
2334 MHI_CHAN_CTX_POLLCFG_MASK);
2335 chcfg |= (MHI_CHAN_CTX_CHSTATE_DISABLED |
2336 (MHI_CHAN_CTX_BRSTMODE_DISABLE <<
2337 MHI_CHAN_CTX_BRSTMODE_SHFT));
2338 c->chcfg = htole32(chcfg);
2339 c->chtype = htole32(MHI_CHAN_TYPE_INVALID);
2340 c->erindex = 0;
2341 }
2342
2343 for (i = 0; i < nitems(psc->xfer_rings); i++) {
2344 ring = &psc->xfer_rings[i];
2345 KASSERT(ring->mhi_chan_id < psc->max_chan);
2346 c = &cbase[ring->mhi_chan_id];
2347 c->chtype = htole32(ring->mhi_chan_direction);
2348 c->erindex = htole32(ring->mhi_chan_event_ring_index);
2349 ring->chan_ctxt = c;
2350 }
2351
2352 bus_dmamap_sync(sc->sc_dmat, QWZ_DMA_MAP(psc->chan_ctxt), 0,
2353 QWZ_DMA_LEN(psc->chan_ctxt), BUS_DMASYNC_PREWRITE);
2354 }
2355
2356 void
qwz_mhi_init_event_rings(struct qwz_pci_softc * psc)2357 qwz_mhi_init_event_rings(struct qwz_pci_softc *psc)
2358 {
2359 struct qwz_softc *sc = &psc->sc_sc;
2360 int i;
2361 uint32_t intmod;
2362 uint64_t paddr, len;
2363 struct qwz_pci_event_ring *ring;
2364 struct qwz_mhi_event_ctxt *c;
2365
2366 c = (struct qwz_mhi_event_ctxt *)QWZ_DMA_KVA(psc->event_ctxt);
2367 for (i = 0; i < nitems(psc->event_rings); i++, c++) {
2368 ring = &psc->event_rings[i];
2369
2370 ring->event_ctxt = c;
2371
2372 intmod = le32toh(c->intmod);
2373 intmod &= ~(MHI_EV_CTX_INTMODC_MASK | MHI_EV_CTX_INTMODT_MASK);
2374 intmod |= (ring->mhi_er_irq_moderation_ms <<
2375 MHI_EV_CTX_INTMODT_SHFT) & MHI_EV_CTX_INTMODT_MASK;
2376 c->intmod = htole32(intmod);
2377
2378 c->ertype = htole32(MHI_ER_TYPE_VALID);
2379 c->msivec = htole32(ring->mhi_er_irq);
2380
2381 paddr = QWZ_DMA_DVA(ring->dmamem);
2382 ring->rp = paddr;
2383 ring->wp = paddr + ring->size -
2384 sizeof(struct qwz_mhi_ring_element);
2385 c->rbase = htole64(paddr);
2386 c->rp = htole64(ring->rp);
2387 c->wp = htole64(ring->wp);
2388
2389 len = sizeof(struct qwz_mhi_ring_element) * ring->num_elements;
2390 c->rlen = htole64(len);
2391 }
2392
2393 bus_dmamap_sync(sc->sc_dmat, QWZ_DMA_MAP(psc->event_ctxt), 0,
2394 QWZ_DMA_LEN(psc->event_ctxt), BUS_DMASYNC_PREWRITE);
2395 }
2396
2397 void
qwz_mhi_init_cmd_ring(struct qwz_pci_softc * psc)2398 qwz_mhi_init_cmd_ring(struct qwz_pci_softc *psc)
2399 {
2400 struct qwz_softc *sc = &psc->sc_sc;
2401 struct qwz_pci_cmd_ring *ring = &psc->cmd_ring;
2402 struct qwz_mhi_cmd_ctxt *c;
2403 uint64_t paddr, len;
2404
2405 paddr = QWZ_DMA_DVA(ring->dmamem);
2406 len = ring->size;
2407
2408 ring->rp = ring->wp = paddr;
2409
2410 c = (struct qwz_mhi_cmd_ctxt *)QWZ_DMA_KVA(psc->cmd_ctxt);
2411 c->rbase = htole64(paddr);
2412 c->rp = htole64(paddr);
2413 c->wp = htole64(paddr);
2414 c->rlen = htole64(len);
2415
2416 bus_dmamap_sync(sc->sc_dmat, QWZ_DMA_MAP(psc->cmd_ctxt), 0,
2417 QWZ_DMA_LEN(psc->cmd_ctxt), BUS_DMASYNC_PREWRITE);
2418 }
2419
2420 void
qwz_mhi_init_dev_ctxt(struct qwz_pci_softc * psc)2421 qwz_mhi_init_dev_ctxt(struct qwz_pci_softc *psc)
2422 {
2423 qwz_mhi_init_xfer_rings(psc);
2424 qwz_mhi_init_event_rings(psc);
2425 qwz_mhi_init_cmd_ring(psc);
2426 }
2427
2428 void *
qwz_pci_cmd_ring_get_elem(struct qwz_pci_cmd_ring * ring,uint64_t ptr)2429 qwz_pci_cmd_ring_get_elem(struct qwz_pci_cmd_ring *ring, uint64_t ptr)
2430 {
2431 uint64_t base = QWZ_DMA_DVA(ring->dmamem), offset;
2432
2433 if (ptr < base || ptr >= base + ring->size)
2434 return NULL;
2435
2436 offset = ptr - base;
2437 if (offset >= ring->size)
2438 return NULL;
2439
2440 return QWZ_DMA_KVA(ring->dmamem) + offset;
2441 }
2442
2443 int
qwz_mhi_cmd_ring_submit(struct qwz_pci_softc * psc,struct qwz_pci_cmd_ring * ring)2444 qwz_mhi_cmd_ring_submit(struct qwz_pci_softc *psc,
2445 struct qwz_pci_cmd_ring *ring)
2446 {
2447 struct qwz_softc *sc = &psc->sc_sc;
2448 uint64_t base = QWZ_DMA_DVA(ring->dmamem);
2449 struct qwz_mhi_cmd_ctxt *c;
2450
2451 if (ring->queued >= ring->num_elements)
2452 return 1;
2453
2454 if (ring->wp + sizeof(struct qwz_mhi_ring_element) >= base + ring->size)
2455 ring->wp = base;
2456 else
2457 ring->wp += sizeof(struct qwz_mhi_ring_element);
2458
2459 bus_dmamap_sync(sc->sc_dmat, QWZ_DMA_MAP(psc->cmd_ctxt), 0,
2460 QWZ_DMA_LEN(psc->cmd_ctxt), BUS_DMASYNC_POSTREAD);
2461
2462 c = (struct qwz_mhi_cmd_ctxt *)QWZ_DMA_KVA(psc->cmd_ctxt);
2463 c->wp = htole64(ring->wp);
2464
2465 bus_dmamap_sync(sc->sc_dmat, QWZ_DMA_MAP(psc->cmd_ctxt), 0,
2466 QWZ_DMA_LEN(psc->cmd_ctxt), BUS_DMASYNC_PREWRITE);
2467
2468 ring->queued++;
2469 qwz_mhi_ring_doorbell(sc, MHI_CRDB_LOWER, ring->wp);
2470 return 0;
2471 }
2472
2473 int
qwz_mhi_send_cmd(struct qwz_pci_softc * psc,uint32_t cmd,uint32_t chan)2474 qwz_mhi_send_cmd(struct qwz_pci_softc *psc, uint32_t cmd, uint32_t chan)
2475 {
2476 struct qwz_softc *sc = &psc->sc_sc;
2477 struct qwz_pci_cmd_ring *ring = &psc->cmd_ring;
2478 struct qwz_mhi_ring_element *e;
2479
2480 if (ring->queued >= ring->num_elements) {
2481 printf("%s: command ring overflow\n", sc->sc_dev.dv_xname);
2482 return 1;
2483 }
2484
2485 e = qwz_pci_cmd_ring_get_elem(ring, ring->wp);
2486 if (e == NULL)
2487 return 1;
2488
2489 e->ptr = 0ULL;
2490 e->dword[0] = 0;
2491 e->dword[1] = htole32(
2492 ((chan << MHI_TRE_CMD_CHID_SHFT) & MHI_TRE_CMD_CHID_MASK) |
2493 ((cmd << MHI_TRE_CMD_CMDID_SHFT) & MHI_TRE_CMD_CMDID_MASK));
2494
2495 return qwz_mhi_cmd_ring_submit(psc, ring);
2496 }
2497
2498 void *
qwz_pci_xfer_ring_get_elem(struct qwz_pci_xfer_ring * ring,uint64_t wp)2499 qwz_pci_xfer_ring_get_elem(struct qwz_pci_xfer_ring *ring, uint64_t wp)
2500 {
2501 uint64_t base = QWZ_DMA_DVA(ring->dmamem), offset;
2502 void *addr = QWZ_DMA_KVA(ring->dmamem);
2503
2504 if (wp < base)
2505 return NULL;
2506
2507 offset = wp - base;
2508 if (offset >= ring->size)
2509 return NULL;
2510
2511 return addr + offset;
2512 }
2513
2514 struct qwz_xfer_data *
qwz_pci_xfer_ring_get_data(struct qwz_pci_xfer_ring * ring,uint64_t wp)2515 qwz_pci_xfer_ring_get_data(struct qwz_pci_xfer_ring *ring, uint64_t wp)
2516 {
2517 uint64_t base = QWZ_DMA_DVA(ring->dmamem), offset;
2518
2519 if (wp < base)
2520 return NULL;
2521
2522 offset = wp - base;
2523 if (offset >= ring->size)
2524 return NULL;
2525
2526 return &ring->data[offset / sizeof(ring->data[0])];
2527 }
2528
2529 int
qwz_mhi_submit_xfer(struct qwz_softc * sc,struct mbuf * m)2530 qwz_mhi_submit_xfer(struct qwz_softc *sc, struct mbuf *m)
2531 {
2532 struct qwz_pci_softc *psc = (struct qwz_pci_softc *)sc;
2533 struct qwz_pci_xfer_ring *ring;
2534 struct qwz_mhi_ring_element *e;
2535 struct qwz_xfer_data *xfer;
2536 uint64_t paddr, base;
2537 int err;
2538
2539 ring = &psc->xfer_rings[QWZ_PCI_XFER_RING_IPCR_OUTBOUND];
2540
2541 if (ring->queued >= ring->num_elements)
2542 return 1;
2543
2544 if (m->m_pkthdr.len > QWZ_PCI_XFER_MAX_DATA_SIZE) {
2545 /* TODO: chunk xfers */
2546 printf("%s: xfer too large: %d bytes\n", __func__, m->m_pkthdr.len);
2547 return 1;
2548
2549 }
2550
2551 e = qwz_pci_xfer_ring_get_elem(ring, ring->wp);
2552 if (e == NULL)
2553 return 1;
2554
2555 xfer = qwz_pci_xfer_ring_get_data(ring, ring->wp);
2556 if (xfer == NULL || xfer->m != NULL)
2557 return 1;
2558
2559 err = bus_dmamap_load_mbuf(sc->sc_dmat, xfer->map, m,
2560 BUS_DMA_NOWAIT | BUS_DMA_WRITE);
2561 if (err && err != EFBIG) {
2562 printf("%s: can't map mbuf (error %d)\n",
2563 sc->sc_dev.dv_xname, err);
2564 return err;
2565 }
2566 if (err) {
2567 /* Too many DMA segments, linearize mbuf. */
2568 if (m_defrag(m, M_DONTWAIT))
2569 return ENOBUFS;
2570 err = bus_dmamap_load_mbuf(sc->sc_dmat, xfer->map, m,
2571 BUS_DMA_NOWAIT | BUS_DMA_WRITE);
2572 if (err) {
2573 printf("%s: can't map mbuf (error %d)\n",
2574 sc->sc_dev.dv_xname, err);
2575 return err;
2576 }
2577 }
2578
2579 bus_dmamap_sync(sc->sc_dmat, xfer->map, 0, m->m_pkthdr.len,
2580 BUS_DMASYNC_PREWRITE);
2581
2582 xfer->m = m;
2583 paddr = xfer->map->dm_segs[0].ds_addr;
2584
2585 e->ptr = htole64(paddr);
2586 e->dword[0] = htole32((m->m_pkthdr.len << MHI_TRE0_DATA_LEN_SHFT) &
2587 MHI_TRE0_DATA_LEN_MASK);
2588 e->dword[1] = htole32(MHI_TRE1_DATA_IEOT |
2589 MHI_TRE1_DATA_TYPE_TRANSFER << MHI_TRE1_DATA_TYPE_SHIFT);
2590
2591 bus_dmamap_sync(sc->sc_dmat, QWZ_DMA_MAP(ring->dmamem),
2592 0, QWZ_DMA_LEN(ring->dmamem), BUS_DMASYNC_PREWRITE);
2593
2594 base = QWZ_DMA_DVA(ring->dmamem);
2595 if (ring->wp + sizeof(struct qwz_mhi_ring_element) >= base + ring->size)
2596 ring->wp = base;
2597 else
2598 ring->wp += sizeof(struct qwz_mhi_ring_element);
2599 ring->queued++;
2600
2601 ring->chan_ctxt->wp = htole64(ring->wp);
2602
2603 bus_dmamap_sync(sc->sc_dmat, QWZ_DMA_MAP(psc->chan_ctxt), 0,
2604 QWZ_DMA_LEN(psc->chan_ctxt), BUS_DMASYNC_PREWRITE);
2605
2606 qwz_mhi_ring_doorbell(sc, ring->db_addr, ring->wp);
2607 return 0;
2608 }
2609
2610 int
qwz_mhi_start_channel(struct qwz_pci_softc * psc,struct qwz_pci_xfer_ring * ring)2611 qwz_mhi_start_channel(struct qwz_pci_softc *psc,
2612 struct qwz_pci_xfer_ring *ring)
2613 {
2614 struct qwz_softc *sc = &psc->sc_sc;
2615 struct qwz_mhi_chan_ctxt *c;
2616 int ret = 0;
2617 uint32_t chcfg;
2618 uint64_t paddr, len;
2619
2620 DNPRINTF(QWZ_D_MHI, "%s: start MHI channel %d in state %d\n", __func__,
2621 ring->mhi_chan_id, ring->mhi_chan_state);
2622
2623 c = ring->chan_ctxt;
2624
2625 chcfg = le32toh(c->chcfg);
2626 chcfg &= ~MHI_CHAN_CTX_CHSTATE_MASK;
2627 chcfg |= MHI_CHAN_CTX_CHSTATE_ENABLED;
2628 c->chcfg = htole32(chcfg);
2629
2630 paddr = QWZ_DMA_DVA(ring->dmamem);
2631 ring->rp = ring->wp = paddr;
2632 c->rbase = htole64(paddr);
2633 c->rp = htole64(ring->rp);
2634 c->wp = htole64(ring->wp);
2635 len = sizeof(struct qwz_mhi_ring_element) * ring->num_elements;
2636 c->rlen = htole64(len);
2637
2638 bus_dmamap_sync(sc->sc_dmat, QWZ_DMA_MAP(psc->chan_ctxt), 0,
2639 QWZ_DMA_LEN(psc->chan_ctxt), BUS_DMASYNC_PREWRITE);
2640
2641 ring->cmd_status = MHI_EV_CC_INVALID;
2642 if (qwz_mhi_send_cmd(psc, MHI_CMD_START_CHAN, ring->mhi_chan_id))
2643 return 1;
2644
2645 while (ring->cmd_status != MHI_EV_CC_SUCCESS) {
2646 ret = tsleep_nsec(&ring->cmd_status, 0, "qwzcmd",
2647 SEC_TO_NSEC(5));
2648 if (ret)
2649 break;
2650 }
2651
2652 if (ret) {
2653 printf("%s: could not start MHI channel %d in state %d: status 0x%x\n",
2654 sc->sc_dev.dv_xname, ring->mhi_chan_id,
2655 ring->mhi_chan_state, ring->cmd_status);
2656 return 1;
2657 }
2658
2659 if (ring->mhi_chan_direction == MHI_CHAN_TYPE_INBOUND) {
2660 uint64_t wp = QWZ_DMA_DVA(ring->dmamem);
2661 int i;
2662
2663 for (i = 0; i < ring->num_elements; i++) {
2664 struct qwz_mhi_ring_element *e;
2665 struct qwz_xfer_data *xfer;
2666 uint64_t paddr;
2667
2668 e = qwz_pci_xfer_ring_get_elem(ring, wp);
2669 xfer = qwz_pci_xfer_ring_get_data(ring, wp);
2670 paddr = xfer->map->dm_segs[0].ds_addr;
2671
2672 e->ptr = htole64(paddr);
2673 e->dword[0] = htole32((QWZ_PCI_XFER_MAX_DATA_SIZE <<
2674 MHI_TRE0_DATA_LEN_SHFT) &
2675 MHI_TRE0_DATA_LEN_MASK);
2676 e->dword[1] = htole32(MHI_TRE1_DATA_IEOT |
2677 MHI_TRE1_DATA_BEI |
2678 MHI_TRE1_DATA_TYPE_TRANSFER <<
2679 MHI_TRE1_DATA_TYPE_SHIFT);
2680
2681 ring->wp = wp;
2682 wp += sizeof(*e);
2683 }
2684
2685 bus_dmamap_sync(sc->sc_dmat, QWZ_DMA_MAP(ring->dmamem), 0,
2686 QWZ_DMA_LEN(ring->dmamem), BUS_DMASYNC_PREWRITE);
2687
2688 qwz_mhi_ring_doorbell(sc, ring->db_addr, ring->wp);
2689 }
2690
2691 return 0;
2692 }
2693
2694 int
qwz_mhi_start_channels(struct qwz_pci_softc * psc)2695 qwz_mhi_start_channels(struct qwz_pci_softc *psc)
2696 {
2697 struct qwz_pci_xfer_ring *ring;
2698 int ret = 0;
2699
2700 qwz_mhi_device_wake(&psc->sc_sc);
2701
2702 ring = &psc->xfer_rings[QWZ_PCI_XFER_RING_IPCR_OUTBOUND];
2703 if (qwz_mhi_start_channel(psc, ring)) {
2704 ret = 1;
2705 goto done;
2706 }
2707
2708 ring = &psc->xfer_rings[QWZ_PCI_XFER_RING_IPCR_INBOUND];
2709 if (qwz_mhi_start_channel(psc, ring))
2710 ret = 1;
2711 done:
2712 qwz_mhi_device_zzz(&psc->sc_sc);
2713 return ret;
2714 }
2715
2716 int
qwz_mhi_start(struct qwz_pci_softc * psc)2717 qwz_mhi_start(struct qwz_pci_softc *psc)
2718 {
2719 struct qwz_softc *sc = &psc->sc_sc;
2720 uint32_t off;
2721 uint32_t ee, state;
2722 int ret;
2723
2724 qwz_mhi_init_dev_ctxt(psc);
2725
2726 psc->bhi_off = qwz_pci_read(sc, MHI_BHI_OFFSET);
2727 DNPRINTF(QWZ_D_MHI, "%s: BHI offset 0x%x\n", __func__, psc->bhi_off);
2728
2729 psc->bhie_off = qwz_pci_read(sc, MHI_BHIE_OFFSET);
2730 DNPRINTF(QWZ_D_MHI, "%s: BHIE offset 0x%x\n", __func__, psc->bhie_off);
2731
2732 /* Clean BHIE RX registers */
2733 for (off = MHI_BHIE_RXVECADDR_LOW_OFFS;
2734 off < (MHI_BHIE_RXVECSTATUS_OFFS - 4);
2735 off += 4)
2736 qwz_pci_write(sc, psc->bhie_off + off, 0x0);
2737
2738 qwz_rddm_prepare(psc);
2739
2740 /* Program BHI INTVEC */
2741 qwz_pci_write(sc, psc->bhi_off + MHI_BHI_INTVEC, 0x00);
2742
2743 /*
2744 * Get BHI execution environment and confirm that it is valid
2745 * for power on.
2746 */
2747 ee = qwz_pci_read(sc, psc->bhi_off + MHI_BHI_EXECENV);
2748 if (!MHI_POWER_UP_CAPABLE(ee)) {
2749 printf("%s: invalid EE for power on: 0x%x\n",
2750 sc->sc_dev.dv_xname, ee);
2751 return 1;
2752 }
2753
2754 /*
2755 * Get MHI state of the device and reset it if it is in system
2756 * error.
2757 */
2758 state = qwz_pci_read(sc, MHI_STATUS);
2759 DNPRINTF(QWZ_D_MHI, "%s: MHI power on with EE: 0x%x, status: 0x%x\n",
2760 sc->sc_dev.dv_xname, ee, state);
2761 state = (state & MHI_STATUS_MHISTATE_MASK) >> MHI_STATUS_MHISTATE_SHFT;
2762 if (state == MHI_STATE_SYS_ERR) {
2763 if (qwz_mhi_reset_device(sc, 0))
2764 return 1;
2765 state = qwz_pci_read(sc, MHI_STATUS);
2766 DNPRINTF(QWZ_D_MHI, "%s: MHI state after reset: 0x%x\n",
2767 sc->sc_dev.dv_xname, state);
2768 state = (state & MHI_STATUS_MHISTATE_MASK) >>
2769 MHI_STATUS_MHISTATE_SHFT;
2770 if (state == MHI_STATE_SYS_ERR) {
2771 printf("%s: MHI stuck in system error state\n",
2772 sc->sc_dev.dv_xname);
2773 return 1;
2774 }
2775 }
2776
2777 psc->bhi_ee = ee;
2778 psc->mhi_state = state;
2779
2780 #if notyet
2781 /* Enable IRQs */
2782 // XXX todo?
2783 #endif
2784
2785 /* Transition to primary runtime. */
2786 if (MHI_IN_PBL(ee)) {
2787 ret = qwz_mhi_fw_load_handler(psc);
2788 if (ret)
2789 return ret;
2790
2791 /* XXX without this delay starting the channels may fail */
2792 delay(1000);
2793 qwz_mhi_start_channels(psc);
2794 } else {
2795 /* XXX Handle partially initialized device...?!? */
2796 ee = qwz_pci_read(sc, psc->bhi_off + MHI_BHI_EXECENV);
2797 if (!MHI_IN_MISSION_MODE(ee)) {
2798 printf("%s: failed to power up MHI, ee=0x%x\n",
2799 sc->sc_dev.dv_xname, ee);
2800 return EIO;
2801 }
2802 }
2803
2804 return 0;
2805 }
2806
2807 void
qwz_mhi_stop(struct qwz_softc * sc)2808 qwz_mhi_stop(struct qwz_softc *sc)
2809 {
2810 qwz_mhi_reset_device(sc, 1);
2811 }
2812
2813 int
qwz_mhi_reset_device(struct qwz_softc * sc,int force)2814 qwz_mhi_reset_device(struct qwz_softc *sc, int force)
2815 {
2816 struct qwz_pci_softc *psc = (struct qwz_pci_softc *)sc;
2817 uint32_t reg;
2818 int ret = 0;
2819
2820 reg = qwz_pcic_read32(sc, MHI_STATUS);
2821
2822 DNPRINTF(QWZ_D_MHI, "%s: MHISTATUS 0x%x\n", sc->sc_dev.dv_xname, reg);
2823 /*
2824 * Observed on QCA6390 that after SOC_GLOBAL_RESET, MHISTATUS
2825 * has SYSERR bit set and thus need to set MHICTRL_RESET
2826 * to clear SYSERR.
2827 */
2828 if (force || (reg & MHI_STATUS_SYSERR_MASK)) {
2829 /* Trigger MHI Reset in device. */
2830 qwz_pcic_write32(sc, MHI_CTRL, MHI_CTRL_RESET_MASK);
2831
2832 /* Wait for the reset bit to be cleared by the device. */
2833 ret = qwz_mhi_await_device_reset(sc);
2834 if (ret)
2835 return ret;
2836
2837 if (psc->bhi_off == 0)
2838 psc->bhi_off = qwz_pci_read(sc, MHI_BHI_OFFSET);
2839
2840 /* Device clear BHI INTVEC so re-program it. */
2841 qwz_pci_write(sc, psc->bhi_off + MHI_BHI_INTVEC, 0x00);
2842 }
2843
2844 return 0;
2845 }
2846
2847 static inline void
qwz_mhi_reset_txvecdb(struct qwz_softc * sc)2848 qwz_mhi_reset_txvecdb(struct qwz_softc *sc)
2849 {
2850 qwz_pcic_write32(sc, PCIE_TXVECDB, 0);
2851 }
2852
2853 static inline void
qwz_mhi_reset_txvecstatus(struct qwz_softc * sc)2854 qwz_mhi_reset_txvecstatus(struct qwz_softc *sc)
2855 {
2856 qwz_pcic_write32(sc, PCIE_TXVECSTATUS, 0);
2857 }
2858
2859 static inline void
qwz_mhi_reset_rxvecdb(struct qwz_softc * sc)2860 qwz_mhi_reset_rxvecdb(struct qwz_softc *sc)
2861 {
2862 qwz_pcic_write32(sc, PCIE_RXVECDB, 0);
2863 }
2864
2865 static inline void
qwz_mhi_reset_rxvecstatus(struct qwz_softc * sc)2866 qwz_mhi_reset_rxvecstatus(struct qwz_softc *sc)
2867 {
2868 qwz_pcic_write32(sc, PCIE_RXVECSTATUS, 0);
2869 }
2870
2871 void
qwz_mhi_clear_vector(struct qwz_softc * sc)2872 qwz_mhi_clear_vector(struct qwz_softc *sc)
2873 {
2874 qwz_mhi_reset_txvecdb(sc);
2875 qwz_mhi_reset_txvecstatus(sc);
2876 qwz_mhi_reset_rxvecdb(sc);
2877 qwz_mhi_reset_rxvecstatus(sc);
2878 }
2879
2880 int
qwz_mhi_fw_load_handler(struct qwz_pci_softc * psc)2881 qwz_mhi_fw_load_handler(struct qwz_pci_softc *psc)
2882 {
2883 struct qwz_softc *sc = &psc->sc_sc;
2884 int ret;
2885 char amss_path[PATH_MAX];
2886 u_char *data;
2887 size_t len;
2888
2889 if (sc->fw_img[QWZ_FW_AMSS].data) {
2890 data = sc->fw_img[QWZ_FW_AMSS].data;
2891 len = sc->fw_img[QWZ_FW_AMSS].size;
2892 } else {
2893 ret = snprintf(amss_path, sizeof(amss_path), "%s-%s-%s",
2894 ATH12K_FW_DIR, sc->hw_params.fw.dir, ATH12K_AMSS_FILE);
2895 if (ret < 0 || ret >= sizeof(amss_path))
2896 return ENOSPC;
2897
2898 ret = loadfirmware(amss_path, &data, &len);
2899 if (ret) {
2900 printf("%s: could not read %s (error %d)\n",
2901 sc->sc_dev.dv_xname, amss_path, ret);
2902 return ret;
2903 }
2904
2905 if (len < MHI_DMA_VEC_CHUNK_SIZE) {
2906 printf("%s: %s is too short, have only %zu bytes\n",
2907 sc->sc_dev.dv_xname, amss_path, len);
2908 free(data, M_DEVBUF, len);
2909 return EINVAL;
2910 }
2911
2912 sc->fw_img[QWZ_FW_AMSS].data = data;
2913 sc->fw_img[QWZ_FW_AMSS].size = len;
2914 }
2915
2916 /* Second-stage boot loader sits in the first 512 KB of image. */
2917 ret = qwz_mhi_fw_load_bhi(psc, data, MHI_DMA_VEC_CHUNK_SIZE);
2918 if (ret != 0) {
2919 printf("%s: could not load firmware %s\n",
2920 sc->sc_dev.dv_xname, amss_path);
2921 return ret;
2922 }
2923
2924 /* Now load the full image. */
2925 ret = qwz_mhi_fw_load_bhie(psc, data, len);
2926 if (ret != 0) {
2927 printf("%s: could not load firmware %s\n",
2928 sc->sc_dev.dv_xname, amss_path);
2929 return ret;
2930 }
2931
2932 while (psc->bhi_ee < MHI_EE_AMSS) {
2933 ret = tsleep_nsec(&psc->bhi_ee, 0, "qwzamss",
2934 SEC_TO_NSEC(5));
2935 if (ret)
2936 break;
2937 }
2938 if (ret != 0) {
2939 printf("%s: device failed to enter AMSS EE\n",
2940 sc->sc_dev.dv_xname);
2941 }
2942
2943 return ret;
2944 }
2945
2946 int
qwz_mhi_await_device_reset(struct qwz_softc * sc)2947 qwz_mhi_await_device_reset(struct qwz_softc *sc)
2948 {
2949 const uint32_t msecs = 24, retries = 2;
2950 uint32_t reg;
2951 int timeout;
2952
2953 /* Poll for CTRL RESET to clear. */
2954 timeout = retries;
2955 while (timeout > 0) {
2956 reg = qwz_pci_read(sc, MHI_CTRL);
2957 DNPRINTF(QWZ_D_MHI, "%s: MHI_CTRL is 0x%x\n", __func__, reg);
2958 if ((reg & MHI_CTRL_RESET_MASK) == 0)
2959 break;
2960 DELAY((msecs / retries) * 1000);
2961 timeout--;
2962 }
2963 if (timeout == 0) {
2964 DNPRINTF(QWZ_D_MHI, "%s: MHI reset failed\n", __func__);
2965 return ETIMEDOUT;
2966 }
2967
2968 return 0;
2969 }
2970
2971 int
qwz_mhi_await_device_ready(struct qwz_softc * sc)2972 qwz_mhi_await_device_ready(struct qwz_softc *sc)
2973 {
2974 uint32_t reg;
2975 int timeout;
2976 const uint32_t msecs = 2000, retries = 4;
2977
2978
2979 /* Poll for READY to be set. */
2980 timeout = retries;
2981 while (timeout > 0) {
2982 reg = qwz_pci_read(sc, MHI_STATUS);
2983 DNPRINTF(QWZ_D_MHI, "%s: MHI_STATUS is 0x%x\n", __func__, reg);
2984 if (reg & MHI_STATUS_READY_MASK) {
2985 reg &= ~MHI_STATUS_READY_MASK;
2986 qwz_pci_write(sc, MHI_STATUS, reg);
2987 break;
2988 }
2989 DELAY((msecs / retries) * 1000);
2990 timeout--;
2991 }
2992 if (timeout == 0) {
2993 printf("%s: MHI not ready\n", sc->sc_dev.dv_xname);
2994 return ETIMEDOUT;
2995 }
2996
2997 return 0;
2998 }
2999
3000 void
qwz_mhi_ready_state_transition(struct qwz_pci_softc * psc)3001 qwz_mhi_ready_state_transition(struct qwz_pci_softc *psc)
3002 {
3003 struct qwz_softc *sc = &psc->sc_sc;
3004 int ret, i;
3005
3006 ret = qwz_mhi_await_device_reset(sc);
3007 if (ret)
3008 return;
3009
3010 ret = qwz_mhi_await_device_ready(sc);
3011 if (ret)
3012 return;
3013
3014 /* Set up memory-mapped IO for channels, events, etc. */
3015 qwz_mhi_init_mmio(psc);
3016
3017 /* Notify event rings. */
3018 for (i = 0; i < nitems(psc->event_rings); i++) {
3019 struct qwz_pci_event_ring *ring = &psc->event_rings[i];
3020 qwz_mhi_ring_doorbell(sc, ring->db_addr, ring->wp);
3021 }
3022
3023 /*
3024 * Set the device into M0 state. The device will transition
3025 * into M0 and the execution environment will switch to SBL.
3026 */
3027 qwz_mhi_set_state(sc, MHI_STATE_M0);
3028 }
3029
3030 void
qwz_mhi_mission_mode_state_transition(struct qwz_pci_softc * psc)3031 qwz_mhi_mission_mode_state_transition(struct qwz_pci_softc *psc)
3032 {
3033 struct qwz_softc *sc = &psc->sc_sc;
3034 int i;
3035
3036 qwz_mhi_device_wake(sc);
3037
3038 /* Notify event rings. */
3039 for (i = 0; i < nitems(psc->event_rings); i++) {
3040 struct qwz_pci_event_ring *ring = &psc->event_rings[i];
3041 qwz_mhi_ring_doorbell(sc, ring->db_addr, ring->wp);
3042 }
3043
3044 /* TODO: Notify transfer/command rings? */
3045
3046 qwz_mhi_device_zzz(sc);
3047 }
3048
3049 void
qwz_mhi_low_power_mode_state_transition(struct qwz_pci_softc * psc)3050 qwz_mhi_low_power_mode_state_transition(struct qwz_pci_softc *psc)
3051 {
3052 struct qwz_softc *sc = &psc->sc_sc;
3053
3054 qwz_mhi_set_state(sc, MHI_STATE_M2);
3055 }
3056
3057 void
qwz_mhi_set_state(struct qwz_softc * sc,uint32_t state)3058 qwz_mhi_set_state(struct qwz_softc *sc, uint32_t state)
3059 {
3060 uint32_t reg;
3061
3062 reg = qwz_pci_read(sc, MHI_CTRL);
3063
3064 if (state != MHI_STATE_RESET) {
3065 reg &= ~MHI_CTRL_MHISTATE_MASK;
3066 reg |= (state << MHI_CTRL_MHISTATE_SHFT) & MHI_CTRL_MHISTATE_MASK;
3067 } else
3068 reg |= MHI_CTRL_RESET_MASK;
3069
3070 qwz_pci_write(sc, MHI_CTRL, reg);
3071 }
3072
3073 void
qwz_mhi_init_mmio(struct qwz_pci_softc * psc)3074 qwz_mhi_init_mmio(struct qwz_pci_softc *psc)
3075 {
3076 struct qwz_softc *sc = &psc->sc_sc;
3077 uint64_t paddr;
3078 uint32_t reg;
3079 int i;
3080
3081 reg = qwz_pci_read(sc, MHI_CHDBOFF);
3082
3083 /* Set device wake doorbell address. */
3084 psc->wake_db = reg + 8 * MHI_DEV_WAKE_DB;
3085
3086 /* Set doorbell address for each transfer ring. */
3087 for (i = 0; i < nitems(psc->xfer_rings); i++) {
3088 struct qwz_pci_xfer_ring *ring = &psc->xfer_rings[i];
3089 ring->db_addr = reg + (8 * ring->mhi_chan_id);
3090 }
3091
3092 reg = qwz_pci_read(sc, MHI_ERDBOFF);
3093 /* Set doorbell address for each event ring. */
3094 for (i = 0; i < nitems(psc->event_rings); i++) {
3095 struct qwz_pci_event_ring *ring = &psc->event_rings[i];
3096 ring->db_addr = reg + (8 * i);
3097 }
3098
3099 paddr = QWZ_DMA_DVA(psc->chan_ctxt);
3100 qwz_pci_write(sc, MHI_CCABAP_HIGHER, paddr >> 32);
3101 qwz_pci_write(sc, MHI_CCABAP_LOWER, paddr & 0xffffffff);
3102
3103 paddr = QWZ_DMA_DVA(psc->event_ctxt);
3104 qwz_pci_write(sc, MHI_ECABAP_HIGHER, paddr >> 32);
3105 qwz_pci_write(sc, MHI_ECABAP_LOWER, paddr & 0xffffffff);
3106
3107 paddr = QWZ_DMA_DVA(psc->cmd_ctxt);
3108 qwz_pci_write(sc, MHI_CRCBAP_HIGHER, paddr >> 32);
3109 qwz_pci_write(sc, MHI_CRCBAP_LOWER, paddr & 0xffffffff);
3110
3111 /* Not (yet?) using fixed memory space from a device-tree. */
3112 qwz_pci_write(sc, MHI_CTRLBASE_HIGHER, 0);
3113 qwz_pci_write(sc, MHI_CTRLBASE_LOWER, 0);
3114 qwz_pci_write(sc, MHI_DATABASE_HIGHER, 0);
3115 qwz_pci_write(sc, MHI_DATABASE_LOWER, 0);
3116 qwz_pci_write(sc, MHI_CTRLLIMIT_HIGHER, 0x0);
3117 qwz_pci_write(sc, MHI_CTRLLIMIT_LOWER, 0xffffffff);
3118 qwz_pci_write(sc, MHI_DATALIMIT_HIGHER, 0x0);
3119 qwz_pci_write(sc, MHI_DATALIMIT_LOWER, 0xffffffff);
3120
3121 reg = qwz_pci_read(sc, MHI_CFG);
3122 reg &= ~(MHI_CFG_NER_MASK | MHI_CFG_NHWER_MASK);
3123 reg |= QWZ_NUM_EVENT_CTX << MHI_CFG_NER_SHFT;
3124 qwz_pci_write(sc, MHI_CFG, reg);
3125 }
3126
3127 int
qwz_mhi_fw_load_bhi(struct qwz_pci_softc * psc,uint8_t * data,size_t len)3128 qwz_mhi_fw_load_bhi(struct qwz_pci_softc *psc, uint8_t *data, size_t len)
3129 {
3130 struct qwz_softc *sc = &psc->sc_sc;
3131 struct qwz_dmamem *data_adm;
3132 uint32_t seq, reg, status = MHI_BHI_STATUS_RESET;
3133 uint64_t paddr;
3134 int ret;
3135
3136 data_adm = qwz_dmamem_alloc(sc->sc_dmat, len, 0);
3137 if (data_adm == NULL) {
3138 printf("%s: could not allocate BHI DMA data buffer\n",
3139 sc->sc_dev.dv_xname);
3140 return 1;
3141 }
3142
3143 /* Copy firmware image to DMA memory. */
3144 memcpy(QWZ_DMA_KVA(data_adm), data, len);
3145
3146 qwz_pci_write(sc, psc->bhi_off + MHI_BHI_STATUS, 0);
3147
3148 /* Set data physical address and length. */
3149 paddr = QWZ_DMA_DVA(data_adm);
3150 qwz_pci_write(sc, psc->bhi_off + MHI_BHI_IMGADDR_HIGH, paddr >> 32);
3151 qwz_pci_write(sc, psc->bhi_off + MHI_BHI_IMGADDR_LOW,
3152 paddr & 0xffffffff);
3153 qwz_pci_write(sc, psc->bhi_off + MHI_BHI_IMGSIZE, len);
3154
3155 /* Set a random transaction sequence number. */
3156 do {
3157 seq = arc4random_uniform(MHI_BHI_TXDB_SEQNUM_BMSK);
3158 } while (seq == 0);
3159 qwz_pci_write(sc, psc->bhi_off + MHI_BHI_IMGTXDB, seq);
3160
3161 /* Wait for completion. */
3162 ret = 0;
3163 while (status != MHI_BHI_STATUS_SUCCESS && psc->bhi_ee < MHI_EE_SBL) {
3164 ret = tsleep_nsec(&psc->bhi_ee, 0, "qwzbhi", SEC_TO_NSEC(5));
3165 if (ret)
3166 break;
3167 reg = qwz_pci_read(sc, psc->bhi_off + MHI_BHI_STATUS);
3168 status = (reg & MHI_BHI_STATUS_MASK) >> MHI_BHI_STATUS_SHFT;
3169 }
3170
3171 if (ret) {
3172 printf("%s: BHI load timeout\n", sc->sc_dev.dv_xname);
3173 reg = qwz_pci_read(sc, psc->bhi_off + MHI_BHI_STATUS);
3174 status = (reg & MHI_BHI_STATUS_MASK) >> MHI_BHI_STATUS_SHFT;
3175 DNPRINTF(QWZ_D_MHI, "%s: BHI status is 0x%x EE is 0x%x\n",
3176 __func__, status, psc->bhi_ee);
3177 }
3178
3179 qwz_dmamem_free(sc->sc_dmat, data_adm);
3180 return ret;
3181 }
3182
3183 int
qwz_mhi_fw_load_bhie(struct qwz_pci_softc * psc,uint8_t * data,size_t len)3184 qwz_mhi_fw_load_bhie(struct qwz_pci_softc *psc, uint8_t *data, size_t len)
3185 {
3186 struct qwz_softc *sc = &psc->sc_sc;
3187 struct qwz_dma_vec_entry *vec;
3188 uint32_t seq, reg, state = MHI_BHIE_TXVECSTATUS_STATUS_RESET;
3189 uint64_t paddr;
3190 const size_t chunk_size = MHI_DMA_VEC_CHUNK_SIZE;
3191 size_t nseg, remain, vec_size;
3192 int i, ret;
3193
3194 nseg = howmany(len, chunk_size);
3195 if (nseg == 0) {
3196 printf("%s: BHIE data too short, have only %zu bytes\n",
3197 sc->sc_dev.dv_xname, len);
3198 return 1;
3199 }
3200
3201 if (psc->amss_data == NULL || QWZ_DMA_LEN(psc->amss_data) < len) {
3202 if (psc->amss_data)
3203 qwz_dmamem_free(sc->sc_dmat, psc->amss_data);
3204 psc->amss_data = qwz_dmamem_alloc(sc->sc_dmat, len, 0);
3205 if (psc->amss_data == NULL) {
3206 printf("%s: could not allocate BHIE DMA data buffer\n",
3207 sc->sc_dev.dv_xname);
3208 return 1;
3209 }
3210 }
3211
3212 vec_size = nseg * sizeof(*vec);
3213 if (psc->amss_vec == NULL || QWZ_DMA_LEN(psc->amss_vec) < vec_size) {
3214 if (psc->amss_vec)
3215 qwz_dmamem_free(sc->sc_dmat, psc->amss_vec);
3216 psc->amss_vec = qwz_dmamem_alloc(sc->sc_dmat, vec_size, 0);
3217 if (psc->amss_vec == NULL) {
3218 printf("%s: could not allocate BHIE DMA vec buffer\n",
3219 sc->sc_dev.dv_xname);
3220 qwz_dmamem_free(sc->sc_dmat, psc->amss_data);
3221 psc->amss_data = NULL;
3222 return 1;
3223 }
3224 }
3225
3226 /* Copy firmware image to DMA memory. */
3227 memcpy(QWZ_DMA_KVA(psc->amss_data), data, len);
3228
3229 /* Create vector which controls chunk-wise DMA copy in hardware. */
3230 paddr = QWZ_DMA_DVA(psc->amss_data);
3231 vec = QWZ_DMA_KVA(psc->amss_vec);
3232 remain = len;
3233 for (i = 0; i < nseg; i++) {
3234 vec[i].paddr = paddr;
3235 if (remain >= chunk_size) {
3236 vec[i].size = chunk_size;
3237 remain -= chunk_size;
3238 paddr += chunk_size;
3239 } else
3240 vec[i].size = remain;
3241 }
3242
3243 /* Set vector physical address and length. */
3244 paddr = QWZ_DMA_DVA(psc->amss_vec);
3245 qwz_pci_write(sc, psc->bhie_off + MHI_BHIE_TXVECADDR_HIGH_OFFS,
3246 paddr >> 32);
3247 qwz_pci_write(sc, psc->bhie_off + MHI_BHIE_TXVECADDR_LOW_OFFS,
3248 paddr & 0xffffffff);
3249 qwz_pci_write(sc, psc->bhie_off + MHI_BHIE_TXVECSIZE_OFFS, vec_size);
3250
3251 /* Set a random transaction sequence number. */
3252 do {
3253 seq = arc4random_uniform(MHI_BHIE_TXVECSTATUS_SEQNUM_BMSK);
3254 } while (seq == 0);
3255 reg = qwz_pci_read(sc, psc->bhie_off + MHI_BHIE_TXVECDB_OFFS);
3256 reg &= ~MHI_BHIE_TXVECDB_SEQNUM_BMSK;
3257 reg |= seq << MHI_BHIE_TXVECDB_SEQNUM_SHFT;
3258 qwz_pci_write(sc, psc->bhie_off + MHI_BHIE_TXVECDB_OFFS, reg);
3259
3260 /* Wait for completion. */
3261 ret = 0;
3262 while (state != MHI_BHIE_TXVECSTATUS_STATUS_XFER_COMPL) {
3263 ret = tsleep_nsec(&psc->bhie_off, 0, "qwzbhie",
3264 SEC_TO_NSEC(5));
3265 if (ret)
3266 break;
3267 reg = qwz_pci_read(sc,
3268 psc->bhie_off + MHI_BHIE_TXVECSTATUS_OFFS);
3269 state = (reg & MHI_BHIE_TXVECSTATUS_STATUS_BMSK) >>
3270 MHI_BHIE_TXVECSTATUS_STATUS_SHFT;
3271 DNPRINTF(QWZ_D_MHI, "%s: txvec state is 0x%x\n", __func__,
3272 state);
3273 }
3274
3275 if (ret) {
3276 printf("%s: BHIE load timeout\n", sc->sc_dev.dv_xname);
3277 return ret;
3278 }
3279 return 0;
3280 }
3281
3282 void
qwz_rddm_prepare(struct qwz_pci_softc * psc)3283 qwz_rddm_prepare(struct qwz_pci_softc *psc)
3284 {
3285 struct qwz_softc *sc = &psc->sc_sc;
3286 struct qwz_dma_vec_entry *vec;
3287 struct qwz_dmamem *data_adm, *vec_adm;
3288 uint32_t seq, reg;
3289 uint64_t paddr;
3290 const size_t len = QWZ_RDDM_DUMP_SIZE;
3291 const size_t chunk_size = MHI_DMA_VEC_CHUNK_SIZE;
3292 size_t nseg, remain, vec_size;
3293 int i;
3294
3295 nseg = howmany(len, chunk_size);
3296 if (nseg == 0) {
3297 printf("%s: RDDM data too short, have only %zu bytes\n",
3298 sc->sc_dev.dv_xname, len);
3299 return;
3300 }
3301
3302 data_adm = qwz_dmamem_alloc(sc->sc_dmat, len, 0);
3303 if (data_adm == NULL) {
3304 printf("%s: could not allocate BHIE DMA data buffer\n",
3305 sc->sc_dev.dv_xname);
3306 return;
3307 }
3308
3309 vec_size = nseg * sizeof(*vec);
3310 vec_adm = qwz_dmamem_alloc(sc->sc_dmat, vec_size, 0);
3311 if (vec_adm == NULL) {
3312 printf("%s: could not allocate BHIE DMA vector buffer\n",
3313 sc->sc_dev.dv_xname);
3314 qwz_dmamem_free(sc->sc_dmat, data_adm);
3315 return;
3316 }
3317
3318 /* Create vector which controls chunk-wise DMA copy from hardware. */
3319 paddr = QWZ_DMA_DVA(data_adm);
3320 vec = QWZ_DMA_KVA(vec_adm);
3321 remain = len;
3322 for (i = 0; i < nseg; i++) {
3323 vec[i].paddr = paddr;
3324 if (remain >= chunk_size) {
3325 vec[i].size = chunk_size;
3326 remain -= chunk_size;
3327 paddr += chunk_size;
3328 } else
3329 vec[i].size = remain;
3330 }
3331
3332 /* Set vector physical address and length. */
3333 paddr = QWZ_DMA_DVA(vec_adm);
3334 qwz_pci_write(sc, psc->bhie_off + MHI_BHIE_RXVECADDR_HIGH_OFFS,
3335 paddr >> 32);
3336 qwz_pci_write(sc, psc->bhie_off + MHI_BHIE_RXVECADDR_LOW_OFFS,
3337 paddr & 0xffffffff);
3338 qwz_pci_write(sc, psc->bhie_off + MHI_BHIE_RXVECSIZE_OFFS, vec_size);
3339
3340 /* Set a random transaction sequence number. */
3341 do {
3342 seq = arc4random_uniform(MHI_BHIE_RXVECSTATUS_SEQNUM_BMSK);
3343 } while (seq == 0);
3344
3345 reg = qwz_pci_read(sc, psc->bhie_off + MHI_BHIE_RXVECDB_OFFS);
3346 reg &= ~MHI_BHIE_RXVECDB_SEQNUM_BMSK;
3347 reg |= seq << MHI_BHIE_RXVECDB_SEQNUM_SHFT;
3348 qwz_pci_write(sc, psc->bhie_off + MHI_BHIE_RXVECDB_OFFS, reg);
3349
3350 psc->rddm_data = data_adm;
3351 psc->rddm_vec = vec_adm;
3352 }
3353
3354 #ifdef QWZ_DEBUG
3355 void
qwz_rddm_task(void * arg)3356 qwz_rddm_task(void *arg)
3357 {
3358 struct qwz_pci_softc *psc = arg;
3359 struct qwz_softc *sc = &psc->sc_sc;
3360 uint32_t reg, state = MHI_BHIE_RXVECSTATUS_STATUS_RESET;
3361 const size_t len = QWZ_RDDM_DUMP_SIZE;
3362 int i, timeout;
3363 const uint32_t msecs = 100, retries = 20;
3364 uint8_t *rddm;
3365 struct nameidata nd;
3366 struct vnode *vp = NULL;
3367 struct iovec iov[3];
3368 struct uio uio;
3369 char path[PATH_MAX];
3370 int error = 0;
3371
3372 if (psc->rddm_data == NULL) {
3373 DPRINTF("%s: RDDM not prepared\n", __func__);
3374 return;
3375 }
3376
3377 /* Poll for completion */
3378 timeout = retries;
3379 while (timeout > 0 && state != MHI_BHIE_RXVECSTATUS_STATUS_XFER_COMPL) {
3380 reg = qwz_pci_read(sc,
3381 psc->bhie_off + MHI_BHIE_RXVECSTATUS_OFFS);
3382 state = (reg & MHI_BHIE_RXVECSTATUS_STATUS_BMSK) >>
3383 MHI_BHIE_RXVECSTATUS_STATUS_SHFT;
3384 DPRINTF("%s: txvec state is 0x%x\n", __func__, state);
3385 DELAY((msecs / retries) * 1000);
3386 timeout--;
3387 }
3388
3389 if (timeout == 0) {
3390 DPRINTF("%s: RDDM dump failed\n", sc->sc_dev.dv_xname);
3391 return;
3392 }
3393
3394 rddm = QWZ_DMA_KVA(psc->rddm_data);
3395 DPRINTF("%s: RDDM snippet:\n", __func__);
3396 for (i = 0; i < MIN(64, len); i++) {
3397 DPRINTF("%s %.2x", i % 16 == 0 ? "\n" : "", rddm[i]);
3398 }
3399 DPRINTF("\n");
3400
3401 DPRINTF("%s: sleeping for 30 seconds to allow userland to boot\n", __func__);
3402 tsleep_nsec(&psc->rddm_data, 0, "qwzrddm", SEC_TO_NSEC(30));
3403
3404 snprintf(path, sizeof(path), "/root/%s-rddm.bin", sc->sc_dev.dv_xname);
3405 DPRINTF("%s: saving RDDM to %s\n", __func__, path);
3406 NDINIT(&nd, 0, 0, UIO_SYSSPACE, path, curproc);
3407 nd.ni_pledge = PLEDGE_CPATH | PLEDGE_WPATH;
3408 nd.ni_unveil = UNVEIL_CREATE | UNVEIL_WRITE;
3409 error = vn_open(&nd, FWRITE | O_CREAT | O_NOFOLLOW | O_TRUNC,
3410 S_IRUSR | S_IWUSR);
3411 if (error) {
3412 DPRINTF("%s: vn_open: error %d\n", __func__, error);
3413 goto done;
3414 }
3415 vp = nd.ni_vp;
3416 VOP_UNLOCK(vp);
3417
3418 iov[0].iov_base = (void *)rddm;
3419 iov[0].iov_len = len;
3420 iov[1].iov_len = 0;
3421 uio.uio_iov = &iov[0];
3422 uio.uio_offset = 0;
3423 uio.uio_segflg = UIO_SYSSPACE;
3424 uio.uio_rw = UIO_WRITE;
3425 uio.uio_resid = len;
3426 uio.uio_iovcnt = 1;
3427 uio.uio_procp = curproc;
3428 error = vget(vp, LK_EXCLUSIVE | LK_RETRY);
3429 if (error) {
3430 DPRINTF("%s: vget: error %d\n", __func__, error);
3431 goto done;
3432 }
3433 error = VOP_WRITE(vp, &uio, IO_UNIT|IO_APPEND, curproc->p_ucred);
3434 vput(vp);
3435 if (error)
3436 DPRINTF("%s: VOP_WRITE: error %d\n", __func__, error);
3437 #if 0
3438 error = vn_close(vp, FWRITE, curproc->p_ucred, curproc);
3439 if (error)
3440 DPRINTF("%s: vn_close: error %d\n", __func__, error);
3441 #endif
3442 done:
3443 qwz_dmamem_free(sc->sc_dmat, psc->rddm_data);
3444 qwz_dmamem_free(sc->sc_dmat, psc->rddm_vec);
3445 psc->rddm_data = NULL;
3446 psc->rddm_vec = NULL;
3447 DPRINTF("%s: done, error %d\n", __func__, error);
3448 }
3449 #endif
3450
3451 void *
qwz_pci_event_ring_get_elem(struct qwz_pci_event_ring * ring,uint64_t rp)3452 qwz_pci_event_ring_get_elem(struct qwz_pci_event_ring *ring, uint64_t rp)
3453 {
3454 uint64_t base = QWZ_DMA_DVA(ring->dmamem), offset;
3455 void *addr = QWZ_DMA_KVA(ring->dmamem);
3456
3457 if (rp < base)
3458 return NULL;
3459
3460 offset = rp - base;
3461 if (offset >= ring->size)
3462 return NULL;
3463
3464 return addr + offset;
3465 }
3466
3467 void
qwz_mhi_state_change(struct qwz_pci_softc * psc,int ee,int mhi_state)3468 qwz_mhi_state_change(struct qwz_pci_softc *psc, int ee, int mhi_state)
3469 {
3470 struct qwz_softc *sc = &psc->sc_sc;
3471 uint32_t old_ee = psc->bhi_ee;
3472 uint32_t old_mhi_state = psc->mhi_state;
3473
3474 if (ee != -1 && psc->bhi_ee != ee) {
3475 switch (ee) {
3476 case MHI_EE_PBL:
3477 DNPRINTF(QWZ_D_MHI, "%s: new EE PBL\n",
3478 sc->sc_dev.dv_xname);
3479 psc->bhi_ee = ee;
3480 break;
3481 case MHI_EE_SBL:
3482 psc->bhi_ee = ee;
3483 DNPRINTF(QWZ_D_MHI, "%s: new EE SBL\n",
3484 sc->sc_dev.dv_xname);
3485 break;
3486 case MHI_EE_AMSS:
3487 DNPRINTF(QWZ_D_MHI, "%s: new EE AMSS\n",
3488 sc->sc_dev.dv_xname);
3489 psc->bhi_ee = ee;
3490 /* Wake thread loading the full AMSS image. */
3491 wakeup(&psc->bhie_off);
3492 break;
3493 case MHI_EE_WFW:
3494 DNPRINTF(QWZ_D_MHI, "%s: new EE WFW\n",
3495 sc->sc_dev.dv_xname);
3496 psc->bhi_ee = ee;
3497 break;
3498 default:
3499 printf("%s: unhandled EE change to %x\n",
3500 sc->sc_dev.dv_xname, ee);
3501 break;
3502 }
3503 }
3504
3505 if (mhi_state != -1 && psc->mhi_state != mhi_state) {
3506 switch (mhi_state) {
3507 case -1:
3508 break;
3509 case MHI_STATE_RESET:
3510 DNPRINTF(QWZ_D_MHI, "%s: new MHI state RESET\n",
3511 sc->sc_dev.dv_xname);
3512 psc->mhi_state = mhi_state;
3513 break;
3514 case MHI_STATE_READY:
3515 DNPRINTF(QWZ_D_MHI, "%s: new MHI state READY\n",
3516 sc->sc_dev.dv_xname);
3517 psc->mhi_state = mhi_state;
3518 qwz_mhi_ready_state_transition(psc);
3519 break;
3520 case MHI_STATE_M0:
3521 DNPRINTF(QWZ_D_MHI, "%s: new MHI state M0\n",
3522 sc->sc_dev.dv_xname);
3523 psc->mhi_state = mhi_state;
3524 qwz_mhi_mission_mode_state_transition(psc);
3525 break;
3526 case MHI_STATE_M1:
3527 DNPRINTF(QWZ_D_MHI, "%s: new MHI state M1\n",
3528 sc->sc_dev.dv_xname);
3529 psc->mhi_state = mhi_state;
3530 qwz_mhi_low_power_mode_state_transition(psc);
3531 break;
3532 case MHI_STATE_SYS_ERR:
3533 DNPRINTF(QWZ_D_MHI,
3534 "%s: new MHI state SYS ERR\n",
3535 sc->sc_dev.dv_xname);
3536 psc->mhi_state = mhi_state;
3537 break;
3538 default:
3539 printf("%s: unhandled MHI state change to %x\n",
3540 sc->sc_dev.dv_xname, mhi_state);
3541 break;
3542 }
3543 }
3544
3545 if (old_ee != psc->bhi_ee)
3546 wakeup(&psc->bhi_ee);
3547 if (old_mhi_state != psc->mhi_state)
3548 wakeup(&psc->mhi_state);
3549 }
3550
3551 void
qwz_pci_intr_ctrl_event_mhi(struct qwz_pci_softc * psc,uint32_t mhi_state)3552 qwz_pci_intr_ctrl_event_mhi(struct qwz_pci_softc *psc, uint32_t mhi_state)
3553 {
3554 DNPRINTF(QWZ_D_MHI, "%s: MHI state change 0x%x -> 0x%x\n", __func__,
3555 psc->mhi_state, mhi_state);
3556
3557 if (psc->mhi_state != mhi_state)
3558 qwz_mhi_state_change(psc, -1, mhi_state);
3559 }
3560
3561 void
qwz_pci_intr_ctrl_event_ee(struct qwz_pci_softc * psc,uint32_t ee)3562 qwz_pci_intr_ctrl_event_ee(struct qwz_pci_softc *psc, uint32_t ee)
3563 {
3564 DNPRINTF(QWZ_D_MHI, "%s: EE change 0x%x to 0x%x\n", __func__,
3565 psc->bhi_ee, ee);
3566
3567 if (psc->bhi_ee != ee)
3568 qwz_mhi_state_change(psc, ee, -1);
3569 }
3570
3571 void
qwz_pci_intr_ctrl_event_cmd_complete(struct qwz_pci_softc * psc,uint64_t ptr,uint32_t cmd_status)3572 qwz_pci_intr_ctrl_event_cmd_complete(struct qwz_pci_softc *psc,
3573 uint64_t ptr, uint32_t cmd_status)
3574 {
3575 struct qwz_pci_cmd_ring *cmd_ring = &psc->cmd_ring;
3576 uint64_t base = QWZ_DMA_DVA(cmd_ring->dmamem);
3577 struct qwz_pci_xfer_ring *xfer_ring = NULL;
3578 struct qwz_mhi_ring_element *e;
3579 uint32_t tre1, chid;
3580 size_t i;
3581
3582 e = qwz_pci_cmd_ring_get_elem(cmd_ring, ptr);
3583 if (e == NULL)
3584 return;
3585
3586 tre1 = le32toh(e->dword[1]);
3587 chid = (tre1 & MHI_TRE1_EV_CHID_MASK) >> MHI_TRE1_EV_CHID_SHFT;
3588
3589 for (i = 0; i < nitems(psc->xfer_rings); i++) {
3590 if (psc->xfer_rings[i].mhi_chan_id == chid) {
3591 xfer_ring = &psc->xfer_rings[i];
3592 break;
3593 }
3594 }
3595 if (xfer_ring == NULL) {
3596 printf("%s: no transfer ring found for command completion "
3597 "on channel %u\n", __func__, chid);
3598 return;
3599 }
3600
3601 xfer_ring->cmd_status = cmd_status;
3602 wakeup(&xfer_ring->cmd_status);
3603
3604 if (cmd_ring->rp + sizeof(*e) >= base + cmd_ring->size)
3605 cmd_ring->rp = base;
3606 else
3607 cmd_ring->rp += sizeof(*e);
3608 }
3609
3610 int
qwz_pci_intr_ctrl_event(struct qwz_pci_softc * psc,struct qwz_pci_event_ring * ring)3611 qwz_pci_intr_ctrl_event(struct qwz_pci_softc *psc, struct qwz_pci_event_ring *ring)
3612 {
3613 struct qwz_softc *sc = &psc->sc_sc;
3614 struct qwz_mhi_event_ctxt *c;
3615 uint64_t rp, wp, base;
3616 struct qwz_mhi_ring_element *e;
3617 uint32_t tre0, tre1, type, code, chid, len;
3618
3619 c = ring->event_ctxt;
3620 if (c == NULL) {
3621 /*
3622 * Interrupts can trigger before mhi_init_event_rings()
3623 * if the device is still active after a warm reboot.
3624 */
3625 return 0;
3626 }
3627
3628 bus_dmamap_sync(sc->sc_dmat, QWZ_DMA_MAP(psc->event_ctxt), 0,
3629 QWZ_DMA_LEN(psc->event_ctxt), BUS_DMASYNC_POSTREAD);
3630
3631 rp = le64toh(c->rp);
3632 wp = le64toh(c->wp);
3633
3634 DNPRINTF(QWZ_D_MHI, "%s: kernel rp=0x%llx\n", __func__, ring->rp);
3635 DNPRINTF(QWZ_D_MHI, "%s: device rp=0x%llx\n", __func__, rp);
3636 DNPRINTF(QWZ_D_MHI, "%s: kernel wp=0x%llx\n", __func__, ring->wp);
3637 DNPRINTF(QWZ_D_MHI, "%s: device wp=0x%llx\n", __func__, wp);
3638
3639 base = QWZ_DMA_DVA(ring->dmamem);
3640 if (ring->rp == rp || rp < base || rp >= base + ring->size)
3641 return 0;
3642 if (wp < base || wp >= base + ring->size)
3643 return 0;
3644
3645 bus_dmamap_sync(sc->sc_dmat, QWZ_DMA_MAP(ring->dmamem),
3646 0, QWZ_DMA_LEN(ring->dmamem), BUS_DMASYNC_POSTREAD);
3647
3648 while (ring->rp != rp) {
3649 e = qwz_pci_event_ring_get_elem(ring, ring->rp);
3650 if (e == NULL)
3651 return 0;
3652
3653 tre0 = le32toh(e->dword[0]);
3654 tre1 = le32toh(e->dword[1]);
3655
3656 len = (tre0 & MHI_TRE0_EV_LEN_MASK) >> MHI_TRE0_EV_LEN_SHFT;
3657 code = (tre0 & MHI_TRE0_EV_CODE_MASK) >> MHI_TRE0_EV_CODE_SHFT;
3658 type = (tre1 & MHI_TRE1_EV_TYPE_MASK) >> MHI_TRE1_EV_TYPE_SHFT;
3659 chid = (tre1 & MHI_TRE1_EV_CHID_MASK) >> MHI_TRE1_EV_CHID_SHFT;
3660 DNPRINTF(QWZ_D_MHI, "%s: len=%u code=0x%x type=0x%x chid=%d\n",
3661 __func__, len, code, type, chid);
3662
3663 switch (type) {
3664 case MHI_PKT_TYPE_STATE_CHANGE_EVENT:
3665 qwz_pci_intr_ctrl_event_mhi(psc, code);
3666 break;
3667 case MHI_PKT_TYPE_EE_EVENT:
3668 qwz_pci_intr_ctrl_event_ee(psc, code);
3669 break;
3670 case MHI_PKT_TYPE_CMD_COMPLETION_EVENT:
3671 qwz_pci_intr_ctrl_event_cmd_complete(psc,
3672 le64toh(e->ptr), code);
3673 break;
3674 default:
3675 printf("%s: unhandled event type 0x%x\n",
3676 __func__, type);
3677 break;
3678 }
3679
3680 if (ring->rp + sizeof(*e) >= base + ring->size)
3681 ring->rp = base;
3682 else
3683 ring->rp += sizeof(*e);
3684
3685 if (ring->wp + sizeof(*e) >= base + ring->size)
3686 ring->wp = base;
3687 else
3688 ring->wp += sizeof(*e);
3689 }
3690
3691 c->wp = htole64(ring->wp);
3692
3693 bus_dmamap_sync(sc->sc_dmat, QWZ_DMA_MAP(psc->event_ctxt), 0,
3694 QWZ_DMA_LEN(psc->event_ctxt), BUS_DMASYNC_PREWRITE);
3695
3696 qwz_mhi_ring_doorbell(sc, ring->db_addr, ring->wp);
3697 return 1;
3698 }
3699
3700 void
qwz_pci_intr_data_event_tx(struct qwz_pci_softc * psc,struct qwz_mhi_ring_element * e)3701 qwz_pci_intr_data_event_tx(struct qwz_pci_softc *psc, struct qwz_mhi_ring_element *e)
3702 {
3703 struct qwz_softc *sc = &psc->sc_sc;
3704 struct qwz_pci_xfer_ring *ring;
3705 struct qwz_xfer_data *xfer;
3706 uint64_t rp, evrp, base, paddr;
3707 uint32_t tre0, tre1, code, chid, evlen, len;
3708 int i;
3709
3710 tre0 = le32toh(e->dword[0]);
3711 tre1 = le32toh(e->dword[1]);
3712
3713 evlen = (tre0 & MHI_TRE0_EV_LEN_MASK) >> MHI_TRE0_EV_LEN_SHFT;
3714 code = (tre0 & MHI_TRE0_EV_CODE_MASK) >> MHI_TRE0_EV_CODE_SHFT;
3715 chid = (tre1 & MHI_TRE1_EV_CHID_MASK) >> MHI_TRE1_EV_CHID_SHFT;
3716
3717 switch (code) {
3718 case MHI_EV_CC_EOT:
3719 for (i = 0; i < nitems(psc->xfer_rings); i++) {
3720 ring = &psc->xfer_rings[i];
3721 if (ring->mhi_chan_id == chid)
3722 break;
3723 }
3724 if (i == nitems(psc->xfer_rings)) {
3725 printf("%s: unhandled channel 0x%x\n",
3726 __func__, chid);
3727 break;
3728 }
3729 base = QWZ_DMA_DVA(ring->dmamem);
3730 /* PTR contains the entry that was last written */
3731 evrp = letoh64(e->ptr);
3732 rp = evrp;
3733 if (rp < base || rp >= base + ring->size) {
3734 printf("%s: invalid ptr 0x%llx\n",
3735 __func__, rp);
3736 break;
3737 }
3738 /* Point rp to next empty slot */
3739 if (rp + sizeof(*e) >= base + ring->size)
3740 rp = base;
3741 else
3742 rp += sizeof(*e);
3743 /* Parse until next empty slot */
3744 while (ring->rp != rp) {
3745 DNPRINTF(QWZ_D_MHI, "%s:%d: ring->rp 0x%llx "
3746 "ring->wp 0x%llx rp 0x%llx\n", __func__,
3747 __LINE__, ring->rp, ring->wp, rp);
3748 e = qwz_pci_xfer_ring_get_elem(ring, ring->rp);
3749 xfer = qwz_pci_xfer_ring_get_data(ring, ring->rp);
3750
3751 if (ring->rp == evrp)
3752 len = evlen;
3753 else
3754 len = xfer->m->m_pkthdr.len;
3755
3756 bus_dmamap_sync(sc->sc_dmat, xfer->map, 0,
3757 xfer->m->m_pkthdr.len, BUS_DMASYNC_POSTREAD);
3758 #ifdef QWZ_DEBUG
3759 {
3760 int i;
3761 DNPRINTF(QWZ_D_MHI, "%s: chan %u data (len %u): ",
3762 __func__,
3763 ring->mhi_chan_id, len);
3764 for (i = 0; i < MIN(32, len); i++) {
3765 DNPRINTF(QWZ_D_MHI, "%02x ",
3766 (unsigned char)mtod(xfer->m, caddr_t)[i]);
3767 }
3768 if (i < len)
3769 DNPRINTF(QWZ_D_MHI, "...");
3770 DNPRINTF(QWZ_D_MHI, "\n");
3771 }
3772 #endif
3773 if (ring->mhi_chan_direction == MHI_CHAN_TYPE_INBOUND) {
3774 /* Save m_data as upper layers use m_adj(9) */
3775 void *o_data = xfer->m->m_data;
3776
3777 /* Pass mbuf to upper layers */
3778 qwz_qrtr_recv_msg(sc, xfer->m);
3779
3780 /* Reset RX mbuf instead of free/alloc */
3781 KASSERT(xfer->m->m_next == NULL);
3782 xfer->m->m_data = o_data;
3783 xfer->m->m_len = xfer->m->m_pkthdr.len =
3784 QWZ_PCI_XFER_MAX_DATA_SIZE;
3785
3786 paddr = xfer->map->dm_segs[0].ds_addr;
3787
3788 e->ptr = htole64(paddr);
3789 e->dword[0] = htole32((
3790 QWZ_PCI_XFER_MAX_DATA_SIZE <<
3791 MHI_TRE0_DATA_LEN_SHFT) &
3792 MHI_TRE0_DATA_LEN_MASK);
3793 e->dword[1] = htole32(MHI_TRE1_DATA_IEOT |
3794 MHI_TRE1_DATA_BEI |
3795 MHI_TRE1_DATA_TYPE_TRANSFER <<
3796 MHI_TRE1_DATA_TYPE_SHIFT);
3797
3798 if (ring->wp + sizeof(*e) >= base + ring->size)
3799 ring->wp = base;
3800 else
3801 ring->wp += sizeof(*e);
3802 } else {
3803 /* Unload and free TX mbuf */
3804 bus_dmamap_unload(sc->sc_dmat, xfer->map);
3805 m_freem(xfer->m);
3806 xfer->m = NULL;
3807 ring->queued--;
3808 }
3809
3810 if (ring->rp + sizeof(*e) >= base + ring->size)
3811 ring->rp = base;
3812 else
3813 ring->rp += sizeof(*e);
3814 }
3815
3816 if (ring->mhi_chan_direction == MHI_CHAN_TYPE_INBOUND) {
3817 ring->chan_ctxt->wp = htole64(ring->wp);
3818
3819 bus_dmamap_sync(sc->sc_dmat,
3820 QWZ_DMA_MAP(psc->chan_ctxt), 0,
3821 QWZ_DMA_LEN(psc->chan_ctxt),
3822 BUS_DMASYNC_PREWRITE);
3823
3824 qwz_mhi_ring_doorbell(sc, ring->db_addr, ring->wp);
3825 }
3826 break;
3827 default:
3828 printf("%s: unhandled event code 0x%x\n",
3829 __func__, code);
3830 }
3831 }
3832
3833 int
qwz_pci_intr_data_event(struct qwz_pci_softc * psc,struct qwz_pci_event_ring * ring)3834 qwz_pci_intr_data_event(struct qwz_pci_softc *psc, struct qwz_pci_event_ring *ring)
3835 {
3836 struct qwz_softc *sc = &psc->sc_sc;
3837 struct qwz_mhi_event_ctxt *c;
3838 uint64_t rp, wp, base;
3839 struct qwz_mhi_ring_element *e;
3840 uint32_t tre0, tre1, type, code, chid, len;
3841
3842 c = ring->event_ctxt;
3843 if (c == NULL) {
3844 /*
3845 * Interrupts can trigger before mhi_init_event_rings()
3846 * if the device is still active after a warm reboot.
3847 */
3848 return 0;
3849 }
3850
3851 bus_dmamap_sync(sc->sc_dmat, QWZ_DMA_MAP(psc->event_ctxt), 0,
3852 QWZ_DMA_LEN(psc->event_ctxt), BUS_DMASYNC_POSTREAD);
3853
3854 rp = le64toh(c->rp);
3855 wp = le64toh(c->wp);
3856
3857 DNPRINTF(QWZ_D_MHI, "%s: kernel rp=0x%llx\n", __func__, ring->rp);
3858 DNPRINTF(QWZ_D_MHI, "%s: device rp=0x%llx\n", __func__, rp);
3859 DNPRINTF(QWZ_D_MHI, "%s: kernel wp=0x%llx\n", __func__, ring->wp);
3860 DNPRINTF(QWZ_D_MHI, "%s: device wp=0x%llx\n", __func__, wp);
3861
3862 base = QWZ_DMA_DVA(ring->dmamem);
3863 if (ring->rp == rp || rp < base || rp >= base + ring->size)
3864 return 0;
3865
3866 bus_dmamap_sync(sc->sc_dmat, QWZ_DMA_MAP(ring->dmamem),
3867 0, QWZ_DMA_LEN(ring->dmamem), BUS_DMASYNC_POSTREAD);
3868
3869 while (ring->rp != rp) {
3870 e = qwz_pci_event_ring_get_elem(ring, ring->rp);
3871 if (e == NULL)
3872 return 0;
3873
3874 tre0 = le32toh(e->dword[0]);
3875 tre1 = le32toh(e->dword[1]);
3876
3877 len = (tre0 & MHI_TRE0_EV_LEN_MASK) >> MHI_TRE0_EV_LEN_SHFT;
3878 code = (tre0 & MHI_TRE0_EV_CODE_MASK) >> MHI_TRE0_EV_CODE_SHFT;
3879 type = (tre1 & MHI_TRE1_EV_TYPE_MASK) >> MHI_TRE1_EV_TYPE_SHFT;
3880 chid = (tre1 & MHI_TRE1_EV_CHID_MASK) >> MHI_TRE1_EV_CHID_SHFT;
3881 DNPRINTF(QWZ_D_MHI, "%s: len=%u code=0x%x type=0x%x chid=%d\n",
3882 __func__, len, code, type, chid);
3883
3884 switch (type) {
3885 case MHI_PKT_TYPE_TX_EVENT:
3886 qwz_pci_intr_data_event_tx(psc, e);
3887 break;
3888 default:
3889 printf("%s: unhandled event type 0x%x\n",
3890 __func__, type);
3891 break;
3892 }
3893
3894 if (ring->rp + sizeof(*e) >= base + ring->size)
3895 ring->rp = base;
3896 else
3897 ring->rp += sizeof(*e);
3898
3899 if (ring->wp + sizeof(*e) >= base + ring->size)
3900 ring->wp = base;
3901 else
3902 ring->wp += sizeof(*e);
3903 }
3904
3905 c->wp = htole64(ring->wp);
3906
3907 bus_dmamap_sync(sc->sc_dmat, QWZ_DMA_MAP(psc->event_ctxt), 0,
3908 QWZ_DMA_LEN(psc->event_ctxt), BUS_DMASYNC_PREWRITE);
3909
3910 qwz_mhi_ring_doorbell(sc, ring->db_addr, ring->wp);
3911 return 1;
3912 }
3913
3914 int
qwz_pci_intr_mhi_ctrl(void * arg)3915 qwz_pci_intr_mhi_ctrl(void *arg)
3916 {
3917 struct qwz_pci_softc *psc = arg;
3918
3919 if (qwz_pci_intr_ctrl_event(psc, &psc->event_rings[0]))
3920 return 1;
3921
3922 return 0;
3923 }
3924
3925 int
qwz_pci_intr_mhi_data(void * arg)3926 qwz_pci_intr_mhi_data(void *arg)
3927 {
3928 struct qwz_pci_softc *psc = arg;
3929
3930 if (qwz_pci_intr_data_event(psc, &psc->event_rings[1]))
3931 return 1;
3932
3933 return 0;
3934 }
3935
3936 int
qwz_pci_intr(void * arg)3937 qwz_pci_intr(void *arg)
3938 {
3939 struct qwz_pci_softc *psc = arg;
3940 struct qwz_softc *sc = (void *)psc;
3941 uint32_t ee, state;
3942 int ret = 0;
3943
3944 /*
3945 * Interrupts can trigger before mhi_start() during boot if the device
3946 * is still active after a warm reboot.
3947 */
3948 if (psc->bhi_off == 0)
3949 psc->bhi_off = qwz_pci_read(sc, MHI_BHI_OFFSET);
3950
3951 ee = qwz_pci_read(sc, psc->bhi_off + MHI_BHI_EXECENV);
3952 state = qwz_pci_read(sc, MHI_STATUS);
3953 state = (state & MHI_STATUS_MHISTATE_MASK) >>
3954 MHI_STATUS_MHISTATE_SHFT;
3955
3956 DNPRINTF(QWZ_D_MHI,
3957 "%s: BHI interrupt with EE: 0x%x -> 0x%x state: 0x%x -> 0x%x\n",
3958 sc->sc_dev.dv_xname, psc->bhi_ee, ee, psc->mhi_state, state);
3959
3960 if (ee == MHI_EE_RDDM) {
3961 /* Firmware crash, e.g. due to invalid DMA memory access. */
3962 psc->bhi_ee = ee;
3963 #ifdef QWZ_DEBUG
3964 if (!psc->rddm_triggered) {
3965 /* Write fw memory dump to root's home directory. */
3966 task_add(systq, &psc->rddm_task);
3967 psc->rddm_triggered = 1;
3968 }
3969 #else
3970 printf("%s: fatal firmware error\n",
3971 sc->sc_dev.dv_xname);
3972 if (!test_bit(ATH12K_FLAG_CRASH_FLUSH, sc->sc_flags) &&
3973 (sc->sc_ic.ic_if.if_flags & (IFF_UP | IFF_RUNNING)) ==
3974 (IFF_UP | IFF_RUNNING)) {
3975 /* Try to reset the device. */
3976 set_bit(ATH12K_FLAG_CRASH_FLUSH, sc->sc_flags);
3977 task_add(systq, &sc->init_task);
3978 }
3979 #endif
3980 return 1;
3981 } else if (psc->bhi_ee == MHI_EE_PBL || psc->bhi_ee == MHI_EE_SBL) {
3982 int new_ee = -1, new_mhi_state = -1;
3983
3984 if (psc->bhi_ee != ee)
3985 new_ee = ee;
3986
3987 if (psc->mhi_state != state)
3988 new_mhi_state = state;
3989
3990 if (new_ee != -1 || new_mhi_state != -1)
3991 qwz_mhi_state_change(psc, new_ee, new_mhi_state);
3992
3993 ret = 1;
3994 }
3995
3996 if (!test_bit(ATH12K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags)) {
3997 int i;
3998
3999 if (qwz_pci_intr_ctrl_event(psc, &psc->event_rings[0]))
4000 ret = 1;
4001 if (qwz_pci_intr_data_event(psc, &psc->event_rings[1]))
4002 ret = 1;
4003
4004 for (i = 0; i < sc->hw_params.ce_count; i++) {
4005 struct qwz_ce_pipe *ce_pipe = &sc->ce.ce_pipe[i];
4006
4007 if (qwz_ce_intr(ce_pipe))
4008 ret = 1;
4009 }
4010
4011 if (test_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, sc->sc_flags)) {
4012 for (i = 0; i < nitems(sc->ext_irq_grp); i++) {
4013 if (qwz_dp_service_srng(sc, i))
4014 ret = 1;
4015 }
4016 }
4017 }
4018
4019 return ret;
4020 }
4021