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Searched refs:AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK (Results 1 – 17 of 17) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dce/
H A Ddce_10_0_sh_mask.h13343 #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff macro
H A Ddce_11_0_sh_mask.h13349 #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff macro
H A Ddce_11_2_sh_mask.h13965 #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff macro
H A Ddce_12_0_sh_mask.h64371 #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h28138 #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK … macro
H A Ddcn_1_0_sh_mask.h47149 #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK … macro
H A Ddcn_2_1_0_sh_mask.h49443 #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK … macro
H A Ddcn_3_0_1_sh_mask.h46164 #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK … macro
H A Ddcn_3_2_1_sh_mask.h49385 #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK … macro
H A Ddcn_3_1_2_sh_mask.h53566 #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK … macro
H A Ddcn_3_1_5_sh_mask.h54537 #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK … macro
H A Ddcn_3_1_4_sh_mask.h544 #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK … macro
H A Ddcn_3_1_6_sh_mask.h55384 #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK … macro
H A Ddcn_3_0_2_sh_mask.h55185 #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK … macro
H A Ddcn_2_0_0_sh_mask.h60836 #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK … macro
H A Ddcn_3_0_0_sh_mask.h63763 #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK … macro
H A Ddcn_3_2_0_sh_mask.h49387 #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK … macro