/openbsd/gnu/llvm/llvm/lib/Target/X86/ |
H A D | X86InsertPrefetch.cpp | 84 Register IndexReg = MI.getOperand(Op + X86::AddrIndexReg).getReg(); in IsMemOpCompatibleWithPrefetch() 219 X86::AddrIndexReg == 2 && X86::AddrDisp == 3 && in runOnMachineFunction() 230 Current->getOperand(MemOpOffset + X86::AddrIndexReg).getReg()) in runOnMachineFunction()
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H A D | X86FixupLEAs.cpp | 463 Register IndexReg = LeaI->getOperand(1 + X86::AddrIndexReg).getReg(); in checkRegUsage() 515 Register IndexReg = I->getOperand(1 + X86::AddrIndexReg).getReg(); in optLEAALU() 563 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg); in optTwoAddrLEA() 668 MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg); in processInstruction() 703 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg); in processInstructionForSlowLEA() 755 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg); in processInstrForSlow3OpLEA()
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H A D | X86AsmPrinter.cpp | 376 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintLeaMemReference() 416 PrintModifiedOperand(MI, OpNo + X86::AddrIndexReg, O, Modifier); in PrintLeaMemReference() 473 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintIntelMemReference() 507 PrintOperand(MI, OpNo + X86::AddrIndexReg, O); in PrintIntelMemReference()
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H A D | X86OptimizeLEAs.cpp | 196 &MI.getOperand(N + X86::AddrIndexReg), in getMemOpKey() 561 MI.getOperand(MemOpNo + X86::AddrIndexReg) in removeRedundantAddrCalc()
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H A D | X86FixupGadgets.cpp | 160 const MachineOperand &Index = MI.getOperand(CurOp + X86::AddrIndexReg); in checkSIB() 170 info.op2 = CurOp + X86::AddrIndexReg; in checkSIB()
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H A D | X86CallFrameOptimization.cpp | 431 (I->getOperand(X86::AddrIndexReg).getReg() != X86::NoRegister) || in collectCallInfo()
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H A D | X86SpeculativeLoadHardening.cpp | 1339 MI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in tracePredStateThroughBlocksAndHarden() 1413 MI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in tracePredStateThroughBlocksAndHarden() 1815 UseMI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in sinkPostLoadHardenedInst()
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H A D | X86InstrInfo.h | 124 MI.getOperand(Op + X86::AddrIndexReg).isReg() && in isLeaMem()
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H A D | X86AvoidStoreForwardingBlocks.cpp | 317 const MachineOperand &Index = MI->getOperand(AddrOffset + X86::AddrIndexReg); in isRelevantAddressingMode()
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H A D | X86LoadValueInjectionLoadHardening.cpp | 788 MI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in instrUsesRegToAccessMemory()
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H A D | X86InstrInfo.cpp | 457 MI.getOperand(Op + X86::AddrIndexReg).isReg() && in isFrameOperand() 460 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 && in isFrameOperand() 870 MI.getOperand(1 + X86::AddrIndexReg).isReg() && in isReallyTriviallyReMaterializable() 871 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 && in isReallyTriviallyReMaterializable() 889 MI.getOperand(1 + X86::AddrIndexReg).isReg() && in isReallyTriviallyReMaterializable() 890 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 && in isReallyTriviallyReMaterializable() 3752 AM.ScaledReg = MemI.getOperand(MemRefBegin + X86::AddrIndexReg).getReg(); in getAddrModeFromMemoryOp() 3846 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() != in getMemOperandsWithOffsetWidth() 3909 MachineOperand &MO = NewMI->getOperand(X86::AddrIndexReg); in loadStoreTileReg() 3921 MachineOperand &MO = NewMI->getOperand(1 + X86::AddrIndexReg); in loadStoreTileReg() [all …]
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H A D | X86MCInstLower.cpp | 390 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && in SimplifyShortMoveForm() 414 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0)) in SimplifyShortMoveForm()
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H A D | X86FastISel.cpp | 219 X86::AddrIndexReg); in addFullAddress()
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/openbsd/gnu/llvm/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCCodeEmitter.cpp | 330 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in emitMemModRMByte() 809 getX86RegEncoding(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix() 835 getX86RegEncoding(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix() 882 getX86RegEncoding(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix() 898 getX86RegEncoding(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix() 915 getX86RegEncoding(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix() 942 getX86RegEncoding(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix() 1192 REX |= isREXExtendedReg(MI, MemOperand + X86::AddrIndexReg) << 1; // REX.X in emitREXPrefix() 1201 REX |= isREXExtendedReg(MI, MemOperand + X86::AddrIndexReg) << 1; // REX.X in emitREXPrefix() 1216 REX |= isREXExtendedReg(MI, MemOperand + X86::AddrIndexReg) << 1; // REX.X in emitREXPrefix()
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H A D | X86MCTargetDesc.cpp | 79 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in isMemOperand() 89 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in is16BitMemOperand() 99 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in is32BitMemOperand() 651 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); in evaluateMemoryOperandAddress() 677 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); in getMemoryOperandRelocationOffset()
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H A D | X86ATTInstPrinter.cpp | 427 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference() 451 printOperand(MI, Op + X86::AddrIndexReg, O); in printMemReference()
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H A D | X86IntelInstPrinter.cpp | 385 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printMemReference() 403 printOperand(MI, Op+X86::AddrIndexReg, O); in printMemReference()
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H A D | X86BaseInfo.h | 34 AddrIndexReg = 2, enumerator
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/openbsd/gnu/llvm/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 3885 Inst.getOperand(4 + X86::AddrIndexReg).getReg()); in validateInstruction() 3893 Inst.getOperand(3 + X86::AddrIndexReg).getReg()); in validateInstruction()
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