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Searched refs:BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT (Results 1 – 5 of 5) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_1_sh_mask.h2435 #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/bif/
H A Dbif_5_0_sh_mask.h670 #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e macro
H A Dbif_5_1_sh_mask.h638 #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_sh_mask.h117987 #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT … macro
H A Dnbio_6_1_sh_mask.h17711 #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT … macro