1 /* $OpenBSD: bonitoreg.h,v 1.8 2016/11/05 05:28:39 visa Exp $ */ 2 /* $NetBSD: bonitoreg.h,v 1.6 2005/12/24 20:07:19 perry Exp $ */ 3 4 /* 5 * The Loongson PCI Northbridge and memory controller is a derivative 6 * of the Bonito chip. 7 * 8 * This file is a stripped-down version of the Bonito layout, containing 9 * only definitions applying to the Loongson chip. 10 */ 11 12 /* 13 * Bonito Register Map 14 * Copyright (c) 1999 Algorithmics Ltd 15 * 16 * Algorithmics gives permission for anyone to use and modify this file 17 * without any obligation or license condition except that you retain 18 * this copyright message in any source redistribution in whole or part. 19 * 20 * Updated copies of this and other files can be found at 21 * ftp://ftp.algor.co.uk/pub/bonito/ 22 * 23 * Users of the Bonito controller are warmly recommended to contribute 24 * any useful changes back to Algorithmics (mail to 25 * bonito@algor.co.uk). 26 */ 27 28 /* Revision 1.48 autogenerated on 08/17/99 15:20:01 */ 29 30 #ifndef _BONITOREG_H_ 31 #define _BONITOREG_H_ 32 33 #define BONITO(x) (BONITO_REG_BASE + (x)) 34 35 #define BONITO_FLASH_BASE 0x1c000000UL 36 #define BONITO_FLASH_SIZE 0x02000000UL 37 #define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1) 38 39 #define BONITO_BOOT_BASE 0x1fc00000UL 40 #define BONITO_BOOT_SIZE 0x00100000UL 41 #define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) 42 #define BONITO_REG_BASE 0x1fe00000UL 43 #define BONITO_REG_SIZE 0x00040000UL 44 #define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1) 45 46 #define BONITO_PCILO_BASE 0x10000000UL 47 #define BONITO_PCILO_SIZE 0x0c000000UL 48 #define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1) 49 #define BONITO_PCILO0_BASE 0x10000000UL 50 #define BONITO_PCILO1_BASE 0x14000000UL 51 #define BONITO_PCILO2_BASE 0x18000000UL 52 #define BONITO_PCIHI_BASE 0x20000000UL 53 #define BONITO_PCIHI_SIZE 0x60000000UL 54 #define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1) 55 #define LS2F_PCIHI_BASE 0x40000000UL 56 #define LS2F_PCIHI_SIZE 0x40000000UL 57 #define LS2F_PCIHI_TOP (LS2F_PCIHI_BASE+LS2F_PCIHI_SIZE-1) 58 #define BONITO_PCIIO_BASE 0x1fd00000UL 59 #define BONITO_PCIIO_LEGACY 0x00004000UL 60 #define BONITO_PCIIO_SIZE 0x00100000UL 61 #define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1) 62 #define BONITO_PCICFG_BASE 0x1fe80000UL 63 #define BONITO_PCICFG_SIZE 0x00080000UL 64 #define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1) 65 66 /* Bonito Register Bases */ 67 68 #define BONITO_PCICONFIGBASE 0x00 69 #define BONITO_REGBASE 0x100 70 71 /* PCI Configuration Registers */ 72 73 #define BONITO_PCI_REG(x) BONITO(BONITO_PCICONFIGBASE + (x)) 74 75 #define BONITO_REV_FPGA(x) ((x) & 0x80) 76 #define BONITO_REV_MAJOR(x) (((x) >> 4) & 0x7) 77 #define BONITO_REV_MINOR(x) ((x) & 0xf) 78 79 /* Controller configuration */ 80 81 #define LOONGSON_PONCFG BONITO(BONITO_REGBASE + 0x00) 82 #define LOONGSON_GENCFG BONITO(BONITO_REGBASE + 0x04) 83 #define LOONGSON_LIOCFG BONITO(BONITO_REGBASE + 0x08) 84 85 /* PCI address map control */ 86 87 #define BONITO_PCIMAP BONITO(BONITO_REGBASE + 0x10) 88 #define LOONGSON_PCIX_BRIDGE_CFG BONITO(BONITO_REGBASE + 0x14) 89 #define BONITO_PCIMAP_CFG BONITO(BONITO_REGBASE + 0x18) 90 91 /* GPIO Regs - r/w */ 92 93 #define BONITO_GPIODATA BONITO(BONITO_REGBASE + 0x1c) 94 #define BONITO_GPIOIE BONITO(BONITO_REGBASE + 0x20) 95 96 /* ICU Configuration Regs - r/w */ 97 98 #define BONITO_INTEDGE BONITO(BONITO_REGBASE + 0x24) 99 #define BONITO_INTSTEER BONITO(BONITO_REGBASE + 0x28) 100 #define BONITO_INTPOL BONITO(BONITO_REGBASE + 0x2c) 101 102 /* ICU Enable Regs - INTEN and INTISR are read only */ 103 104 #define BONITO_INTENSET BONITO(BONITO_REGBASE + 0x30) 105 #define BONITO_INTENCLR BONITO(BONITO_REGBASE + 0x34) 106 #define BONITO_INTEN BONITO(BONITO_REGBASE + 0x38) 107 #define BONITO_INTISR BONITO(BONITO_REGBASE + 0x3c) 108 109 /* Memory window */ 110 111 #define BONITO_MEM_WIN_BASE_L BONITO(BONITO_REGBASE + 0x40) 112 #define BONITO_MEM_WIN_BASE_H BONITO(BONITO_REGBASE + 0x44) 113 #define BONITO_MEM_WIN_MASK_L BONITO(BONITO_REGBASE + 0x48) 114 #define BONITO_MEM_WIN_MASK_H BONITO(BONITO_REGBASE + 0x4c) 115 116 /* PCI_Hit*_Sel_* */ 117 118 #define LOONGSON_PCI_HIT0_SEL_L BONITO(BONITO_REGBASE + 0x50) 119 #define LOONGSON_PCI_HIT0_SEL_H BONITO(BONITO_REGBASE + 0x54) 120 #define LOONGSON_PCI_HIT1_SEL_L BONITO(BONITO_REGBASE + 0x58) 121 #define LOONGSON_PCI_HIT1_SEL_H BONITO(BONITO_REGBASE + 0x5c) 122 #define LOONGSON_PCI_HIT2_SEL_L BONITO(BONITO_REGBASE + 0x60) 123 #define LOONGSON_PCI_HIT2_SEL_H BONITO(BONITO_REGBASE + 0x64) 124 125 /* PCIX Arbitration */ 126 127 #define LOONGSON_PXARB_CFG BONITO(BONITO_REGBASE + 0x68) 128 #define LOONGSON_PXARB_STS BONITO(BONITO_REGBASE + 0x6c) 129 130 /* Chip configuration */ 131 132 #define LOONGSON_CHIP_CONFIG0 BONITO(BONITO_REGBASE + 0x80) 133 #define LOONGSON_PAD1V8_CTRL BONITO(BONITO_REGBASE + 0x84) 134 #define LOONGSON_PAD3V3_CTRL BONITO(BONITO_REGBASE + 0x88) 135 136 /* ###### Bit Definitions for individual Registers #### */ 137 138 /* gencfg */ 139 140 #define LOONGSON_GENCFG_OV_EN 0x00000001 /* video accel enable */ 141 142 #define BONITO_GENCFG_CPUSELFRESET 0x00000004 /* reset system */ 143 144 /* pcimap */ 145 146 #define BONITO_PCIMAP_PCIMAP_LO0 0x0000003f 147 #define BONITO_PCIMAP_PCIMAP_LO0_SHIFT 0 148 #define BONITO_PCIMAP_PCIMAP_LO1 0x00000fc0 149 #define BONITO_PCIMAP_PCIMAP_LO1_SHIFT 6 150 #define BONITO_PCIMAP_PCIMAP_LO2 0x0003f000 151 #define BONITO_PCIMAP_PCIMAP_LO2_SHIFT 12 152 #define BONITO_PCIMAP_PCIMAP_2 0x00040000 /* real bonito only */ 153 #define BONITO_PCIMAP_WIN(WIN,ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) 154 #define BONITO_PCIMAP_WINSIZE (1UL<<26) 155 #define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1)) 156 #define BONITO_PCIMAP_WINBASE(ADDR) ((ADDR) << 26) 157 158 /* PCIMAP Cfg */ 159 160 #define BONITO_PCIMAPCFG_TYPE1 0x00010000 161 162 /* PXARB_CFG */ 163 164 #define LOONGSON_PXARB_DEVICE_EN 0x00000001 165 #define LOONGSON_PXARB_DISABLE_BROKEN 0x00000002 166 #define LOONGSON_PXARB_DEFAULT_MAS_EN 0x00000004 167 #define LOONGSON_PXARB_DEFAULT_MAS_MSK 0x00000038 168 #define LOONGSON_PXARB_DEFAULT_MAS_SHFT 3 169 #define LOONGSON_PXARB_PARK_DELAY_MSK 0x000000c0 170 #define LOONGSON_PXARB_PARK_DELAY_SHFT 6 171 #define LOONGSON_PXARB_PARK_DELAY_0 0 172 #define LOONGSON_PXARB_PARK_DELAY_8 1 173 #define LOONGSON_PXARB_PARK_DELAY_32 2 174 #define LOONGSON_PXARB_PARK_DELAY_128 3 175 #define LOONGSON_PXARB_LEVEL_MSK 0x0000ff00 176 #define LOONGSON_PXARB_LEVEL_SHFT 8 177 #define LOONGSON_PXARB_RUDE_DEV_MSK 0x00ff0000 178 #define LOONGSON_PXARB_RUDE_DEV_SHFT 16 179 180 #endif /* _BONITOREG_H_ */ 181