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Searched refs:BT_ADDR (Results 1 – 3 of 3) sorted by relevance

/openbsd/sys/dev/sbus/
H A Dcgthree.c65 #define BT_ADDR 0x00 /* map address register */ macro
385 BT_WRITE(sc, BT_ADDR, BT_D4M4(start)); in cgthree_loadcmap()
466 BT_WRITE(sc, BT_ADDR, BT_RMR); in cgthree_reset()
467 BT_BARRIER(sc, BT_ADDR, BUS_SPACE_BARRIER_WRITE); in cgthree_reset()
472 BT_WRITE(sc, BT_ADDR, BT_BMR); in cgthree_reset()
473 BT_BARRIER(sc, BT_ADDR, BUS_SPACE_BARRIER_WRITE); in cgthree_reset()
481 BT_WRITE(sc, BT_ADDR, BT_CR); in cgthree_reset()
482 BT_BARRIER(sc, BT_ADDR, BUS_SPACE_BARRIER_WRITE); in cgthree_reset()
488 BT_WRITE(sc, BT_ADDR, BT_CTR); in cgthree_reset()
489 BT_BARRIER(sc, BT_ADDR, BUS_SPACE_BARRIER_WRITE); in cgthree_reset()
H A Dcgsix.c446 BT_WRITE(sc, BT_ADDR, BT_OV1 << 24); in cgsix_updatecursor()
454 BT_WRITE(sc, BT_ADDR, BT_OV3 << 24); in cgsix_updatecursor()
477 BT_WRITE(sc, BT_ADDR, BT_CR << 24); in cgsix_updatecursor()
482 BT_WRITE(sc, BT_ADDR, BT_CR << 24); in cgsix_updatecursor()
623 BT_WRITE(sc, BT_ADDR, BT_D4M4(start) << 24); in cgsix_loadcmap_immediate()
674 BT_WRITE(sc, BT_ADDR, BT_CR << 24); in cgsix_reset()
685 BT_WRITE(sc, BT_ADDR, BT_RMR << 24); in cgsix_hardreset()
686 BT_BARRIER(sc, BT_ADDR, BUS_SPACE_BARRIER_WRITE); in cgsix_hardreset()
691 BT_WRITE(sc, BT_ADDR, BT_BMR << 24); in cgsix_hardreset()
700 BT_WRITE(sc, BT_ADDR, BT_CR << 24); in cgsix_hardreset()
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H A Dcgsixreg.h34 #define BT_ADDR 0x00 /* map address register */ macro