| /openbsd/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64StorePairSuppress.cpp | 150 const MachineOperand *BaseOp; in runOnMachineFunction() local
153 if (TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, in runOnMachineFunction()
155 BaseOp->isReg()) { in runOnMachineFunction()
156 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction()
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| H A D | AArch64InstrInfo.h | 149 const MachineOperand *&BaseOp,
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| H A D | AArch64InstrInfo.cpp | 2592 const MachineOperand *BaseOp; in getMemOperandsWithOffsetWidth() local
2593 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, OffsetIsScalable, in getMemOperandsWithOffsetWidth()
2596 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
2620 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
2652 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
2656 BaseOp = &LdSt.getOperand(2); in getMemOperandWithOffsetWidth()
2661 if (!BaseOp->isReg() && !BaseOp->isFI()) in getMemOperandWithOffsetWidth()
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| /openbsd/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMHazardRecognizer.cpp | 109 static bool getBaseOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, in getBaseOffset() argument
129 BaseOp = &MI.getOperand(1); in getBaseOffset()
141 BaseOp = &MI.getOperand(1); in getBaseOffset()
146 BaseOp = &MI.getOperand(2); in getBaseOffset()
160 BaseOp = &MI.getOperand(1); in getBaseOffset()
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| H A D | ARMLoadStoreOptimizer.cpp | 1624 Register Base = BaseOp.getReg(); in MergeBaseUpdateLSDouble()
1659 MIB.addReg(BaseOp.getReg(), RegState::Kill) in MergeBaseUpdateLSDouble()
1770 Register BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp()
1795 bool BaseKill = BaseOp.isKill(); in FixInvalidRegPairOp()
1796 bool BaseUndef = BaseOp.isUndef(); in FixInvalidRegPairOp()
2731 MI->getOperand(BaseOp).setReg(NewBaseReg); in AdjustBaseAndOffset()
2871 int BaseOp = getBaseOperandIndex(Use); in DistributeIncrements() local
2872 if (BaseOp == -1) in DistributeIncrements()
2875 if (!Use.getOperand(BaseOp).isReg() || in DistributeIncrements()
3000 int BaseOp = getBaseOperandIndex(MI); in DistributeIncrements() local
[all …]
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| /openbsd/gnu/llvm/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 754 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
785 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
788 if (!BaseOp->isReg()) in getMemOperandWithOffsetWidth()
810 const MachineOperand *BaseOp; in getMemOperandsWithOffsetWidth() local
812 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
814 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
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| H A D | LanaiInstrInfo.h | 77 const MachineOperand *&BaseOp,
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| /openbsd/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonOptAddrMode.cpp | 430 MachineOperand BaseOp = MI->getOperand(getBaseOpPosition(MI)); in processAddUses() local
432 if (!BaseOp.isReg() || BaseOp.getReg() != AddDefR) in processAddUses()
496 MachineOperand &BaseOp = UseMI->getOperand(getBaseOpPosition(UseMI)); in updateAddUses() local
498 BaseOp.setReg(NewReg); in updateAddUses()
499 BaseOp.setIsUndef(AddRegOp.isUndef()); in updateAddUses()
500 BaseOp.setImplicit(AddRegOp.isImplicit()); in updateAddUses()
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| H A D | HexagonInstrInfo.cpp | 1172 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1178 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1187 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1195 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill) in expandPostRAPseudo()
1200 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1216 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1233 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill) in expandPostRAPseudo()
1238 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
3046 if (!BaseOp || !BaseOp->isReg()) in getMemOperandsWithOffsetWidth()
3048 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
[all …]
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| /openbsd/gnu/llvm/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 107 const MachineOperand *BaseOp = (RelocOp == Op1) ? Op2 : Op1; in checkADDrr() local
148 .add(DefInst->getOperand(0)).addImm(Opcode).add(*BaseOp) in checkADDrr()
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| /openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | EvergreenInstructions.td | 644 field string BaseOp;
653 let BaseOp = name;
659 let BaseOp = name;
675 field string BaseOp;
683 let BaseOp = name;
689 let BaseOp = name;
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| H A D | SIInstrInfo.cpp | 311 if (!BaseOp) { in getMemOperandsWithOffsetWidth()
316 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
352 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
374 if (BaseOp && !BaseOp->isFI()) in getMemOperandsWithOffsetWidth()
375 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
417 if (!BaseOp) // e.g. S_MEMTIME in getMemOperandsWithOffsetWidth()
419 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
431 if (BaseOp) in getMemOperandsWithOffsetWidth()
432 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
434 if (BaseOp) in getMemOperandsWithOffsetWidth()
[all …]
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| /openbsd/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 1205 const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffset() argument
1213 BaseOp = BaseOps.front(); in getMemOperandWithOffset()
1357 const MachineOperand *BaseOp; in describeLoadedValue() local
1358 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, in describeLoadedValue()
1382 return ParamLoadedValue(*BaseOp, Expr); in describeLoadedValue()
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| H A D | MachineSink.cpp | 1016 const MachineOperand *BaseOp; in SinkingPreventsImplicitNullCheck() local
1019 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) in SinkingPreventsImplicitNullCheck()
1022 if (!BaseOp->isReg()) in SinkingPreventsImplicitNullCheck()
1035 MBP.LHS.getReg() == BaseOp->getReg(); in SinkingPreventsImplicitNullCheck()
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| H A D | ModuloSchedule.cpp | 927 const MachineOperand *BaseOp; in computeDelta() local
930 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) in computeDelta()
937 if (!BaseOp->isReg()) in computeDelta()
940 Register BaseReg = BaseOp->getReg(); in computeDelta()
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| H A D | MachinePipeliner.cpp | 2084 const MachineOperand *BaseOp; in computeDelta() local
2087 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) in computeDelta()
2094 if (!BaseOp->isReg()) in computeDelta()
2097 Register BaseReg = BaseOp->getReg(); in computeDelta()
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| /openbsd/gnu/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.h | 132 const MachineOperand *&BaseOp,
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| /openbsd/gnu/llvm/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 1415 unsigned BaseOp = 0; in LowerXALUO() local
1422 BaseOp = M68kISD::ADD; in LowerXALUO()
1426 BaseOp = M68kISD::ADD; in LowerXALUO()
1430 BaseOp = M68kISD::SUB; in LowerXALUO()
1434 BaseOp = M68kISD::SUB; in LowerXALUO()
1441 SDValue Arith = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); in LowerXALUO()
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| /openbsd/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 663 const MachineOperand *&BaseOp,
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| H A D | PPCInstrInfo.cpp | 2854 const MachineOperand *BaseOp; in getMemOperandsWithOffsetWidth() local
2856 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
2858 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
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| /openbsd/gnu/llvm/llvm/include/llvm/Target/ |
| H A D | Target.td | 1792 // let RowFields = BaseOp
1793 // All add instruction predicated/non-predicated will have to set their BaseOp
1796 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
1797 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
1798 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
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| /openbsd/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1384 const MachineOperand *&BaseOp, int64_t &Offset,
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| /openbsd/gnu/llvm/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 3955 unsigned BaseOp = 0; in lowerXALUO() local
3962 BaseOp = SystemZISD::SADDO; in lowerXALUO()
3967 BaseOp = SystemZISD::SSUBO; in lowerXALUO()
3972 BaseOp = SystemZISD::UADDO; in lowerXALUO()
3977 BaseOp = SystemZISD::USUBO; in lowerXALUO()
3984 SDValue Result = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); in lowerXALUO()
4020 unsigned BaseOp = 0; in lowerADDSUBCARRY() local
4030 BaseOp = SystemZISD::ADDCARRY; in lowerADDSUBCARRY()
4038 BaseOp = SystemZISD::SUBCARRY; in lowerADDSUBCARRY()
4050 SDValue Result = DAG.getNode(BaseOp, DL, VTs, LHS, RHS, Carry); in lowerADDSUBCARRY()
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| /openbsd/gnu/llvm/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 7017 unsigned BaseOp; in lowerAddSubSatToMinMax() local
7024 BaseOp = TargetOpcode::G_ADD; in lowerAddSubSatToMinMax()
7029 BaseOp = TargetOpcode::G_ADD; in lowerAddSubSatToMinMax()
7034 BaseOp = TargetOpcode::G_SUB; in lowerAddSubSatToMinMax()
7039 BaseOp = TargetOpcode::G_SUB; in lowerAddSubSatToMinMax()
7073 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, RHSClamped}); in lowerAddSubSatToMinMax()
7079 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, Min}); in lowerAddSubSatToMinMax()
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| /openbsd/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 3741 auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg); in getAddrModeFromMemoryOp() local
3742 if (!BaseOp.isReg()) // Can be an MO_FrameIndex in getAddrModeFromMemoryOp()
3751 AM.BaseReg = BaseOp.getReg(); in getAddrModeFromMemoryOp()
3838 const MachineOperand *BaseOp = in getMemOperandsWithOffsetWidth() local
3840 if (!BaseOp->isReg()) // Can be an MO_FrameIndex in getMemOperandsWithOffsetWidth()
3858 if (!BaseOp->isReg()) in getMemOperandsWithOffsetWidth()
3867 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
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