1 /* $OpenBSD: ciphyreg.h,v 1.4 2022/01/09 05:42:44 jsg Exp $ */ 2 /* $FreeBSD: ciphyreg.h,v 1.1 2004/09/10 20:57:45 wpaul Exp $ */ 3 /* 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef _DEV_MII_CIPHYREG_H_ 36 #define _DEV_MII_CIPHYREG_H_ 37 38 /* 39 * Register definitions for the Cicada CS8201 10/100/1000 gigE copper 40 * PHY, embedded within the VIA Networks VT6122 controller. 41 */ 42 43 /* Vendor-specific PHY registers */ 44 45 /* 100baseTX status extension register */ 46 #define CIPHY_MII_100STS 0x10 47 #define CIPHY_100STS_DESLCK 0x8000 /* descrambler locked */ 48 #define CIPHY_100STS_LKCERR 0x4000 /* lock error detected/lock lost */ 49 #define CIPHY_100STS_DISC 0x2000 /* disconnect state */ 50 #define CIPHY_100STS_LINK 0x1000 /* current link state */ 51 #define CIPHY_100STS_RXERR 0x0800 /* receive error detected */ 52 #define CIPHY_100STS_TXERR 0x0400 /* transmit error detected */ 53 #define CIPHY_100STS_SSDERR 0x0200 /* false carrier error detected */ 54 #define CIPHY_100STS_ESDERR 0x0100 /* premature end of stream error */ 55 56 /* 1000BT status extension register #2 */ 57 #define CIPHY_MII_1000STS2 0x11 58 #define CIPHY_1000STS2_DESLCK 0x8000 /* descrambler locked */ 59 #define CIPHY_1000STS2_LKCERR 0x4000 /* lock error detected/lock lost */ 60 #define CIPHY_1000STS2_DISC 0x2000 /* disconnect state */ 61 #define CIPHY_1000STS2_LINK 0x1000 /* current link state */ 62 #define CIPHY_1000STS2_RXERR 0x0800 /* receive error detected */ 63 #define CIPHY_1000STS2_TXERR 0x0400 /* transmit error detected */ 64 #define CIPHY_1000STS2_SSDERR 0x0200 /* false carrier error detected */ 65 #define CIPHY_1000STS2_ESDERR 0x0100 /* premature end of stream error */ 66 #define CIPHY_1000STS2_CARREXT 0x0080 /* carrier extension err detected */ 67 #define CIPHY_1000STS2_BCM5400 0x0040 /* non-compliant BCM5400 detected */ 68 69 /* Bypass control register */ 70 #define CIPHY_MII_BYPASS 0x12 71 #define CIPHY_BYPASS_TX 0x8000 /* transmit disable */ 72 #define CIPHY_BYPASS_4B5B 0x4000 /* bypass the 4B5B encoder */ 73 #define CIPHY_BYPASS_SCRAM 0x2000 /* bypass scrambler */ 74 #define CIPHY_BYPASS_DSCAM 0x1000 /* bypass descrambler */ 75 #define CIPHY_BYPASS_PCSRX 0x0800 /* bypass PCS receive */ 76 #define CIPHY_BYPASS_PCSTX 0x0400 /* bypass PCS transmit */ 77 #define CIPHY_BYPASS_LFI 0x0200 /* bypass LFI timer */ 78 #define CIPHY_BYPASS_TXCLK 0x0100 /* enable transmit clock on LED4 pin */ 79 #define CIPHY_BYPASS_BCM5400_F 0x0080 /* force BCM5400 detect */ 80 #define CIPHY_BYPASS_BCM5400 0x0040 /* bypass BCM5400 detect */ 81 #define CIPHY_BYPASS_PAIRSWAP 0x0020 /* disable automatic pair swap */ 82 #define CIPHY_BYPASS_POLARITY 0x0010 /* disable polarity correction */ 83 #define CIPHY_BYPASS_PARALLEL 0x0008 /* parallel detect enable */ 84 #define CIPHY_BYPASS_PULSE 0x0004 /* disable pulse shaping filter */ 85 #define CIPHY_BYPASS_1000BNP 0x0002 /* disable 1000BT next page exchange */ 86 87 /* RX error count register */ 88 #define CIPHY_MII_RXERR 0x13 89 90 /* False carrier sense count register */ 91 #define CIPHY_MII_FCSERR 0x14 92 93 /* Ddisconnect error counter */ 94 #define CIPHY_MII_DISCERR 0x15 95 96 /* 10baseT control/status register */ 97 #define CIPHY_MII_10BTCSR 0x16 98 #define CIPHY_10BTCSR_DLIT 0x8000 /* Disable data link integrity test */ 99 #define CIPHY_10BTCSR_JABBER 0x4000 /* Disable jabber detect */ 100 #define CIPHY_10BTCSR_ECHO 0x2000 /* Disable echo mode */ 101 #define CIPHY_10BTCSR_SQE 0x1000 /* Disable signal quality error */ 102 #define CIPHY_10BTCSR_SQUENCH 0x0C00 /* Squelch control */ 103 #define CIPHY_10BTCSR_EOFERR 0x0100 /* End of Frame error */ 104 #define CIPHY_10BTCSR_DISC 0x0080 /* Disconnect status */ 105 #define CIPHY_10BTCSR_LINK 0x0040 /* current link state */ 106 #define CIPHY_10BTCSR_ITRIM 0x0038 /* current reference trim */ 107 #define CIPHY_10BTCSR_CSR 0x0006 /* CSR behavior control */ 108 109 #define CIPHY_SQUELCH_300MV 0x0000 110 #define CIPHY_SQUELCH_197MV 0x0400 111 #define CIPHY_SQUELCH_450MV 0x0800 112 #define CIPHY_SQUELCH_RSVD 0x0C00 113 114 #define CIPHY_ITRIM_PLUS2 0x0000 115 #define CIPHY_ITRIM_PLUS4 0x0008 116 #define CIPHY_ITRIM_PLUS6 0x0010 117 #define CIPHY_ITRIM_PLUS6_ 0x0018 118 #define CIPHY_ITRIM_MINUS4 0x0020 119 #define CIPHY_ITRIM_MINUS4_ 0x0028 120 #define CIPHY_ITRIM_MINUS2 0x0030 121 #define CIPHY_ITRIM_ZERO 0x0038 122 123 /* Extended PHY control register #1 */ 124 #define CIPHY_MII_ECTL1 0x17 125 #define CIPHY_ECTL1_ACTIPHY 0x0020 /* Enable ActiPHY power saving */ 126 #define CIPHY_ECTL1_IOVOL 0x0e00 /* MAC interface and I/O voltage select */ 127 #define CIPHY_ECTL1_INTSEL 0xf000 /* select MAC interface */ 128 129 #define CIPHY_IOVOL_3300MV 0x0000 /* 3.3V for I/O pins */ 130 #define CIPHY_IOVOL_2500MV 0x0200 /* 2.5V for I/O pins */ 131 132 #define CIPHY_INTSEL_GMII 0x0000 /* GMII/MII */ 133 #define CIPHY_INTSEL_RGMII 0x1000 134 #define CIPHY_INTSEL_TBI 0x2000 135 #define CIPHY_INTSEL_RTBI 0x3000 136 137 /* Extended PHY control register #2 */ 138 #define CIPHY_MII_ECTL2 0x18 139 #define CIPHY_ECTL2_ERATE 0xE000 /* 10/1000 edge rate control */ 140 #define CIPHY_ECTL2_VTRIM 0x1C00 /* voltage reference trim */ 141 #define CIPHY_ECTL2_CABLELEN 0x000E /* Cable quality/length */ 142 #define CIPHY_ECTL2_ANALOGLOOP 0x0001 /* 1000BT analog loopback */ 143 144 #define CIPHY_CABLELEN_0TO10M 0x0000 145 #define CIPHY_CABLELEN_10TO20M 0x0002 146 #define CIPHY_CABLELEN_20TO40M 0x0004 147 #define CIPHY_CABLELEN_40TO80M 0x0006 148 #define CIPHY_CABLELEN_80TO100M 0x0008 149 #define CIPHY_CABLELEN_100TO140M 0x000A 150 #define CIPHY_CABLELEN_140TO180M 0x000C 151 #define CIPHY_CABLELEN_OVER180M 0x000E 152 153 /* Interrupt mask register */ 154 #define CIPHY_MII_IMR 0x19 155 #define CIPHY_IMR_PINENABLE 0x8000 /* Interrupt pin enable */ 156 #define CIPHY_IMR_SPEED 0x4000 /* speed changed event */ 157 #define CIPHY_IMR_LINK 0x2000 /* link change/ActiPHY event */ 158 #define CIPHY_IMR_DPX 0x1000 /* duplex change event */ 159 #define CIPHY_IMR_ANEGERR 0x0800 /* autoneg error event */ 160 #define CIPHY_IMR_ANEGDONE 0x0400 /* autoneg done event */ 161 #define CIPHY_IMR_NPRX 0x0200 /* page received event */ 162 #define CIPHY_IMR_SYMERR 0x0100 /* symbol error event */ 163 #define CIPHY_IMR_LOCKERR 0x0080 /* descrambler lock lost event */ 164 #define CIPHY_IMR_XOVER 0x0040 /* MDI crossover change event */ 165 #define CIPHY_IMR_POLARITY 0x0020 /* polarity change event */ 166 #define CIPHY_IMR_JABBER 0x0010 /* jabber detect event */ 167 #define CIPHY_IMR_SSDERR 0x0008 /* false carrier detect event */ 168 #define CIPHY_IMR_ESDERR 0x0004 /* parallel detect error event */ 169 #define CIPHY_IMR_MASTERSLAVE 0x0002 /* master/slave resolve done event */ 170 #define CIPHY_IMR_RXERR 0x0001 /* RX error event */ 171 172 /* Interrupt status register */ 173 #define CIPHY_MII_ISR 0x1A 174 #define CIPHY_ISR_IPENDING 0x8000 /* Interrupt is pending */ 175 #define CIPHY_ISR_SPEED 0x4000 /* speed changed event */ 176 #define CIPHY_ISR_LINK 0x2000 /* link change/ActiPHY event */ 177 #define CIPHY_ISR_DPX 0x1000 /* duplex change event */ 178 #define CIPHY_ISR_ANEGERR 0x0800 /* autoneg error event */ 179 #define CIPHY_ISR_ANEGDONE 0x0400 /* autoneg done event */ 180 #define CIPHY_ISR_NPRX 0x0200 /* page received event */ 181 #define CIPHY_ISR_SYMERR 0x0100 /* symbol error event */ 182 #define CIPHY_ISR_LOCKERR 0x0080 /* descrambler lock lost event */ 183 #define CIPHY_ISR_XOVER 0x0040 /* MDI crossover change event */ 184 #define CIPHY_ISR_POLARITY 0x0020 /* polarity change event */ 185 #define CIPHY_ISR_JABBER 0x0010 /* jabber detect event */ 186 #define CIPHY_ISR_SSDERR 0x0008 /* false carrier detect event */ 187 #define CIPHY_ISR_ESDERR 0x0004 /* parallel detect error event */ 188 #define CIPHY_ISR_MASTERSLAVE 0x0002 /* master/slave resolve done event */ 189 #define CIPHY_ISR_RXERR 0x0001 /* RX error event */ 190 191 /* LED control register */ 192 #define CIPHY_MII_LED 0x1B 193 #define CIPHY_LED_LINK10FORCE 0x8000 /* Force on link10 LED */ 194 #define CIPHY_LED_LINK10DIS 0x4000 /* Disable link10 LED */ 195 #define CIPHY_LED_LINK100FORCE 0x2000 /* Force on link10 LED */ 196 #define CIPHY_LED_LINK100DIS 0x1000 /* Disable link100 LED */ 197 #define CIPHY_LED_LINK1000FORCE 0x0800 /* Force on link1000 LED */ 198 #define CIPHY_LED_LINK1000DIS 0x0400 /* Disable link1000 LED */ 199 #define CIPHY_LED_FDXFORCE 0x0200 /* Force on duplex LED */ 200 #define CIPHY_LED_FDXDIS 0x0100 /* Disable duplex LED */ 201 #define CIPHY_LED_ACTFORCE 0x0080 /* Force on activity LED */ 202 #define CIPHY_LED_ACTDIS 0x0040 /* Disable activity LED */ 203 #define CIPHY_LED_PULSE 0x0008 /* LED pulse enable */ 204 #define CIPHY_LED_LINKACTBLINK 0x0004 /* enable link/activity LED blink */ 205 #define CIPHY_LED_BLINKRATE 0x0002 /* blink rate 0=10hz, 1=5hz */ 206 207 /* Auxiliary control and status register */ 208 #define CIPHY_MII_AUXCSR 0x1C 209 #define CIPHY_AUXCSR_ANEGDONE 0x8000 /* Autoneg complete */ 210 #define CIPHY_AUXCSR_ANEGOFF 0x4000 /* Autoneg disabled */ 211 #define CIPHY_AUXCSR_XOVER 0x2000 /* MDI/MDI-X crossover indication */ 212 #define CIPHY_AUXCSR_PAIRSWAP 0x1000 /* pair swap indication */ 213 #define CIPHY_AUXCSR_APOLARITY 0x0800 /* polarity inversion pair A */ 214 #define CIPHY_AUXCSR_BPOLARITY 0x0400 /* polarity inversion pair B */ 215 #define CIPHY_AUXCSR_CPOLARITY 0x0200 /* polarity inversion pair C */ 216 #define CIPHY_AUXCSR_DPOLARITY 0x0100 /* polarity inversion pair D */ 217 #define CIPHY_AUXCSR_FDX 0x0020 /* duplex 1=full, 0=half */ 218 #define CIPHY_AUXCSR_SPEED 0x0018 /* speed */ 219 #define CIPHY_AUXCSR_MDPPS 0x0004 /* No idea, not documented */ 220 #define CIPHY_AUXCSR_STICKYREST 0x0002 /* reset clears sticky bits */ 221 222 #define CIPHY_SPEED10 0x0000 223 #define CIPHY_SPEED100 0x0008 224 #define CIPHY_SPEED1000 0x0010 225 226 /* Delay skew status register */ 227 #define CIPHY_MII_DSKEW 0x1D 228 #define CIPHY_DSKEW_PAIRA 0x7000 /* Pair A skew in symbol times */ 229 #define CIPHY_DSKEW_PAIRB 0x0700 /* Pair B skew in symbol times */ 230 #define CIPHY_DSKEW_PAIRC 0x0070 /* Pair C skew in symbol times */ 231 #define CIPHY_DSKEW_PAIRD 0x0007 /* Pair D skew in symbol times */ 232 233 #endif /* _DEV_CIPHY_MIIREG_H_ */ 234