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Searched refs:CLK_BASE (Results 1 – 25 of 26) sorted by relevance

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/openbsd/sys/dev/pci/drm/amd/display/dc/inc/hw/
H A Dclk_mgr_internal.h81 #define CLK_BASE(inst) \ macro
85 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr_clk.c44 CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dvega10_reg_init.c53 adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); in vega10_reg_base_init()
H A Dvega20_reg_init.c51 adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); in vega20_reg_base_init()
/openbsd/sys/dev/pci/drm/amd/include/
H A Dcyan_skillfish_ip_offset.h45 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0, 0, 0, 0 } }, variable
H A Dnavi10_ip_offset.h43 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x0001… variable
H A Ddimgrey_cavefish_ip_offset.h46 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, variable
H A Dnavi12_ip_offset.h46 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } }, variable
H A Dnavi14_ip_offset.h46 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } }, variable
H A Dvega20_ip_offset.h45 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x0001… variable
H A Dsienna_cichlid_ip_offset.h46 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0 } }, variable
H A Dbeige_goby_ip_offset.h47 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, variable
H A Drenoir_ip_offset.h53 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017E00, 0 } }, variable
H A Dvega10_ip_offset.h203 static const struct IP_BASE __maybe_unused CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } }, variable
H A Dvangogh_ip_offset.h58 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, variable
H A Dyellow_carp_offset.h33 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, variable
H A Darct_ip_offset.h47 static const struct IP_BASE CLK_BASE ={ { { { 0x000120C0, 0x00016C00, 0x00401800, 0, 0, … variable
H A Daldebaran_ip_offset.h42 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, variable
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c72 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0, 0, 0 } }, variable
91 (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn301/
H A Ddcn301_resource.c184 #define CLK_BASE(seg) \ macro
188 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c59 (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.c51 (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c70 (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn314/
H A Ddcn314_resource.c208 #define CLK_BASE(seg) \ macro
212 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn31/
H A Ddcn31_resource.c192 #define CLK_BASE(seg) \ macro
196 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \

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