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Searched refs:CLK_BASE__INST0_SEG1 (Results 1 – 14 of 14) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/
H A Dcyan_skillfish_ip_offset.h174 #define CLK_BASE__INST0_SEG1 0 macro
H A Dnavi10_ip_offset.h184 #define CLK_BASE__INST0_SEG1 0x00016E00 macro
H A Ddimgrey_cavefish_ip_offset.h217 #define CLK_BASE__INST0_SEG1 0x02401800 macro
H A Dnavi12_ip_offset.h238 #define CLK_BASE__INST0_SEG1 0x02401800 macro
H A Dnavi14_ip_offset.h238 #define CLK_BASE__INST0_SEG1 0x02401800 macro
H A Dvega20_ip_offset.h211 #define CLK_BASE__INST0_SEG1 0x00016E00 macro
H A Dsienna_cichlid_ip_offset.h245 #define CLK_BASE__INST0_SEG1 0x02401800 macro
H A Dbeige_goby_ip_offset.h246 #define CLK_BASE__INST0_SEG1 0x02401800 macro
H A Drenoir_ip_offset.h320 #define CLK_BASE__INST0_SEG1 0x00016E00 macro
H A Dvega10_ip_offset.h1206 #define CLK_BASE__INST0_SEG1 0 macro
H A Dvangogh_ip_offset.h341 #define CLK_BASE__INST0_SEG1 0x02401800 macro
H A Dyellow_carp_offset.h288 #define CLK_BASE__INST0_SEG1 0x02401800 macro
H A Darct_ip_offset.h303 #define CLK_BASE__INST0_SEG1 0x00016C00 macro
H A Daldebaran_ip_offset.h318 #define CLK_BASE__INST0_SEG1 0x02401800 macro