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Searched refs:CP_CPC_IC_BASE_CNTL__VMID__SHIFT (Results 1 – 11 of 11) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h2502 #define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0 macro
H A Dgfx_8_1_sh_mask.h3024 #define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0 macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11942 #define CP_CPC_IC_BASE_CNTL__VMID__SHIFT … macro
H A Dgc_9_1_sh_mask.h13372 #define CP_CPC_IC_BASE_CNTL__VMID__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h13150 #define CP_CPC_IC_BASE_CNTL__VMID__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h15155 #define CP_CPC_IC_BASE_CNTL__VMID__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h3348 #define CP_CPC_IC_BASE_CNTL__VMID__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h33924 #define CP_CPC_IC_BASE_CNTL__VMID__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h39573 #define CP_CPC_IC_BASE_CNTL__VMID__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h37009 #define CP_CPC_IC_BASE_CNTL__VMID__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h36236 #define CP_CPC_IC_BASE_CNTL__VMID__SHIFT … macro