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Searched refs:CP_RB0_CNTL__CACHE_POLICY__SHIFT (Results 1 – 13 of 13) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2713 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x00000018 macro
H A Dgfx_7_2_sh_mask.h1052 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 macro
H A Dgfx_8_0_sh_mask.h1370 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 macro
H A Dgfx_8_1_sh_mask.h1894 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h10695 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT … macro
H A Dgc_9_1_sh_mask.h12176 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h11981 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h13703 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h1997 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h15102 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h17600 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h17254 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h15860 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT … macro