| /openbsd/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenExtract.cpp | 100 ConstantInt *CSL = nullptr, *CSR = nullptr, *CM = nullptr; in INITIALIZE_PASS_DEPENDENCY() local
107 bool Match = match(In, m_And(m_Shl(m_LShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
114 Match = match(In, m_And(m_Shl(m_AShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
121 CSR = ConstantInt::get(Type::getInt32Ty(Ctx), 0); in INITIALIZE_PASS_DEPENDENCY()
131 Match = match(In, m_And(m_LShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
138 Match = match(In, m_And(m_AShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
145 Match = match(In, m_Shl(m_LShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
152 Match = match(In, m_Shl(m_AShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
165 uint32_t SR = CSR->getZExtValue(); in INITIALIZE_PASS_DEPENDENCY()
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| H A D | HexagonVLIWPacketizer.cpp | 351 for (auto *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR) in doesModifyCalleeSavedReg() local
352 if (MI.modifiesRegister(*CSR, TRI)) in doesModifyCalleeSavedReg()
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| H A D | HexagonFrameLowering.cpp | 286 static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR, in needsStackFrame() argument
315 if (CSR[*S]) in needsStackFrame()
325 for (int x = CSR.find_first(); x >= 0; x = CSR.find_next(x)) { in needsStackFrame()
440 BitVector CSR(Hexagon::NUM_TARGET_REGS); in findShrunkPrologEpilog() local
443 CSR[*S] = true; in findShrunkPrologEpilog()
446 if (needsStackFrame(I, CSR, HRI)) in findShrunkPrologEpilog()
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| /openbsd/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | LiveRegUnits.cpp | 99 for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; ++CSR) { in addCalleeSavedRegs() local
100 const unsigned N = *CSR; in addCalleeSavedRegs()
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| H A D | RegisterClassInfo.cpp | 57 const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); in runOnMachineFunction() local
63 if (CSR[I] == 0) { in runOnMachineFunction()
71 if (CSR[I] != LastCalleeSavedRegs[I]) { in runOnMachineFunction()
84 for (const MCPhysReg *I = CSR; *I; ++I) { in runOnMachineFunction()
96 for (const MCPhysReg *I = CSR; *I; ++I) in runOnMachineFunction()
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| H A D | MachineFrameInfo.cpp | 125 for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; in getPristineRegs() local
126 ++CSR) in getPristineRegs()
127 BV.set(*CSR); in getPristineRegs()
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| H A D | LivePhysRegs.cpp | 177 for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; ++CSR) in addCalleeSavedRegs() local
178 LiveRegs.addReg(*CSR); in addCalleeSavedRegs()
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| H A D | RegAllocPBQP.cpp | 583 const MCPhysReg *CSR = MF.getRegInfo().getCalleeSavedRegs(); in isACalleeSavedRegister() local
584 for (unsigned i = 0; CSR[i] != 0; ++i) in isACalleeSavedRegister()
585 if (TRI.regsOverlap(Reg, CSR[i])) in isACalleeSavedRegister()
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| H A D | MachineRegisterInfo.cpp | 609 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); in disableCalleeSavedRegister() local
610 for (const MCPhysReg *I = CSR; *I; ++I) in disableCalleeSavedRegister()
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| /openbsd/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86MachineFunctionInfo.cpp | 30 for (const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs(); in setRestoreBasePointer() local
31 unsigned Reg = *CSR; ++CSR) { in setRestoreBasePointer()
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| /openbsd/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMCallingConv.td | 278 // R8 is used to pass swifterror, remove it from CSR.
281 // R10 is used to pass swiftself, remove it from CSR.
296 // R8 is used to pass swifterror, remove it from CSR.
300 // R10 is used to pass swifterror, remove it from CSR.
325 // R8 is used to pass swifterror, remove it from CSR.
328 // R10 is used to pass swiftself, remove it from CSR.
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| H A D | ARMRegisterInfo.td | 229 // Allocate LR as the first CSR since it is always saved anyway.
246 // Allocate LR as the first CSR since it is always saved anyway.
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| /openbsd/gnu/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCV.td | 18 // Named operands for CSR instructions.
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| H A D | RISCVSystemOperands.td | 17 // CSR (control and status register read/write) instruction options.
69 // The following CSR encodings match those given in Tables 2.2,
377 // Entropy Source CSR
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| H A D | RISCVFrameLowering.cpp | 45 CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; })) in emitSCSPrologue() argument
95 CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; })) in emitSCSEpilogue() argument
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| H A D | RISCVSchedule.td | 29 def WriteCSR : SchedWrite; // CSR instructions
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| /openbsd/gnu/llvm/llvm/lib/Target/Lanai/ |
| H A D | LanaiCallingConv.td | 49 def CSR: CalleeSavedRegs<(add)>;
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| /openbsd/gnu/llvm/llvm/lib/Target/BPF/ |
| H A D | BPFCallingConv.td | 48 def CSR : CalleeSavedRegs<(add R6, R7, R8, R9, R10)>;
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| /openbsd/gnu/llvm/llvm/lib/Target/XCore/ |
| H A D | XCoreFrameLowering.cpp | 458 for (const CalleeSavedInfo &CSR : CSI) { in restoreCalleeSavedRegisters() local
459 Register Reg = CSR.getReg(); in restoreCalleeSavedRegisters()
464 TII.loadRegFromStackSlot(MBB, MI, Reg, CSR.getFrameIdx(), RC, TRI, in restoreCalleeSavedRegisters()
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| /openbsd/gnu/llvm/llvm/tools/llvm-diff/lib/ |
| H A D | DifferenceEngine.cpp | 617 const ConstantStruct *CSR = cast<ConstantStruct>(R); in equivalentAsOperands() local
620 const StructType *RTy = cast<StructType>(CSR->getType()); in equivalentAsOperands()
631 const Value *RAgg = CSR->getAggregateElement(I); in equivalentAsOperands()
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| /openbsd/gnu/llvm/llvm/lib/Target/VE/ |
| H A D | VECallingConv.td | 147 def CSR : CalleeSavedRegs<(add (sequence "SX%u", 18, 33))>;
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| /openbsd/gnu/llvm/llvm/lib/Target/Sparc/ |
| H A D | SparcCallingConv.td | 139 def CSR : CalleeSavedRegs<(add)> {
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| /openbsd/gnu/llvm/llvm/include/llvm/TargetParser/ |
| H A D | Triple.h | 177 CSR, enumerator
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| /openbsd/gnu/llvm/llvm/lib/TargetParser/ |
| H A D | Triple.cpp | 187 case CSR: return "csr"; in getVendorTypeName()
549 .Case("csr", Triple::CSR) in parseVendor()
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| /openbsd/gnu/llvm/llvm/lib/Target/SystemZ/ |
| H A D | SystemZCallingConv.td | 149 // R9 is used to return SwiftError; remove it from CSR.
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