1 /* $OpenBSD: lxtphyreg.h,v 1.3 2022/01/09 05:42:44 jsg Exp $ */ 2 /* $NetBSD: lxtphyreg.h,v 1.1 1998/10/24 00:33:17 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _DEV_MII_LXTPHYREG_H_ 35 #define _DEV_MII_LXTPHYREG_H_ 36 37 /* 38 * LXT970 registers. 39 */ 40 41 #define MII_LXTPHY_MIRROR 0x10 /* Mirror register */ 42 /* All bits user-defined */ 43 44 #define MII_LXTPHY_IER 0x11 /* Interrupt Enable Register */ 45 #define IER_MIIDRVLVL 0x0008 /* Reduced MII driver levels */ 46 #define IER_LNK_CRITERIA 0x0004 /* Enhanced Link Loss Criteria */ 47 #define IER_INTEN 0x0002 /* Interrupt Enable */ 48 #define IER_TINT 0x0001 /* Force Interrupt */ 49 50 #define MII_LXTPHY_ISR 0x12 /* Interrupt Status Register */ 51 #define ISR_MINT 0x8000 /* MII Interrupt Pending */ 52 #define ISR_XTALOK 0x4000 /* Clocks OK */ 53 54 #define MII_LXTPHY_CONFIG 0x13 /* Configuration Register */ 55 #define CONFIG_TXMIT_TEST 0x4000 /* 100base-T Transmit Test */ 56 #define CONFIG_REPEATER 0x2000 /* Repeater Mode */ 57 #define CONFIG_MDIO_INT 0x1000 /* Enable intr signalling on MDIO */ 58 #define CONFIG_TPLOOP 0x0800 /* Disable 10base-T Loopback */ 59 #define CONFIG_SQE 0x0400 /* Enable SQE */ 60 #define CONFIG_DISJABBER 0x0200 /* Disable Jabber */ 61 #define CONFIG_DISLINKTEST 0x0100 /* Disable Link Test */ 62 #define CONFIG_LEDC1 0x0080 /* LEDC configuration */ 63 #define CONFIG_LEDC0 0x0040 /* ... */ 64 /* 0 0 LEDC indicates collision */ 65 /* 0 1 LEDC is off */ 66 /* 1 0 LEDC indicates activity */ 67 /* 1 1 LEDC is on */ 68 #define CONFIG_ADVTXCLK 0x0020 /* Advance TX clock */ 69 #define CONFIG_5BSYMBOL 0x0010 /* 5-bit Symbol mode */ 70 #define CONFIG_SCRAMBLER 0x0008 /* Bypass scrambler */ 71 #define CONFIG_100BASEFX 0x0004 /* 100base-FX */ 72 #define CONFIG_TXDISCON 0x0001 /* Disconnect TP transmitter */ 73 74 #define MII_LXTPHY_CSR 0x14 /* Chip Status Register */ 75 #define CSR_LINK 0x2000 /* Link is up */ 76 #define CSR_DUPLEX 0x1000 /* Full-duplex */ 77 #define CSR_SPEED 0x0800 /* 100Mbps */ 78 #define CSR_ACOMP 0x0400 /* Autonegotiation complete */ 79 #define CSR_PAGERCVD 0x0200 /* Link page received */ 80 #define CSR_LOWVCC 0x0004 /* Low Voltage Fault */ 81 82 #endif /* _DEV_MII_LXTPHYREG_H_ */ 83