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Searched refs:DAG (Results 1 – 25 of 266) sorted by relevance

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/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h220 SelectionDAG &DAG) const;
222 SelectionDAG &DAG) const;
224 SelectionDAG &DAG) const;
375 SelectionDAG &DAG,
378 SelectionDAG &DAG) const;
380 SelectionDAG &DAG) const;
390 SelectionDAG &DAG) const;
397 SelectionDAG &DAG) const;
448 SelectionDAG &DAG) const;
460 SDValue Idx = getZero(dl, MVT::i32, DAG); in LoHalf()
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H A DHexagonISelLoweringHVX.cpp850 return DAG.getLoad(VecTy, dl, DAG.getEntryNode(), CP, in buildHvxVectorReg()
1537 DAG.getLoad(ByteTy, dl, DAG.getEntryNode(), CP, in compressHvxPred()
1916 Op.dump(&DAG); in LowerHvxMulh()
2522 {HiHalf(P2, DAG), LoHalf(P1, DAG), S16}, DAG); in emitHvxMulHsV60()
2570 {HiHalf(P1, DAG), LoHalf(P1, DAG)}, DAG); in emitHvxMulLoHiV60()
2578 {HiHalf(P2, DAG), T3, S16}, DAG); in emitHvxMulLoHiV60()
2582 {LoHalf(P0, DAG), LoHalf(P2, DAG), S16}, DAG); in emitHvxMulLoHiV60()
3348 return opJoin(SplitVectorOp(Op, DAG), SDLoc(Op), DAG); in LegalizeHvxResize()
3487 SelectionDAG &DAG = DCI.DAG; in combineTruncateBeforeLegal() local
3527 SelectionDAG &DAG = DCI.DAG; in combineConcatVectorsBeforeLegal() local
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H A DHexagonISelLowering.cpp178 return DAG.getMemcpy( in CreateCopyOfByValArgument()
405 SelectionDAG &DAG = CLI.DAG; in LowerCall() local
1182 return DAG.getLoad(VT, dl, DAG.getEntryNode(), in LowerRETURNADDR()
1189 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT); in LowerRETURNADDR()
1201 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, in LowerFRAMEADDR()
1204 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, in LowerFRAMEADDR()
1987 return DAG.getMergeValues({DAG.getUNDEF(ty(Op)), Trap}, dl); in replaceMemWithUndef()
2521 return DAG.getBitcast(VecTy, DAG.getConstant(V, dl, MVT::i32)); in buildVector32()
2672 ExtV = Off == 0 ? LoHalf(VecV, DAG) : HiHalf(VecV, DAG); in extractVector()
2821 ValR = getCombine(DAG.getUNDEF(MVT::i32), ValR, dl, MVT::i64, DAG); in insertVectorPred()
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/openbsd/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp34 return DAG.getNode(Op, DL, VTs, Ops); in createMemMemNode()
54 SDValue LenAdj = DAG.getNode(ISD::ADD, DL, MVT::i64, in emitMemMemReg()
83 return DAG.getStore( in memsetStore()
117 Dst = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, in EmitTargetCodeForMemset()
163 SelectionDAG &DAG) { in addIPMSequence() argument
194 Length = DAG.getZExtOrTrunc(Length, DL, PtrVT); in EmitTargetCodeForMemchr()
195 Char = DAG.getZExtOrTrunc(Char, DL, MVT::i32); in EmitTargetCodeForMemchr()
196 Char = DAG.getNode(ISD::AND, DL, MVT::i32, Char, in EmitTargetCodeForMemchr()
207 End, DAG.getConstant(0, DL, PtrVT), in EmitTargetCodeForMemchr()
259 return getBoundedStrlen(DAG, DL, Chain, Src, DAG.getConstant(0, DL, PtrVT)); in EmitTargetCodeForStrlen()
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/openbsd/gnu/llvm/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp302 return DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, in LowerGlobalAddress()
719 SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), in ExpandADDSUB()
723 SDValue Hi = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), in ExpandADDSUB()
780 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), in LowerFRAMEADDR()
798 return DAG.getLoad(getPointerTy(DAG.getDataLayout()), SDLoc(Op), in LowerRETURNADDR()
826 SDValue Stack = DAG.getCopyFromReg(DAG.getEntryNode(), dl, in LowerEH_RETURN()
918 DAG.getNode(XCoreISD::CRC8, DL, DAG.getVTList(VT, VT), in LowerINTRINSIC_WO_CHAIN()
943 return DAG.getLoad(getPointerTy(DAG.getDataLayout()), SDLoc(Op), in LowerATOMIC_LOAD()
1029 SelectionDAG &DAG = CLI.DAG; in LowerCall() local
1584 SelectionDAG &DAG = DCI.DAG; in PerformDAGCombine() local
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/openbsd/gnu/llvm/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp407 SelectionDAG &DAG = CLI.DAG; in LowerCall() local
515 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]); in LowerCCCArguments()
580 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout())); in LowerReturn()
585 DAG.getRegister(Lanai::RV, getPointerTy(DAG.getDataLayout()))); in LowerReturn()
644 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); in LowerCCCCallTo()
700 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr, in LowerCCCCallTo()
960 DAG.getNode(ISD::SHL, DL, VT, V, DAG.getConstant(I, DL, MVT::i32)); in LowerMUL()
1066 return DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo()); in LowerRETURNADDR()
1072 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT); in LowerRETURNADDR()
1089 DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo()); in LowerFRAMEADDR()
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/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1200 SelectionDAG &DAG = CLI.DAG; in lowerUnhandledCall() local
1418 SelectionDAG &DAG = DCI.DAG; in combineFMinMaxLegacy() local
2886 SelectionDAG &DAG = DCI.DAG; in simplifyMul24() local
2989 SelectionDAG &DAG = DCI.DAG; in performLoadCombine() local
3045 SelectionDAG &DAG = DCI.DAG; in performStoreCombine() local
3091 SelectionDAG &DAG = DCI.DAG; in performAssertSZExtCombine() local
3142 SelectionDAG &DAG = DCI.DAG; in splitBinaryBitConstantOpImpl() local
3175 SelectionDAG &DAG = DCI.DAG; in performShlCombine() local
3238 SelectionDAG &DAG = DCI.DAG; in performSraCombine() local
3273 SelectionDAG &DAG = DCI.DAG; in performSrlCombine() local
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H A DGCNSchedStrategy.cpp302 if (DAG->top() == DAG->bottom()) { in pickNode()
664 : DAG(DAG), S(static_cast<GCNSchedStrategy &>(*DAG.SchedImpl)), MF(DAG.MF), in GCNSchedStage()
712 if (DAG.StartingOccupancy <= DAG.MinOccupancy) in initGCNSchedStage()
761 DAG.Pressure[IDX].getOccupancy(DAG.ST) == DAG.MinOccupancy; in finalizeGCNSchedStage()
777 DAG.enterRegion(CurrentMBB, DAG.begin(), DAG.end(), NumRegionInstrs); in initGCNRegion()
780 if (DAG.begin() == DAG.end() || DAG.begin() == std::prev(DAG.end())) in initGCNRegion()
872 DAG.Regions[RegionIdx] = std::pair(DAG.RegionBegin, DAG.RegionEnd); in finalizeGCNRegion()
1175 DAG.RegionEnd = DAG.RegionBegin; in revertScheduling()
1185 DAG.BB->insert(DAG.RegionEnd, MI); in revertScheduling()
1195 RegOpers.collect(*MI, *DAG.TRI, DAG.MRI, DAG.ShouldTrackLaneMasks, false); in revertScheduling()
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H A DR600ISelLowering.cpp741 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); in LowerUADDSUBO()
746 return DAG.getNode( in lowerFP_TO_UINT()
751 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_UINT()
756 return DAG.getNode( in lowerFP_TO_SINT()
761 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_SINT()
774 return DAG.getLoad(VT, DL, DAG.getEntryNode(), in LowerImplicitParameter()
1404 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(2, DL, MVT::i32)); in LowerLOAD()
1517 SDValue Arg = DAG.getLoad( in LowerFormalArguments()
1519 DAG.getConstant(PartOffset, DL, MVT::i32), DAG.getUNDEF(MVT::i32), in LowerFormalArguments()
1726 SelectionDAG &DAG = DCI.DAG; in PerformDAGCombine() local
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H A DSIISelLowering.h64 SDValue getPreloadedValue(SelectionDAG &DAG,
102 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
110 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
111 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
112 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
134 SDValue getFPExtOrFPRound(SelectionDAG &DAG,
150 SelectionDAG &DAG) const;
160 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
202 unsigned getFusedOpcode(const SelectionDAG &DAG,
354 SelectionDAG &DAG) const override;
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/openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp562 SelectionDAG &DAG = TLO.DAG; in ShrinkDemandedOp() local
600 SelectionDAG &DAG = DCI.DAG; in SimplifyDemandedBits() local
616 SelectionDAG &DAG = DCI.DAG; in SimplifyDemandedBits() local
2751 SelectionDAG &DAG = DCI.DAG; in SimplifyDemandedVectorElts() local
3728 SelectionDAG &DAG = DCI.DAG; in foldSetCCWithAnd() local
3892 SelectionDAG &DAG = DCI.DAG; in optimizeSetCCOfSignedTruncationCheck() local
3923 SelectionDAG &DAG = DCI.DAG; in optimizeSetCCByHoistingAndByConstFromLogicalShift() local
3995 SelectionDAG &DAG = DCI.DAG; in foldSetCCWithBinOp() local
4205 SelectionDAG &DAG = DCI.DAG; in SimplifySetCC() local
6247 SelectionDAG &DAG = DCI.DAG; in prepareUREMEqFold() local
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H A DSelectionDAGBuilder.cpp2428 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), in visitBr()
3071 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), in visitCallBr()
3109 DAG.getCopyFromReg(DAG.getEntryNode(), dl, in visitLandingPad()
3117 DAG.getCopyFromReg(DAG.getEntryNode(), dl, in visitLandingPad()
3157 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(), in visitIndirectBr()
3179 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot())); in visitUnreachable()
4414 SelectionDAG& DAG = SDB->DAG; in getUniformBase() local
6241 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl, in visitIntrinsicCall()
6858 DAG.setRoot(DAG.getNode( in visitIntrinsicCall()
9557 SelectionDAG &DAG = Builder.DAG; in addStackMapLiveVars() local
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H A DLegalizeIntegerTypes.cpp509 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), in PromoteIntRes_BSWAP()
579 return DAG.getNode( in PromoteIntRes_CTLZ()
821 SDValue Res = DAG.getMaskedGather(DAG.getVTList(NVT, MVT::Other), in PromoteIntRes_MGATHER()
845 SDValue Res = DAG.getNode(N->getOpcode(), dl, DAG.getVTList(VT, SVT), in PromoteIntRes_Overflow()
1558 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(), in PromoteIntRes_UNDEF()
3024 Carry = DAG.getSelect(dl, NVT, Cmp, DAG.getConstant(1, dl, NVT), in ExpandIntRes_ADDSUB()
3039 Borrow = DAG.getSelect(dl, NVT, Cmp, DAG.getConstant(1, dl, NVT), in ExpandIntRes_ADDSUB()
4315 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops); in ExpandIntRes_Shift()
4381 Hi = DAG.getNode( in ExpandIntRes_SIGN_EXTEND()
4564 DAG.getStore(DAG.getEntryNode(), dl, DAG.getConstant(0, dl, PtrVT), Temp, in ExpandIntRes_XMULO()
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H A DLegalizeTypesGeneric.cpp63 auto &DL = DAG.getDataLayout(); in ExpandRes_BITCAST()
139 Vals.push_back(DAG.getNode( in ExpandRes_BITCAST()
171 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, StackPtr, PtrInfo); in ExpandRes_BITCAST()
229 SDValue NewVec = DAG.getNode( in ExpandRes_EXTRACT_VECTOR_ELT()
243 if (DAG.getDataLayout().isBigEndian()) in ExpandRes_EXTRACT_VECTOR_ELT()
269 Hi = DAG.getLoad( in ExpandRes_NormalLoad()
427 if (DAG.getDataLayout().isBigEndian()) in ExpandOp_INSERT_VECTOR_ELT()
433 Idx = DAG.getNode(ISD::ADD, dl, in ExpandOp_INSERT_VECTOR_ELT()
483 Hi = DAG.getStore( in ExpandOp_NormalStore()
570 Lo = DAG.getUNDEF(LoVT); in SplitRes_UNDEF()
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H A DLegalizeDAG.cpp88 SelectionDAG &DAG; member in __anond6e4589b0111::SelectionDAGLegalize
98 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); in getSetCCResultType()
107 : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG), in SelectionDAGLegalize()
329 DAG.getConstantPool(LLVMC, TLI.getPointerTy(DAG.getDataLayout())); in ExpandConstantFP()
1406 Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, in ExpandExtractFromVectorThroughStack()
1465 Ch = DAG.getStore( in ExpandInsertToVectorThroughStack()
1511 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl, in ExpandVectorBuildThroughStack()
1797 return DAG.getLoad( in ExpandSCALAR_TO_VECTOR()
1963 DAG.getConstantPool(CP, TLI.getPointerTy(DAG.getDataLayout())); in ExpandBUILD_VECTOR()
2739 DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()))); in ExpandNode()
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/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h515 bool isReassocProfitable(SelectionDAG &DAG, SDValue N0,
797 SelectionDAG &DAG) const override;
952 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
955 SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const;
988 SelectionDAG &DAG) const override;
1023 SelectionDAG &DAG) const;
1053 SDValue LowerDIV(SDValue Op, SelectionDAG &DAG) const;
1054 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
1072 SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) const;
1095 SelectionDAG &DAG) const;
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H A DAArch64ISelLowering.cpp7125 SelectionDAG &DAG = CLI.DAG; in LowerCall() local
15978 SelectionDAG &DAG = DCI.DAG; in tryCombineToEXTR() local
16019 SelectionDAG &DAG = DCI.DAG; in tryCombineToBSL() local
16191 SelectionDAG &DAG = DCI.DAG; in performORCombine() local
16300 SelectionDAG &DAG = DCI.DAG; in performSVEAndCombine() local
16395 SelectionDAG &DAG = DCI.DAG; in performANDCombine() local
16502 SelectionDAG &DAG = DCI.DAG; in performFirstTrueTestVectorCombine() local
16539 SelectionDAG &DAG = DCI.DAG; in performLastTrueTestVectorCombine() local
16553 SelectionDAG &DAG = DCI.DAG; in performExtractVectorEltCombine() local
18012 SelectionDAG &DAG = DCI.DAG; in performIntrinsicCombine() local
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/openbsd/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp576 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); in LowerFormalArguments_32()
603 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); in LowerFormalArguments_32()
610 DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, MachinePointerInfo())); in LowerFormalArguments_32()
722 DAG.getStore(Chain, DL, VArg, DAG.getFrameIndex(FI, PtrVT), in LowerFormalArguments_64()
798 SelectionDAG &DAG = CLI.DAG; in LowerCall_32() local
1188 SelectionDAG &DAG = CLI.DAG; in LowerCall_64() local
2122 return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr, in makeAddress()
2693 DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(SP::I6, PtrVT), in LowerVASTART()
2719 return DAG.getLoad( in LowerVAARG()
2811 Chain = (depth || AlwaysFlush) ? getFLUSHW(Op, DAG) : DAG.getEntryNode(); in getFRAMEADDR()
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/openbsd/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsISelLowering.h385 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), in getAddrLocal()
388 DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, in getAddrLocal()
391 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, in getAddrLocal()
404 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), in getAddrGlobal()
420 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty)); in getAddrGlobalLargeGOT()
437 return DAG.getNode(ISD::ADD, DL, Ty, in getAddrNonPIC()
456 DAG.getNode(MipsISD::Highest, DL, Ty, in getAddrNonPICSym64()
460 DAG.getNode(ISD::ADD, DL, Ty, Highest, in getAddrNonPICSym64()
468 return DAG.getNode(ISD::ADD, DL, Ty, Shift2, in getAddrNonPICSym64()
480 return DAG.getNode( in getAddrGPRel()
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/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp4405 SelectionDAG &DAG = CLI.DAG; in LowerCall() local
7191 return DAG.getVectorShuffle(VT, dl, DAG.getBitcast(VT, LHS), in getPack()
13213 SDValue Ops[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT)}; in lowerShuffleAsUNPCKAndPermute()
18888 SDValue Ops[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT)}; in lowerV4X128Shuffle()
19612 return DAG.getSetCC(DL, VT, DAG.getConstant(0, DL, ExtVT), in lower1BitShuffle()
20839 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl), in LowerToTLSExecModel()
27933 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), in LowerINTRINSIC_WO_CHAIN()
28733 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), in LowerRETURNADDR()
28740 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI, in LowerRETURNADDR()
50177 auto IsZExtLike = [DAG = &DAG, ScalarVT](SDValue V) { in detectAVGPattern()
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H A DX86SelectionDAGInfo.cpp43 DAG.getSubtarget().getRegisterInfo()); in isBaseRegConflictPossible()
59 assert(!isBaseRegConflictPossible(DAG, ClobberSet)); in EmitTargetCodeForMemset()
103 Count = DAG.getIntPtrConstant(SizeVal, dl); in EmitTargetCodeForMemset()
112 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT), in EmitTargetCodeForMemset()
117 Count = DAG.getIntPtrConstant(SizeVal, dl); in EmitTargetCodeForMemset()
141 DAG.getMemset(Chain, dl, in EmitTargetCodeForMemset()
172 return DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops); in emitRepmovs()
250 Results.push_back(DAG.getMemcpy( in emitConstantSizeRepmov()
252 DAG.getNode(ISD::ADD, dl, DstVT, Dst, DAG.getConstant(Offset, dl, DstVT)), in emitConstantSizeRepmov()
253 DAG.getNode(ISD::ADD, dl, SrcVT, Src, DAG.getConstant(Offset, dl, SrcVT)), in emitConstantSizeRepmov()
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/openbsd/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp302 DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo()); in lowerFRAMEADDR()
327 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, GRLenVT); in lowerRETURNADDR()
335 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); in lowerEH_DWARF_CFA()
633 return DAG.getMergeValues({DAG.getUNDEF(Op.getValueType()), Op0}, DL); in lowerINTRINSIC_W_CHAIN()
671 {DAG.getNode( in lowerINTRINSIC_W_CHAIN()
679 return DAG.getMergeValues({DAG.getUNDEF(Op.getValueType()), Op0}, DL); in lowerINTRINSIC_W_CHAIN()
704 return DAG.getMergeValues({DAG.getUNDEF(Op.getValueType()), Op0}, DL); in lowerINTRINSIC_W_CHAIN()
813 return DAG.getNode( in lowerINTRINSIC_VOID()
1270 DAG.getNode( in ReplaceNodeResults()
1665 SelectionDAG &DAG = DCI.DAG; in PerformDAGCombine() local
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/openbsd/gnu/llvm/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp249 return DAG.getMemcpy( in CreateCopyOfByValArgument()
456 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); in LowerMemArgument()
487 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), in LowerMemOpCallTo()
492 return DAG.getStore( in LowerMemOpCallTo()
503 SelectionDAG &DAG = CLI.DAG; in LowerCall() local
540 DAG); in LowerCall()
718 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); in LowerCall()
1130 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout()))); in LowerReturn()
2587 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result, in LowerExternalSymbol()
2652 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result, in LowerGlobalAddress()
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/openbsd/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp3402 bool SwapOps = DAG.isSplatValue(V2) && !DAG.isSplatValue(V1); in lowerVECTOR_SHUFFLE()
4765 return DAG.getLoad(VT, DL, DAG.getEntryNode(), in lowerRETURNADDR()
4773 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, XLenVT); in lowerRETURNADDR()
5678 DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, DAG.getUNDEF(VT), in LowerINTRINSIC_WO_CHAIN()
8809 SelectionDAG &DAG = DCI.DAG; in performANDCombine() local
8847 SelectionDAG &DAG = DCI.DAG; in performORCombine() local
9465 SelectionDAG &DAG = DCI.DAG; in combineBinOp_VLToVWBinOp_VL() local
9562 SelectionDAG &DAG = DCI.DAG; in performFP_TO_INTCombine() local
9655 SelectionDAG &DAG = DCI.DAG; in performFP_TO_INT_SATCombine() local
10085 SelectionDAG &DAG = DCI.DAG; in PerformDAGCombine() local
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/openbsd/gnu/llvm/llvm/lib/CodeGen/
H A DMacroFusion.cpp92 DAG.dumpNodeName(SecondSU); dbgs() << " / "; in fuseInstructionPair()
98 if (&SecondSU != &DAG.ExitSU) in fuseInstructionPair()
111 if (&FirstSU != &DAG.EntrySU) { in fuseInstructionPair()
123 if (&SecondSU == &DAG.ExitSU) { in fuseInstructionPair()
124 for (SUnit &SU : DAG.SUnits) { in fuseInstructionPair()
153 void MacroFusion::apply(ScheduleDAGInstrs *DAG) { in apply() argument
157 for (SUnit &ISU : DAG->SUnits) in apply()
158 scheduleAdjacentImpl(*DAG, ISU); in apply()
160 if (DAG->ExitSU.getInstr()) in apply()
162 scheduleAdjacentImpl(*DAG, DAG->ExitSU); in apply()
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1234567891011