1 /* Definitions for the Blackfin port. 2 Copyright (C) 2005 Free Software Foundation, Inc. 3 Contributed by Analog Devices. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 2, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING. If not, write to 19 the Free Software Foundation, 51 Franklin Street, Fifth Floor, 20 Boston, MA 02110-1301, USA. */ 21 22 #ifndef _BFIN_CONFIG 23 #define _BFIN_CONFIG 24 25 #define OBJECT_FORMAT_ELF 26 27 #define BRT 1 28 #define BRF 0 29 30 /* Print subsidiary information on the compiler version in use. */ 31 #define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)") 32 33 /* Run-time compilation parameters selecting different hardware subsets. */ 34 35 extern int target_flags; 36 37 /* Predefinition in the preprocessor for this target machine */ 38 #ifndef TARGET_CPU_CPP_BUILTINS 39 #define TARGET_CPU_CPP_BUILTINS() \ 40 do \ 41 { \ 42 builtin_define_std ("bfin"); \ 43 builtin_define_std ("BFIN"); \ 44 builtin_define ("__ADSPBLACKFIN__"); \ 45 if (TARGET_FDPIC) \ 46 builtin_define ("__BFIN_FDPIC__"); \ 47 if (TARGET_ID_SHARED_LIBRARY) \ 48 builtin_define ("__ID_SHARED_LIB__"); \ 49 } \ 50 while (0) 51 #endif 52 53 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\ 54 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\ 55 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \ 56 " 57 #ifndef SUBTARGET_DRIVER_SELF_SPECS 58 # define SUBTARGET_DRIVER_SELF_SPECS 59 #endif 60 61 #define LINK_GCC_C_SEQUENCE_SPEC \ 62 "%{mfdpic:%{!static: %L} %{static: %G %L %G}} \ 63 %{!mfdpic:%G %L %G}" 64 65 /* A C string constant that tells the GCC driver program options to pass to 66 the assembler. It can also specify how to translate options you give to GNU 67 CC into options for GCC to pass to the assembler. See the file `sun3.h' 68 for an example of this. 69 70 Do not define this macro if it does not need to do anything. 71 72 Defined in svr4.h. */ 73 #undef ASM_SPEC 74 #define ASM_SPEC "\ 75 %{G*} %{v} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} \ 76 %{mno-fdpic:-mnopic} %{mfdpic}" 77 78 #define LINK_SPEC "\ 79 %{h*} %{v:-V} \ 80 %{b} \ 81 %{mfdpic:-melf32bfinfd -z text} \ 82 %{static:-dn -Bstatic} \ 83 %{shared:-G -Bdynamic} \ 84 %{symbolic:-Bsymbolic} \ 85 %{G*} \ 86 %{YP,*} \ 87 %{Qy:} %{!Qn:-Qy} \ 88 -init __init -fini __fini " 89 90 /* Generate DSP instructions, like DSP halfword loads */ 91 #define TARGET_DSP (1) 92 93 #define TARGET_DEFAULT (MASK_SPECLD_ANOMALY | MASK_CSYNC_ANOMALY) 94 95 /* Maximum number of library ids we permit */ 96 #define MAX_LIBRARY_ID 255 97 98 extern const char *bfin_library_id_string; 99 100 /* Sometimes certain combinations of command options do not make 101 sense on a particular target machine. You can define a macro 102 `OVERRIDE_OPTIONS' to take account of this. This macro, if 103 defined, is executed once just after all the command options have 104 been parsed. 105 106 Don't use this macro to turn on various extra optimizations for 107 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 108 109 #define OVERRIDE_OPTIONS override_options () 110 111 #define FUNCTION_MODE SImode 112 #define Pmode SImode 113 114 /* store-condition-codes instructions store 0 for false 115 This is the value stored for true. */ 116 #define STORE_FLAG_VALUE 1 117 118 /* Define this if pushing a word on the stack 119 makes the stack pointer a smaller address. */ 120 #define STACK_GROWS_DOWNWARD 121 122 #define STACK_PUSH_CODE PRE_DEC 123 124 /* Define this to nonzero if the nominal address of the stack frame 125 is at the high-address end of the local variables; 126 that is, each additional local variable allocated 127 goes at a more negative offset in the frame. */ 128 #define FRAME_GROWS_DOWNWARD 1 129 130 /* We define a dummy ARGP register; the parameters start at offset 0 from 131 it. */ 132 #define FIRST_PARM_OFFSET(DECL) 0 133 134 /* Offset within stack frame to start allocating local variables at. 135 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 136 first local allocated. Otherwise, it is the offset to the BEGINNING 137 of the first local allocated. */ 138 #define STARTING_FRAME_OFFSET 0 139 140 /* Register to use for pushing function arguments. */ 141 #define STACK_POINTER_REGNUM REG_P6 142 143 /* Base register for access to local variables of the function. */ 144 #define FRAME_POINTER_REGNUM REG_P7 145 146 /* A dummy register that will be eliminated to either FP or SP. */ 147 #define ARG_POINTER_REGNUM REG_ARGP 148 149 /* `PIC_OFFSET_TABLE_REGNUM' 150 The register number of the register used to address a table of 151 static data addresses in memory. In some cases this register is 152 defined by a processor's "application binary interface" (ABI). 153 When this macro is defined, RTL is generated for this register 154 once, as with the stack pointer and frame pointer registers. If 155 this macro is not defined, it is up to the machine-dependent files 156 to allocate such a register (if necessary). */ 157 #define PIC_OFFSET_TABLE_REGNUM (REG_P5) 158 159 #define FDPIC_FPTR_REGNO REG_P1 160 #define FDPIC_REGNO REG_P3 161 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO) 162 163 /* A static chain register for nested functions. We need to use a 164 call-clobbered register for this. */ 165 #define STATIC_CHAIN_REGNUM REG_P2 166 167 /* Define this if functions should assume that stack space has been 168 allocated for arguments even when their values are passed in 169 registers. 170 171 The value of this macro is the size, in bytes, of the area reserved for 172 arguments passed in registers. 173 174 This space can either be allocated by the caller or be a part of the 175 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' 176 says which. */ 177 #define FIXED_STACK_AREA 12 178 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA 179 180 /* Define this if the above stack space is to be considered part of the 181 * space allocated by the caller. */ 182 #define OUTGOING_REG_PARM_STACK_SPACE 183 184 /* Define this if the maximum size of all the outgoing args is to be 185 accumulated and pushed during the prologue. The amount can be 186 found in the variable current_function_outgoing_args_size. */ 187 #define ACCUMULATE_OUTGOING_ARGS 1 188 189 /* Value should be nonzero if functions must have frame pointers. 190 Zero means the frame pointer need not be set up (and parms 191 may be accessed via the stack pointer) in functions that seem suitable. 192 This is computed in `reload', in reload1.c. 193 */ 194 #define FRAME_POINTER_REQUIRED (bfin_frame_pointer_required ()) 195 196 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */ 197 198 /* Make strings word-aligned so strcpy from constants will be faster. */ 199 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 200 (TREE_CODE (EXP) == STRING_CST \ 201 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 202 203 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18) 204 #define TRAMPOLINE_TEMPLATE(FILE) \ 205 if (TARGET_FDPIC) \ 206 { \ 207 fprintf(FILE, "\t.dd\t0x00000000\n"); /* 0 */ \ 208 fprintf(FILE, "\t.dd\t0x00000000\n"); /* 0 */ \ 209 fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \ 210 fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ \ 211 fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ \ 212 fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ \ 213 fprintf(FILE, "\t.dw\t0xac4b\n"); /* p3 = [p1 + 4] */ \ 214 fprintf(FILE, "\t.dw\t0x9149\n"); /* p1 = [p1] */ \ 215 fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ \ 216 } \ 217 else \ 218 { \ 219 fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \ 220 fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ \ 221 fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ \ 222 fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ \ 223 fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ \ 224 } 225 226 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 227 initialize_trampoline (TRAMP, FNADDR, CXT) 228 229 /* Definitions for register eliminations. 230 231 This is an array of structures. Each structure initializes one pair 232 of eliminable registers. The "from" register number is given first, 233 followed by "to". Eliminations of the same "from" register are listed 234 in order of preference. 235 236 There are two registers that can always be eliminated on the i386. 237 The frame pointer and the arg pointer can be replaced by either the 238 hard frame pointer or to the stack pointer, depending upon the 239 circumstances. The hard frame pointer is not used before reload and 240 so it is not eligible for elimination. */ 241 242 #define ELIMINABLE_REGS \ 243 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 244 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ 245 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \ 246 247 /* Given FROM and TO register numbers, say whether this elimination is 248 allowed. Frame pointer elimination is automatically handled. 249 250 All other eliminations are valid. */ 251 252 #define CAN_ELIMINATE(FROM, TO) \ 253 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) 254 255 /* Define the offset between two registers, one to be eliminated, and the other 256 its replacement, at the start of a routine. */ 257 258 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 259 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO))) 260 261 /* This processor has 262 8 data register for doing arithmetic 263 8 pointer register for doing addressing, including 264 1 stack pointer P6 265 1 frame pointer P7 266 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3) 267 1 condition code flag register CC 268 5 return address registers RETS/I/X/N/E 269 1 arithmetic status register (ASTAT). */ 270 271 #define FIRST_PSEUDO_REGISTER 50 272 273 #define D_REGNO_P(X) ((X) <= REG_R7) 274 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7) 275 #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3) 276 #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X)) 277 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3) 278 #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X))) 279 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X))) 280 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X))) 281 #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X))) 282 283 #define REGISTER_NAMES { \ 284 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \ 285 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \ 286 "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \ 287 "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \ 288 "A0", "A1", \ 289 "CC", \ 290 "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \ 291 "ARGP", \ 292 "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \ 293 } 294 295 #define SHORT_REGISTER_NAMES { \ 296 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \ 297 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \ 298 "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \ 299 "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", } 300 301 #define HIGH_REGISTER_NAMES { \ 302 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \ 303 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \ 304 "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \ 305 "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", } 306 307 #define DREGS_PAIR_NAMES { \ 308 "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, } 309 310 #define BYTE_REGISTER_NAMES { \ 311 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", } 312 313 314 /* 1 for registers that have pervasive standard uses 315 and are not available for the register allocator. */ 316 317 #define FIXED_REGISTERS \ 318 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \ 319 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ 320 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \ 321 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \ 322 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \ 323 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 324 /*lb0/1 */ \ 325 1, 1 \ 326 } 327 328 /* 1 for registers not available across function calls. 329 These must include the FIXED_REGISTERS and also any 330 registers that can be used without being saved. 331 The latter must include the registers where values are returned 332 and the register where structure-value addresses are passed. 333 Aside from that, you can include as many other registers as you like. */ 334 335 #define CALL_USED_REGISTERS \ 336 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \ 337 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \ 338 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \ 339 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 340 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \ 341 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 342 /*lb0/1 */ \ 343 1, 1 \ 344 } 345 346 /* Order in which to allocate registers. Each register must be 347 listed once, even those in FIXED_REGISTERS. List frame pointer 348 late and fixed registers last. Note that, in general, we prefer 349 registers listed in CALL_USED_REGISTERS, keeping the others 350 available for storage of persistent values. */ 351 352 #define REG_ALLOC_ORDER \ 353 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \ 354 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \ 355 REG_A0, REG_A1, \ 356 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \ 357 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \ 358 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \ 359 REG_ASTAT, REG_SEQSTAT, REG_USP, \ 360 REG_CC, REG_ARGP, \ 361 REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \ 362 } 363 364 /* Macro to conditionally modify fixed_regs/call_used_regs. */ 365 #define CONDITIONAL_REGISTER_USAGE \ 366 { \ 367 conditional_register_usage(); \ 368 if (TARGET_FDPIC) \ 369 call_used_regs[FDPIC_REGNO] = 1; \ 370 if (!TARGET_FDPIC && flag_pic) \ 371 { \ 372 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 373 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 374 } \ 375 } 376 377 /* Define the classes of registers for register constraints in the 378 machine description. Also define ranges of constants. 379 380 One of the classes must always be named ALL_REGS and include all hard regs. 381 If there is more than one class, another class must be named NO_REGS 382 and contain no registers. 383 384 The name GENERAL_REGS must be the name of a class (or an alias for 385 another name such as ALL_REGS). This is the class of registers 386 that is allowed by "g" or "r" in a register constraint. 387 Also, registers outside this class are allocated only when 388 instructions express preferences for them. 389 390 The classes must be numbered in nondecreasing order; that is, 391 a larger-numbered class must never be contained completely 392 in a smaller-numbered class. 393 394 For any two classes, it is very desirable that there be another 395 class that represents their union. */ 396 397 398 enum reg_class 399 { 400 NO_REGS, 401 IREGS, 402 BREGS, 403 LREGS, 404 MREGS, 405 CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */ 406 DAGREGS, 407 EVEN_AREGS, 408 ODD_AREGS, 409 AREGS, 410 CCREGS, 411 EVEN_DREGS, 412 ODD_DREGS, 413 DREGS, 414 FDPIC_REGS, 415 FDPIC_FPTR_REGS, 416 PREGS_CLOBBERED, 417 PREGS, 418 IPREGS, 419 DPREGS, 420 MOST_REGS, 421 LT_REGS, 422 LC_REGS, 423 LB_REGS, 424 PROLOGUE_REGS, 425 NON_A_CC_REGS, 426 ALL_REGS, LIM_REG_CLASSES 427 }; 428 429 #define N_REG_CLASSES ((int)LIM_REG_CLASSES) 430 431 #define GENERAL_REGS DPREGS 432 433 /* Give names of register classes as strings for dump file. */ 434 435 #define REG_CLASS_NAMES \ 436 { "NO_REGS", \ 437 "IREGS", \ 438 "BREGS", \ 439 "LREGS", \ 440 "MREGS", \ 441 "CIRCREGS", \ 442 "DAGREGS", \ 443 "EVEN_AREGS", \ 444 "ODD_AREGS", \ 445 "AREGS", \ 446 "CCREGS", \ 447 "EVEN_DREGS", \ 448 "ODD_DREGS", \ 449 "DREGS", \ 450 "FDPIC_REGS", \ 451 "FDPIC_FPTR_REGS", \ 452 "PREGS_CLOBBERED", \ 453 "PREGS", \ 454 "IPREGS", \ 455 "DPREGS", \ 456 "MOST_REGS", \ 457 "LT_REGS", \ 458 "LC_REGS", \ 459 "LB_REGS", \ 460 "PROLOGUE_REGS", \ 461 "NON_A_CC_REGS", \ 462 "ALL_REGS" } 463 464 /* An initializer containing the contents of the register classes, as integers 465 which are bit masks. The Nth integer specifies the contents of class N. 466 The way the integer MASK is interpreted is that register R is in the class 467 if `MASK & (1 << R)' is 1. 468 469 When the machine has more than 32 registers, an integer does not suffice. 470 Then the integers are replaced by sub-initializers, braced groupings 471 containing several integers. Each sub-initializer must be suitable as an 472 initializer for the type `HARD_REG_SET' which is defined in 473 `hard-reg-set.h'. */ 474 475 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use 476 MOST_REGS as the union of DPREGS and DAGREGS. */ 477 478 #define REG_CLASS_CONTENTS \ 479 /* 31 - 0 63-32 */ \ 480 { { 0x00000000, 0 }, /* NO_REGS */ \ 481 { 0x000f0000, 0 }, /* IREGS */ \ 482 { 0x00f00000, 0 }, /* BREGS */ \ 483 { 0x0f000000, 0 }, /* LREGS */ \ 484 { 0xf0000000, 0 }, /* MREGS */ \ 485 { 0x0fff0000, 0 }, /* CIRCREGS */ \ 486 { 0xffff0000, 0 }, /* DAGREGS */ \ 487 { 0x00000000, 0x1 }, /* EVEN_AREGS */ \ 488 { 0x00000000, 0x2 }, /* ODD_AREGS */ \ 489 { 0x00000000, 0x3 }, /* AREGS */ \ 490 { 0x00000000, 0x4 }, /* CCREGS */ \ 491 { 0x00000055, 0 }, /* EVEN_DREGS */ \ 492 { 0x000000aa, 0 }, /* ODD_DREGS */ \ 493 { 0x000000ff, 0 }, /* DREGS */ \ 494 { 0x00000800, 0x000 }, /* FDPIC_REGS */ \ 495 { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \ 496 { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \ 497 { 0x0000ff00, 0x800 }, /* PREGS */ \ 498 { 0x000fff00, 0x800 }, /* IPREGS */ \ 499 { 0x0000ffff, 0x800 }, /* DPREGS */ \ 500 { 0xffffffff, 0x800 }, /* MOST_REGS */\ 501 { 0x00000000, 0x3000 }, /* LT_REGS */\ 502 { 0x00000000, 0xc000 }, /* LC_REGS */\ 503 { 0x00000000, 0x30000 }, /* LB_REGS */\ 504 { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\ 505 { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\ 506 { 0xffffffff, 0x3ffff }} /* ALL_REGS */ 507 508 #define IREG_POSSIBLE_P(OUTER) \ 509 ((OUTER) == POST_INC || (OUTER) == PRE_INC \ 510 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \ 511 || (OUTER) == MEM || (OUTER) == ADDRESS) 512 513 #define MODE_CODE_BASE_REG_CLASS(MODE, OUTER, INDEX) \ 514 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS) 515 516 #define INDEX_REG_CLASS PREGS 517 518 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \ 519 (P_REGNO_P (X) || (X) == REG_ARGP \ 520 || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \ 521 && I_REGNO_P (X))) 522 523 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \ 524 ((X) >= FIRST_PSEUDO_REGISTER \ 525 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)) 526 527 #ifdef REG_OK_STRICT 528 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \ 529 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX) 530 #else 531 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \ 532 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX) 533 #endif 534 535 #define REGNO_OK_FOR_INDEX_P(X) 0 536 537 /* Get reg_class from a letter such as appears in the machine description. */ 538 539 #define REG_CLASS_FROM_LETTER(LETTER) \ 540 ((LETTER) == 'a' ? PREGS : \ 541 (LETTER) == 'Z' ? FDPIC_REGS : \ 542 (LETTER) == 'Y' ? FDPIC_FPTR_REGS : \ 543 (LETTER) == 'd' ? DREGS : \ 544 (LETTER) == 'z' ? PREGS_CLOBBERED : \ 545 (LETTER) == 'D' ? EVEN_DREGS : \ 546 (LETTER) == 'W' ? ODD_DREGS : \ 547 (LETTER) == 'e' ? AREGS : \ 548 (LETTER) == 'A' ? EVEN_AREGS : \ 549 (LETTER) == 'B' ? ODD_AREGS : \ 550 (LETTER) == 'b' ? IREGS : \ 551 (LETTER) == 'v' ? BREGS : \ 552 (LETTER) == 'f' ? MREGS : \ 553 (LETTER) == 'c' ? CIRCREGS : \ 554 (LETTER) == 'C' ? CCREGS : \ 555 (LETTER) == 't' ? LT_REGS : \ 556 (LETTER) == 'k' ? LC_REGS : \ 557 (LETTER) == 'u' ? LB_REGS : \ 558 (LETTER) == 'x' ? MOST_REGS : \ 559 (LETTER) == 'y' ? PROLOGUE_REGS : \ 560 (LETTER) == 'w' ? NON_A_CC_REGS : \ 561 NO_REGS) 562 563 /* The same information, inverted: 564 Return the class number of the smallest class containing 565 reg number REGNO. This could be a conditional expression 566 or could index an array. */ 567 568 #define REGNO_REG_CLASS(REGNO) \ 569 ((REGNO) < REG_P0 ? DREGS \ 570 : (REGNO) < REG_I0 ? PREGS \ 571 : (REGNO) == REG_ARGP ? PREGS \ 572 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \ 573 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \ 574 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \ 575 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \ 576 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \ 577 : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \ 578 : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \ 579 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \ 580 : (REGNO) == REG_CC ? CCREGS \ 581 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \ 582 : NO_REGS) 583 584 /* When defined, the compiler allows registers explicitly used in the 585 rtl to be used as spill registers but prevents the compiler from 586 extending the lifetime of these registers. */ 587 #define SMALL_REGISTER_CLASSES 1 588 589 #define CLASS_LIKELY_SPILLED_P(CLASS) \ 590 ((CLASS) == PREGS_CLOBBERED \ 591 || (CLASS) == PROLOGUE_REGS \ 592 || (CLASS) == CCREGS) 593 594 /* Do not allow to store a value in REG_CC for any mode */ 595 /* Do not allow to store value in pregs if mode is not SI*/ 596 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE)) 597 598 /* Return the maximum number of consecutive registers 599 needed to represent mode MODE in a register of class CLASS. */ 600 #define CLASS_MAX_NREGS(CLASS, MODE) \ 601 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \ 602 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 603 604 #define HARD_REGNO_NREGS(REGNO, MODE) \ 605 ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \ 606 : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \ 607 : CLASS_MAX_NREGS (GENERAL_REGS, MODE)) 608 609 /* A C expression that is nonzero if hard register TO can be 610 considered for use as a rename register for FROM register */ 611 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO) 612 613 /* A C expression that is nonzero if it is desirable to choose 614 register allocation so as to avoid move instructions between a 615 value of mode MODE1 and a value of mode MODE2. 616 617 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, 618 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1, 619 MODE2)' must be zero. */ 620 #define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) == (MODE2)) 621 622 /* `PREFERRED_RELOAD_CLASS (X, CLASS)' 623 A C expression that places additional restrictions on the register 624 class to use when it is necessary to copy value X into a register 625 in class CLASS. The value is a register class; perhaps CLASS, or 626 perhaps another, smaller class. */ 627 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS) 628 629 /* Function Calling Conventions. */ 630 631 /* The type of the current function; normal functions are of type 632 SUBROUTINE. */ 633 typedef enum { 634 SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER 635 } e_funkind; 636 637 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 } 638 639 /* Flags for the call/call_value rtl operations set up by function_arg */ 640 #define CALL_NORMAL 0x00000000 /* no special processing */ 641 #define CALL_LONG 0x00000001 /* always call indirect */ 642 #define CALL_SHORT 0x00000002 /* always call by symbol */ 643 644 typedef struct { 645 int words; /* # words passed so far */ 646 int nregs; /* # registers available for passing */ 647 int *arg_regs; /* array of register -1 terminated */ 648 int call_cookie; /* Do special things for this call */ 649 } CUMULATIVE_ARGS; 650 651 /* Define where to put the arguments to a function. 652 Value is zero to push the argument on the stack, 653 or a hard register in which to store the argument. 654 655 MODE is the argument's machine mode. 656 TYPE is the data type of the argument (as a tree). 657 This is null for libcalls where that information may 658 not be available. 659 CUM is a variable of type CUMULATIVE_ARGS which gives info about 660 the preceding args and about the function being called. 661 NAMED is nonzero if this argument is a named parameter 662 (otherwise it is an extra parameter matching an ellipsis). */ 663 664 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 665 (function_arg (&CUM, MODE, TYPE, NAMED)) 666 667 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO) 668 669 670 /* Initialize a variable CUM of type CUMULATIVE_ARGS 671 for a call to a function whose data type is FNTYPE. 672 For a library call, FNTYPE is 0. */ 673 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \ 674 (init_cumulative_args (&CUM, FNTYPE, LIBNAME)) 675 676 /* Update the data in CUM to advance over an argument 677 of mode MODE and data type TYPE. 678 (TYPE is null for libcalls where that information may not be available.) */ 679 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 680 (function_arg_advance (&CUM, MODE, TYPE, NAMED)) 681 682 #define RETURN_POPS_ARGS(FDECL, FUNTYPE, STKSIZE) 0 683 684 /* Define how to find the value returned by a function. 685 VALTYPE is the data type of the value (as a tree). 686 If the precise function being called is known, FUNC is its FUNCTION_DECL; 687 otherwise, FUNC is 0. 688 */ 689 690 #define VALUE_REGNO(MODE) (REG_R0) 691 692 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 693 gen_rtx_REG (TYPE_MODE (VALTYPE), \ 694 VALUE_REGNO(TYPE_MODE(VALTYPE))) 695 696 /* Define how to find the value returned by a library function 697 assuming the value has mode MODE. */ 698 699 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE)) 700 701 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0) 702 703 #define DEFAULT_PCC_STRUCT_RETURN 0 704 #define RETURN_IN_MEMORY(TYPE) bfin_return_in_memory(TYPE) 705 706 /* Before the prologue, the return address is in the RETS register. */ 707 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS) 708 709 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT) 710 711 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS) 712 713 /* Call instructions don't modify the stack pointer on the Blackfin. */ 714 #define INCOMING_FRAME_SP_OFFSET 0 715 716 /* Describe how we implement __builtin_eh_return. */ 717 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 718 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2) 719 #define EH_RETURN_HANDLER_RTX \ 720 gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD)) 721 722 /* Addressing Modes */ 723 724 /* Recognize any constant value that is a valid address. */ 725 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X)) 726 727 /* Nonzero if the constant value X is a legitimate general operand. 728 symbol_ref are not legitimate and will be put into constant pool. 729 See force_const_mem(). 730 If -mno-pool, all constants are legitimate. 731 */ 732 #define LEGITIMATE_CONSTANT_P(x) 1 733 734 /* A number, the maximum number of registers that can appear in a 735 valid memory address. Note that it is up to you to specify a 736 value equal to the maximum number that `GO_IF_LEGITIMATE_ADDRESS' 737 would ever accept. */ 738 #define MAX_REGS_PER_ADDRESS 1 739 740 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 741 that is a valid memory address for an instruction. 742 The MODE argument is the machine mode for the MEM expression 743 that wants to use this address. 744 745 Blackfin addressing modes are as follows: 746 747 [preg] 748 [preg + imm16] 749 750 B [ Preg + uimm15 ] 751 W [ Preg + uimm16m2 ] 752 [ Preg + uimm17m4 ] 753 754 [preg++] 755 [preg--] 756 [--sp] 757 */ 758 759 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \ 760 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode) 761 762 #ifdef REG_OK_STRICT 763 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ 764 do { \ 765 if (bfin_legitimate_address_p (MODE, X, 1)) \ 766 goto WIN; \ 767 } while (0); 768 #else 769 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ 770 do { \ 771 if (bfin_legitimate_address_p (MODE, X, 0)) \ 772 goto WIN; \ 773 } while (0); 774 #endif 775 776 /* Try machine-dependent ways of modifying an illegitimate address 777 to be legitimate. If we find one, return the new, valid address. 778 This macro is used in only one place: `memory_address' in explow.c. 779 780 OLDX is the address as it was before break_out_memory_refs was called. 781 In some cases it is useful to look at this to decide what needs to be done. 782 783 MODE and WIN are passed so that this macro can use 784 GO_IF_LEGITIMATE_ADDRESS. 785 786 It is always safe for this macro to do nothing. It exists to recognize 787 opportunities to optimize the output. 788 */ 789 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 790 do { \ 791 rtx _q = legitimize_address(X, OLDX, MODE); \ 792 if (_q) { X = _q; goto WIN; } \ 793 } while (0) 794 795 #define HAVE_POST_INCREMENT 1 796 #define HAVE_POST_DECREMENT 1 797 #define HAVE_PRE_DECREMENT 1 798 799 /* `LEGITIMATE_PIC_OPERAND_P (X)' 800 A C expression that is nonzero if X is a legitimate immediate 801 operand on the target machine when generating position independent 802 code. You can assume that X satisfies `CONSTANT_P', so you need 803 not check this. You can also assume FLAG_PIC is true, so you need 804 not check it either. You need not define this macro if all 805 constants (including `SYMBOL_REF') can be immediate operands when 806 generating position independent code. */ 807 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X) 808 809 #define SYMBOLIC_CONST(X) \ 810 (GET_CODE (X) == SYMBOL_REF \ 811 || GET_CODE (X) == LABEL_REF \ 812 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 813 814 /* 815 A C statement or compound statement with a conditional `goto 816 LABEL;' executed if memory address X (an RTX) can have different 817 meanings depending on the machine mode of the memory reference it 818 is used for or if the address is valid for some modes but not 819 others. 820 821 Autoincrement and autodecrement addresses typically have 822 mode-dependent effects because the amount of the increment or 823 decrement is the size of the operand being addressed. Some 824 machines have other mode-dependent addresses. Many RISC machines 825 have no mode-dependent addresses. 826 827 You may assume that ADDR is a valid address for the machine. 828 */ 829 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 830 do { \ 831 if (GET_CODE (ADDR) == POST_INC \ 832 || GET_CODE (ADDR) == POST_DEC \ 833 || GET_CODE (ADDR) == PRE_DEC) \ 834 goto LABEL; \ 835 } while (0) 836 837 #define NOTICE_UPDATE_CC(EXPR, INSN) 0 838 839 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 840 is done just by pretending it is already truncated. */ 841 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 842 843 /* Max number of bytes we can move from memory to memory 844 in one reasonably fast instruction. */ 845 #define MOVE_MAX UNITS_PER_WORD 846 847 848 /* STORAGE LAYOUT: target machine storage layout 849 Define this macro as a C expression which is nonzero if accessing 850 less than a word of memory (i.e. a `char' or a `short') is no 851 faster than accessing a word of memory, i.e., if such access 852 require more than one instruction or if there is no difference in 853 cost between byte and (aligned) word loads. 854 855 When this macro is not defined, the compiler will access a field by 856 finding the smallest containing object; when it is defined, a 857 fullword load will be used if alignment permits. Unless bytes 858 accesses are faster than word accesses, using word accesses is 859 preferable since it may eliminate subsequent memory access if 860 subsequent accesses occur to other fields in the same word of the 861 structure, but to different bytes. */ 862 #define SLOW_BYTE_ACCESS 0 863 #define SLOW_SHORT_ACCESS 0 864 865 /* Define this if most significant bit is lowest numbered 866 in instructions that operate on numbered bit-fields. */ 867 #define BITS_BIG_ENDIAN 0 868 869 /* Define this if most significant byte of a word is the lowest numbered. 870 We can't access bytes but if we could we would in the Big Endian order. */ 871 #define BYTES_BIG_ENDIAN 0 872 873 /* Define this if most significant word of a multiword number is numbered. */ 874 #define WORDS_BIG_ENDIAN 0 875 876 /* number of bits in an addressable storage unit */ 877 #define BITS_PER_UNIT 8 878 879 /* Width in bits of a "word", which is the contents of a machine register. 880 Note that this is not necessarily the width of data type `int'; 881 if using 16-bit ints on a 68000, this would still be 32. 882 But on a machine with 16-bit registers, this would be 16. */ 883 #define BITS_PER_WORD 32 884 885 /* Width of a word, in units (bytes). */ 886 #define UNITS_PER_WORD 4 887 888 /* Width in bits of a pointer. 889 See also the macro `Pmode1' defined below. */ 890 #define POINTER_SIZE 32 891 892 /* Allocation boundary (in *bits*) for storing pointers in memory. */ 893 #define POINTER_BOUNDARY 32 894 895 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 896 #define PARM_BOUNDARY 32 897 898 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 899 #define STACK_BOUNDARY 32 900 901 /* Allocation boundary (in *bits*) for the code of a function. */ 902 #define FUNCTION_BOUNDARY 32 903 904 /* Alignment of field after `int : 0' in a structure. */ 905 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 906 907 /* No data type wants to be aligned rounder than this. */ 908 #define BIGGEST_ALIGNMENT 32 909 910 /* Define this if move instructions will actually fail to work 911 when given unaligned data. */ 912 #define STRICT_ALIGNMENT 1 913 914 /* (shell-command "rm c-decl.o stor-layout.o") 915 * never define PCC_BITFIELD_TYPE_MATTERS 916 * really cause some alignment problem 917 */ 918 919 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \ 920 BITS_PER_UNIT) 921 922 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \ 923 BITS_PER_UNIT) 924 925 926 /* what is the 'type' of size_t */ 927 #define SIZE_TYPE "long unsigned int" 928 929 /* Define this as 1 if `char' should by default be signed; else as 0. */ 930 #define DEFAULT_SIGNED_CHAR 1 931 #define FLOAT_TYPE_SIZE BITS_PER_WORD 932 #define SHORT_TYPE_SIZE 16 933 #define CHAR_TYPE_SIZE 8 934 #define INT_TYPE_SIZE 32 935 #define LONG_TYPE_SIZE 32 936 #define LONG_LONG_TYPE_SIZE 64 937 938 /* Note: Fix this to depend on target switch. -- lev */ 939 940 /* Note: Try to implement double and force long double. -- tonyko 941 * #define __DOUBLES_ARE_FLOATS__ 942 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE 943 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE 944 * #define DOUBLES_ARE_FLOATS 1 945 */ 946 947 #define DOUBLE_TYPE_SIZE 64 948 #define LONG_DOUBLE_TYPE_SIZE 64 949 950 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)' 951 A macro to update M and UNSIGNEDP when an object whose type is 952 TYPE and which has the specified mode and signedness is to be 953 stored in a register. This macro is only called when TYPE is a 954 scalar type. 955 956 On most RISC machines, which only have operations that operate on 957 a full register, define this macro to set M to `word_mode' if M is 958 an integer mode narrower than `BITS_PER_WORD'. In most cases, 959 only integer modes should be widened because wider-precision 960 floating-point operations are usually more expensive than their 961 narrower counterparts. 962 963 For most machines, the macro definition does not change UNSIGNEDP. 964 However, some machines, have instructions that preferentially 965 handle either signed or unsigned quantities of certain modes. For 966 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add 967 instructions sign-extend the result to 64 bits. On such machines, 968 set UNSIGNEDP according to which kind of extension is more 969 efficient. 970 971 Do not define this macro if it would never modify M.*/ 972 973 #define BFIN_PROMOTE_MODE_P(MODE) \ 974 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \ 975 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) 976 977 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 978 if (BFIN_PROMOTE_MODE_P(MODE)) \ 979 { \ 980 if (MODE == QImode) \ 981 UNSIGNEDP = 1; \ 982 else if (MODE == HImode) \ 983 UNSIGNEDP = 0; \ 984 (MODE) = SImode; \ 985 } 986 987 /* Describing Relative Costs of Operations */ 988 989 /* Do not put function addr into constant pool */ 990 #define NO_FUNCTION_CSE 1 991 992 /* A C expression for the cost of moving data from a register in class FROM to 993 one in class TO. The classes are expressed using the enumeration values 994 such as `GENERAL_REGS'. A value of 2 is the default; other values are 995 interpreted relative to that. 996 997 It is not required that the cost always equal 2 when FROM is the same as TO; 998 on some machines it is expensive to move between registers if they are not 999 general registers. */ 1000 1001 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 1002 bfin_register_move_cost ((MODE), (CLASS1), (CLASS2)) 1003 1004 /* A C expression for the cost of moving data of mode M between a 1005 register and memory. A value of 2 is the default; this cost is 1006 relative to those in `REGISTER_MOVE_COST'. 1007 1008 If moving between registers and memory is more expensive than 1009 between two registers, you should define this macro to express the 1010 relative cost. */ 1011 1012 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \ 1013 bfin_memory_move_cost ((MODE), (CLASS), (IN)) 1014 1015 /* Specify the machine mode that this machine uses 1016 for the index in the tablejump instruction. */ 1017 #define CASE_VECTOR_MODE SImode 1018 1019 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic 1020 1021 /* Define if operations between registers always perform the operation 1022 on the full register even if a narrower mode is specified. 1023 #define WORD_REGISTER_OPERATIONS 1024 */ 1025 1026 #define CONST_18UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 262140) 1027 #define CONST_16BIT_IMM_P(VALUE) ((VALUE) >= -32768 && (VALUE) <= 32767) 1028 #define CONST_16UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 65535) 1029 #define CONST_7BIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 63) 1030 #define CONST_7NBIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 0) 1031 #define CONST_5UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 31) 1032 #define CONST_4BIT_IMM_P(VALUE) ((VALUE) >= -8 && (VALUE) <= 7) 1033 #define CONST_4UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 15) 1034 #define CONST_3BIT_IMM_P(VALUE) ((VALUE) >= -4 && (VALUE) <= 3) 1035 #define CONST_3UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 7) 1036 1037 #define CONSTRAINT_LEN(C, STR) \ 1038 ((C) == 'P' || (C) == 'M' || (C) == 'N' ? 2 \ 1039 : (C) == 'K' ? 3 \ 1040 : DEFAULT_CONSTRAINT_LEN ((C), (STR))) 1041 1042 #define CONST_OK_FOR_P(VALUE, STR) \ 1043 ((STR)[1] == '0' ? (VALUE) == 0 \ 1044 : (STR)[1] == '1' ? (VALUE) == 1 \ 1045 : (STR)[1] == '2' ? (VALUE) == 2 \ 1046 : (STR)[1] == '3' ? (VALUE) == 3 \ 1047 : (STR)[1] == '4' ? (VALUE) == 4 \ 1048 : 0) 1049 1050 #define CONST_OK_FOR_K(VALUE, STR) \ 1051 ((STR)[1] == 'u' \ 1052 ? ((STR)[2] == '3' ? CONST_3UBIT_IMM_P (VALUE) \ 1053 : (STR)[2] == '4' ? CONST_4UBIT_IMM_P (VALUE) \ 1054 : (STR)[2] == '5' ? CONST_5UBIT_IMM_P (VALUE) \ 1055 : (STR)[2] == 'h' ? CONST_16UBIT_IMM_P (VALUE) \ 1056 : 0) \ 1057 : (STR)[1] == 's' \ 1058 ? ((STR)[2] == '3' ? CONST_3BIT_IMM_P (VALUE) \ 1059 : (STR)[2] == '4' ? CONST_4BIT_IMM_P (VALUE) \ 1060 : (STR)[2] == '7' ? CONST_7BIT_IMM_P (VALUE) \ 1061 : (STR)[2] == 'h' ? CONST_16BIT_IMM_P (VALUE) \ 1062 : 0) \ 1063 : (STR)[1] == 'n' \ 1064 ? ((STR)[2] == '7' ? CONST_7NBIT_IMM_P (VALUE) \ 1065 : 0) \ 1066 : (STR)[1] == 'N' \ 1067 ? ((STR)[2] == '7' ? CONST_7BIT_IMM_P (-(VALUE)) \ 1068 : 0) \ 1069 : 0) 1070 1071 #define CONST_OK_FOR_M(VALUE, STR) \ 1072 ((STR)[1] == '1' ? (VALUE) == 255 \ 1073 : (STR)[1] == '2' ? (VALUE) == 65535 \ 1074 : 0) 1075 1076 /* The letters I, J, K, L and M in a register constraint string 1077 can be used to stand for particular ranges of immediate operands. 1078 This macro defines what the ranges are. 1079 C is the letter, and VALUE is a constant value. 1080 Return 1 if VALUE is in the range specified by C. 1081 1082 bfin constant operands are as follows 1083 1084 J 2**N 5bit imm scaled 1085 Ks7 -64 .. 63 signed 7bit imm 1086 Ku5 0..31 unsigned 5bit imm 1087 Ks4 -8 .. 7 signed 4bit imm 1088 Ks3 -4 .. 3 signed 3bit imm 1089 Ku3 0 .. 7 unsigned 3bit imm 1090 Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n 1091 */ 1092 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \ 1093 ((C) == 'J' ? (log2constp (VALUE)) \ 1094 : (C) == 'K' ? CONST_OK_FOR_K (VALUE, STR) \ 1095 : (C) == 'L' ? log2constp (~(VALUE)) \ 1096 : (C) == 'M' ? CONST_OK_FOR_M (VALUE, STR) \ 1097 : (C) == 'P' ? CONST_OK_FOR_P (VALUE, STR) \ 1098 : 0) 1099 1100 /*Constant Output Formats */ 1101 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1102 ((C) == 'H' ? 1 : 0) 1103 1104 #define EXTRA_CONSTRAINT(VALUE, D) \ 1105 ((D) == 'Q' ? GET_CODE (VALUE) == SYMBOL_REF : 0) 1106 1107 /* Switch into a generic section. */ 1108 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section 1109 1110 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE) 1111 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX) 1112 1113 typedef enum sections { 1114 CODE_DIR, 1115 DATA_DIR, 1116 LAST_SECT_NM 1117 } SECT_ENUM_T; 1118 1119 typedef enum directives { 1120 LONG_CONST_DIR, 1121 SHORT_CONST_DIR, 1122 BYTE_CONST_DIR, 1123 SPACE_DIR, 1124 INIT_DIR, 1125 LAST_DIR_NM 1126 } DIR_ENUM_T; 1127 1128 #define TEXT_SECTION_ASM_OP ".text;" 1129 #define DATA_SECTION_ASM_OP ".data;" 1130 1131 #define ASM_APP_ON "" 1132 #define ASM_APP_OFF "" 1133 1134 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \ 1135 do { fputs (".global ", FILE); \ 1136 assemble_name (FILE, NAME); \ 1137 fputc (';',FILE); \ 1138 fputc ('\n',FILE); \ 1139 } while (0) 1140 1141 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ 1142 do { \ 1143 fputs (".type ", FILE); \ 1144 assemble_name (FILE, NAME); \ 1145 fputs (", STT_FUNC", FILE); \ 1146 fputc (';',FILE); \ 1147 fputc ('\n',FILE); \ 1148 ASM_OUTPUT_LABEL(FILE, NAME); \ 1149 } while (0) 1150 1151 #define ASM_OUTPUT_LABEL(FILE, NAME) \ 1152 do { assemble_name (FILE, NAME); \ 1153 fputs (":\n",FILE); \ 1154 } while (0) 1155 1156 #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 1157 do { fprintf (FILE, "_%s", NAME); \ 1158 } while (0) 1159 1160 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1161 do { char __buf[256]; \ 1162 fprintf (FILE, "\t.dd\t"); \ 1163 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ 1164 assemble_name (FILE, __buf); \ 1165 fputc (';', FILE); \ 1166 fputc ('\n', FILE); \ 1167 } while (0) 1168 1169 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1170 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) 1171 1172 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ 1173 do { \ 1174 char __buf[256]; \ 1175 fprintf (FILE, "\t.dd\t"); \ 1176 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ 1177 assemble_name (FILE, __buf); \ 1178 fputs (" - ", FILE); \ 1179 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \ 1180 assemble_name (FILE, __buf); \ 1181 fputc (';', FILE); \ 1182 fputc ('\n', FILE); \ 1183 } while (0) 1184 1185 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1186 do { \ 1187 if ((LOG) != 0) \ 1188 fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \ 1189 } while (0) 1190 1191 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1192 do { \ 1193 asm_output_skip (FILE, SIZE); \ 1194 } while (0) 1195 1196 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 1197 do { \ 1198 switch_to_section (data_section); \ 1199 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \ 1200 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \ 1201 ASM_OUTPUT_LABEL (FILE, NAME); \ 1202 fprintf (FILE, "%s %ld;\n", ASM_SPACE, \ 1203 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \ 1204 } while (0) 1205 1206 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1207 do { \ 1208 ASM_GLOBALIZE_LABEL1(FILE,NAME); \ 1209 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0) 1210 1211 #define ASM_COMMENT_START "//" 1212 1213 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1214 do { \ 1215 fprintf (FILE, "\tCALL __mcount;\n"); \ 1216 } while(0) 1217 1218 #undef NO_PROFILE_COUNTERS 1219 #define NO_PROFILE_COUNTERS 1 1220 1221 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO]) 1222 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO]) 1223 1224 extern struct rtx_def *bfin_compare_op0, *bfin_compare_op1; 1225 extern struct rtx_def *bfin_cc_rtx, *bfin_rets_rtx; 1226 1227 /* This works for GAS and some other assemblers. */ 1228 #define SET_ASM_OP ".set " 1229 1230 /* DBX register number for a given compiler register number */ 1231 #define DBX_REGISTER_NUMBER(REGNO) (REGNO) 1232 1233 #define SIZE_ASM_OP "\t.size\t" 1234 1235 #endif /* _BFIN_CONFIG */ 1236