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Searched refs:DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK (Results 1 – 18 of 18) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h3009 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x00000010L macro
H A Ddce_8_0_sh_mask.h1641 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x10 macro
H A Ddce_10_0_sh_mask.h1643 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x10 macro
H A Ddce_11_0_sh_mask.h1591 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x10 macro
H A Ddce_11_2_sh_mask.h1753 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x10 macro
H A Ddce_12_0_sh_mask.h2653 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h143 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK … macro
H A Ddcn_3_0_3_sh_mask.h531 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK … macro
H A Ddcn_1_0_sh_mask.h2017 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK … macro
H A Ddcn_2_1_0_sh_mask.h473 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK … macro
H A Ddcn_3_0_1_sh_mask.h861 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK … macro
H A Ddcn_3_1_2_sh_mask.h793 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK … macro
H A Ddcn_3_1_5_sh_mask.h296 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK … macro
H A Ddcn_3_1_4_sh_mask.h8261 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK … macro
H A Ddcn_3_1_6_sh_mask.h1330 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK … macro
H A Ddcn_3_0_2_sh_mask.h586 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK … macro
H A Ddcn_2_0_0_sh_mask.h591 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK … macro
H A Ddcn_3_0_0_sh_mask.h572 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK … macro