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Searched refs:DDI_BUF_CTL (Results 1 – 9 of 9) sorted by relevance

/openbsd/sys/dev/pci/drm/i915/gvt/
H A Ddisplay.c219 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &= in emulate_monitor_status_change()
222 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
282 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= in emulate_monitor_status_change()
284 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &= in emulate_monitor_status_change()
311 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= in emulate_monitor_status_change()
313 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= in emulate_monitor_status_change()
341 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= in emulate_monitor_status_change()
343 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= in emulate_monitor_status_change()
423 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
449 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
[all …]
H A Dhandlers.c802 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) in ddi_buf_ctl_mmio_write()
821 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); in fdi_auto_training_started()
2342 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2343 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2344 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2345 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2346 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
/openbsd/sys/dev/pci/drm/i915/display/
H A Dintel_ddi.c776 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); in intel_ddi_get_encoder_pipes()
1474 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); in hsw_set_signal_levels()
2831 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); in mtl_disable_ddi_buf()
2834 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); in mtl_disable_ddi_buf()
2858 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); in disable_ddi_buf()
2861 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); in disable_ddi_buf()
3474 intel_de_write(dev_priv, DDI_BUF_CTL(port), in intel_ddi_prepare_link_retrain()
4264 dig_port->dp.output_reg = DDI_BUF_CTL(port); in intel_ddi_init_dp_connector()
4495 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); in intel_ddi_init_hdmi_connector()
4969 intel_de_read(dev_priv, DDI_BUF_CTL(port)) in intel_ddi_init()
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H A Dintel_fdi.c801 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), in hsw_fdi_link_train()
803 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
846 intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0); in hsw_fdi_link_train()
847 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
881 intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0); in hsw_fdi_disable()
H A Dicl_dsi.c513 intel_de_rmw(dev_priv, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE); in gen11_dsi_enable_ddi_buffer()
515 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & in gen11_dsi_enable_ddi_buffer()
1352 intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); in gen11_dsi_disable_port()
1354 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & in gen11_dsi_disable_port()
H A Dintel_tc.c796 intel_de_rmw(i915, DDI_BUF_CTL(port), DDI_BUF_CTL_TC_PHY_OWNERSHIP, in adlp_tc_phy_take_ownership()
810 val = intel_de_read(i915, DDI_BUF_CTL(port)); in adlp_tc_phy_is_owned()
1413 return intel_de_read(i915, DDI_BUF_CTL(dig_port->base.port)) & in tc_port_is_enabled()
H A Dintel_display.c7415 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) in intel_ddi_crt_present()
/openbsd/sys/dev/pci/drm/i915/
H A Dintel_gvt_mmio_table.c513 MMIO_D(DDI_BUF_CTL(PORT_A)); in iterate_generic_mmio()
514 MMIO_D(DDI_BUF_CTL(PORT_B)); in iterate_generic_mmio()
515 MMIO_D(DDI_BUF_CTL(PORT_C)); in iterate_generic_mmio()
516 MMIO_D(DDI_BUF_CTL(PORT_D)); in iterate_generic_mmio()
517 MMIO_D(DDI_BUF_CTL(PORT_E)); in iterate_generic_mmio()
H A Di915_reg.h5728 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) macro